From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) by mx.groups.io with SMTP id smtpd.web11.9308.1614085092459013525 for ; Tue, 23 Feb 2021 04:58:12 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=YClzk7FS; spf=pass (domain: nuviainc.com, ip: 209.85.221.50, mailfrom: leif@nuviainc.com) Received: by mail-wr1-f50.google.com with SMTP id n4so22516754wrx.1 for ; Tue, 23 Feb 2021 04:58:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=rO9os2TLIq5JuuYkE7/BGM1GokKqEyy/D0t0CZ9IF0U=; b=YClzk7FSx6phKrxYCv5oPzdPMfBYG+n2E/0jtihi7eSzO83JD8M53EbBypShLYeTAZ OzDTzoJi/wowpWokLR6RfX5dGdsG9OmfIMUfvrw9ynUO1kwWDPS/OSVMznpNJ3kOUSr4 BesUQQIVMaQQc4YwUsgSLJybyChtDmdf4Xk/5P8JhRPQTIVYNazBD1MC9FhjSa30egP4 2vkzfyjIv/ckus09AAJ8vdiXuTtX++c3DlGQwFKrKu5fUIktjlgSwYj8vBzi5ydHNqH6 CnLQOl8Aaf2lp7LwH34RJu1uQQdAnrXRXj4nRXvh75daWXaJHtLGN4D4XxQ8Y2W1eKsO WtIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=rO9os2TLIq5JuuYkE7/BGM1GokKqEyy/D0t0CZ9IF0U=; b=MXDBtV9f57Oi9PIUfY+7GoILq4umiA2vUNOWuHnaijS9cmmEUld4F6UUD41MSK6BZ5 uL9DNW59VO+M6Tzl0nd3b0bFYO8lRHfmySMXVQDTlMzxXMJB5TrpJv+avpKcVKllN1VW S3quKbfT9q0OsJ6QetwG3T2JKPrcyw9DpeEflcOKclQ9nJ92gLbgUmWy5r3a9qipE4UK qnMEcMAx8143/nF6XWzPqZ/Vzaii5EbJeyArNIzi3eFZNRMgEODnr7eqijG6SouX+xmw xMKEbiWGuDTfCdCLChLkpYmPTNx29IxjSRSAE546TupZtlCNXE1PLoIGAAH5hYSjq3bT txbQ== X-Gm-Message-State: AOAM532SJSJOKVxFusl0YcBFdcqAfNydXvp76yPv01C+YfQ2wBHtUUP/ aHxAF4EaRFZkxtKUMhxwxlIF9Q== X-Google-Smtp-Source: ABdhPJwhXnNMWs+cQpDfip8UKzkn2a9P9eYP1qImasuSz9QiHJH0VlR7+DPrOW79bHkjp1U1qYXgYA== X-Received: by 2002:a5d:4bce:: with SMTP id l14mr26158823wrt.256.1614085091051; Tue, 23 Feb 2021 04:58:11 -0800 (PST) Return-Path: Received: from vanye (cpc1-cmbg19-2-0-cust915.5-4.cable.virginm.net. [82.27.183.148]) by smtp.gmail.com with ESMTPSA id i1sm2378251wmq.12.2021.02.23.04.58.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Feb 2021 04:58:10 -0800 (PST) Date: Tue, 23 Feb 2021 12:58:08 +0000 From: "Leif Lindholm" To: Ming Huang Cc: devel@edk2.groups.io, Ard Biesheuvel , guoheyi@linux.alibaba.com Subject: Re: [PATCH edk2 v2 1/1] ArmPkg/ArmGic: Fix GICR_IPRIORITYR address wrong issue Message-ID: <20210223125808.GA1664@vanye> References: <20210223110642.90020-1-huangming@linux.alibaba.com> MIME-Version: 1.0 In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Tue, Feb 23, 2021 at 13:42:49 +0100, Ard Biesheuvel wrote: > On Tue, 23 Feb 2021 at 12:07, Ming Huang wrote: > > > > The register address of GICR_IPRIORITYR is in SGI_base frame. Add > > IPRIORITY_ADDRESS macro for getting GICR_IPRIORITYR address. Otherwise > > GIC RAS error(Uncorrected software error) may report in ArmGicDxe. > > NOTE: missing sign-off > > Patch seems fine to me > > Tested-by: Ard Biesheuvel # QEMU/kvm guest on ThunderX2 Also looks good in QEMU. Reviewed-by: Leif Lindholm Ming, can you confirm that the contribution conforms to the developer certificate of origin by replyint with your Signed-off-by: ? > > > > > --- > > ArmPkg/Drivers/ArmGic/ArmGicLib.c | 5 ++++- > > 1 file changed, 4 insertions(+), 1 deletion(-) > > > > diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.c b/ArmPkg/Drivers/ArmGic/ArmGicLib.c > > index 8ef32b33a1..b4d3965acb 100644 > > --- a/ArmPkg/Drivers/ArmGic/ArmGicLib.c > > +++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.c > > @@ -30,6 +30,9 @@ > > #define ICENABLER_ADDRESS(base,offset) ((base) + \ > > ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ICENABLER + (4 * offset)) > > > > +#define IPRIORITY_ADDRESS(base,offset) ((base) + \ > > + ARM_GICR_CTLR_FRAME_SIZE + ARM_GIC_ICDIPR + (4 * offset)) > > + > > /** > > * > > * Return whether the Source interrupt index refers to a shared interrupt (SPI) > > @@ -236,7 +239,7 @@ ArmGicSetInterruptPriority ( > > } > > > > MmioAndThenOr32 ( > > - GicCpuRedistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset), > > + IPRIORITY_ADDRESS (GicCpuRedistributorBase, RegOffset), > > ~(0xff << RegShift), > > Priority << RegShift > > ); > > -- > > 2.17.1 > >