From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pg1-f170.google.com (mail-pg1-f170.google.com [209.85.215.170]) by mx.groups.io with SMTP id smtpd.web11.1181.1614130744492915070 for ; Tue, 23 Feb 2021 17:39:04 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@gmail.com header.s=20161025 header.b=aV5hr7GJ; spf=pass (domain: gmail.com, ip: 209.85.215.170, mailfrom: naitaku@gmail.com) Received: by mail-pg1-f170.google.com with SMTP id p21so381112pgl.12 for ; Tue, 23 Feb 2021 17:39:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3Kkfvom8Zxvvfg2EHfB8n1mQ+6zZ9wUogMWDZxRiGpk=; b=aV5hr7GJ6fTLSsye1jDeWCbQZSycRaw3JrXrsTjmq0zt1+oElh2ljEfNklfBUzgoyU sn4yuXxiu41vhAI1wbhlc1fqklQl5EKzxu2tr8IapYKuaTSVFJyrAaW7loneT6nN/Dv1 xqLl1Rldp+dvpFa7VJ4WrXmuAXHcRQ+6rvXP+XjPg00t0ZIg6PALlH7y1+XldvqlfutM AL6zRw02Jpeg+5O9S9kC9vaF1jNrSCkh6oZiTx/jsFhUrXdu6xaxldbtCuaDB10VUw+d 6AJvW+AoRWM7zJRvfplxVfxhjONE4VstLz1H/dRYIh/XfA32pbMPfSX2dXYVtI2zh76+ 3/vg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3Kkfvom8Zxvvfg2EHfB8n1mQ+6zZ9wUogMWDZxRiGpk=; b=Wlvov8jXSpt6U1QauhW/XAD7/MF1vrJ1JGySOSF8SIZhmH/5D1qR1zQNVOtZThETcA aJAXrwfxNT+MxLvKFG/1JlYwGy2EtNgYfmfwZiMJycpB94liQK23EZhxcQ1Y7lLLxLXj f1uiJjM69/EFx4TU4WgVVi1ilc1gh8Fh/MMX+nC4Qevlv1u05W8FsrWZGN0+xjej6mZf jRQ0lGKlxrGYcf1WdPE7f/TNpKUlrLCH4h2c5WYEbd2f8GsEacE9XOeOHMIr8nyf8nAw voOCkVu8qbpZm8UfwQNG3gtKUR9mduS2Fd3I7Vu/4KLjXleu7eAM/m0f69CbUq03fy0W jmOA== X-Gm-Message-State: AOAM532Q0ENL8VNRi4fL5qsqO5Qjclnq7ECfyqUXpP44wyTavRsCXH3L z2lKSdAHIkIM9QPQP7fgHaqWaoFhzV3NODHz X-Google-Smtp-Source: ABdhPJzGm78QXiyOTXEdQsgDimNC/nqueTsjOw8oaewvCQQJhr2yrnl3DHeBzpZbcYeU/4ch5mt+OQ== X-Received: by 2002:aa7:84cb:0:b029:1ed:9b6f:1b6f with SMTP id x11-20020aa784cb0000b02901ed9b6f1b6fmr4903890pfn.57.1614130743552; Tue, 23 Feb 2021 17:39:03 -0800 (PST) Return-Path: Received: from localhost.localdomain ([240d:1e:84:2c00:4c90:1fc7:fcf3:2538]) by smtp.googlemail.com with ESMTPSA id bj9sm340236pjb.49.2021.02.23.17.39.01 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 23 Feb 2021 17:39:03 -0800 (PST) From: "Takuto Naito" To: devel@edk2.groups.io Cc: Takuto Naito , Sai Chaganty , Nate DeSimone , Heng Luo Subject: [PATCH edk2-platforms v1 1/2] TigerlakeSiliconPkg: Fix build error with GCC5 Date: Wed, 24 Feb 2021 10:37:35 +0900 Message-Id: <20210224013736.74815-2-naitaku@gmail.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210224013736.74815-1-naitaku@gmail.com> References: <20210224013736.74815-1-naitaku@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3224 Fix build errors caused by "-Werror=unused-but-set-variable" with GCC5. These build errors occur only with DEBUG target because RELEASE_GCC5_X64_CC_FLAGS has "-Wno-unused-but-set-variable", but DEBUG_GCC5_X64_CC_FLAGS doesn't. Cc: Sai Chaganty Cc: Nate DeSimone Cc: Heng Luo Signed-off-by: Takuto Naito --- .../PcieRp/LibraryPrivate/PcieClientRpLib/PcieClientRpLib.c | 2 -- .../IpBlock/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitLib.c | 5 ----- .../Pch/PchSmiDispatcher/Smm/PchSmiHelperClient.c | 2 -- 3 files changed, 9 deletions(-) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/PcieClientRpLib/PcieClientRpLib.c b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/PcieClientRpLib/PcieClientRpLib.c index 15d295a573..231cb367bc 100644 --- a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/PcieClientRpLib/PcieClientRpLib.c +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/PcieClientRpLib/PcieClientRpLib.c @@ -104,12 +104,10 @@ ConfigureRpLtrOverride ( UINT32 OvrEn; UINT32 OvrVal; BOOLEAN IsCpuPcie; - UINT32 LtrCfgLock; IsCpuPcie = FALSE; OvrEn = 0; OvrVal = 0; - LtrCfgLock = 0; if (DevNum == SA_PEG0_DEV_NUM || DevNum == SA_PEG3_DEV_NUM) { IsCpuPcie = TRUE; diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitLib.c b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitLib.c index faac07c45d..e88abe550f 100644 --- a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitLib.c +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitLib.c @@ -313,8 +313,6 @@ DmarTableUpdate ( UINTN Offset; UINTN StructureLen; UINT64 McD0BaseAddress; - UINT32 GttMmAdr; - UINT64 McD2BaseAddress; UINT16 IgdMode; UINT16 GttMode; UINT32 IgdMemSize; @@ -381,9 +379,6 @@ DmarTableUpdate ( GttMemSize = (1 << GttMode) * (1024) * (1024); } - McD2BaseAddress = PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, IGD_BUS_NUM, IGD_DEV_NUM, IGD_FUN_NUM, 0); - GttMmAdr = (PciSegmentRead32 (McD2BaseAddress + R_SA_IGD_GTTMMADR)) & 0xFFFFFFF0; - DmarTable->RmrrIgd.RmrrHeader.ReservedMemoryRegionBaseAddress = (PciSegmentRead32 (McD0BaseAddress + R_SA_BGSM) & ~(0x01)); DmarTable->RmrrIgd.RmrrHeader.ReservedMemoryRegionLimitAddress = DmarTable->RmrrIgd.RmrrHeader.ReservedMemoryRegionBaseAddress + IgdMemSize + GttMemSize - 1; DEBUG ((DEBUG_INFO, "RMRR Base address IGD %016lX\n", DmarTable->RmrrIgd.RmrrHeader.ReservedMemoryRegionBaseAddress)); diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmiHelperClient.c b/Silicon/Intel/TigerlakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmiHelperClient.c index 7693e76683..3adc05ce89 100644 --- a/Silicon/Intel/TigerlakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmiHelperClient.c +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmiHelperClient.c @@ -29,8 +29,6 @@ GetPcieRpNumber ( OUT UINTN *RpNumber ) { - UINT64 RpBase; - RpBase = PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, RpDev, RpFun, 0); GetPchPcieRpNumber (RpDev, RpFun, RpNumber); } -- 2.30.1