From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web08.6623.1614172355420694373 for ; Wed, 24 Feb 2021 05:12:35 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: chandni.cherukuri@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 07CA91FB; Wed, 24 Feb 2021 05:12:35 -0800 (PST) Received: from usa.arm.com (a074744.blr.arm.com [10.162.17.16]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 523AF3F70D; Wed, 24 Feb 2021 05:12:33 -0800 (PST) From: Chandni Cherukuri To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Sami Mujawar Subject: [edk2-platforms][PATCH V1 1/5] Platform/ARM/Morello: Add Platform library implementation Date: Wed, 24 Feb 2021 18:42:20 +0530 Message-Id: <20210224131224.11481-2-chandni.cherukuri@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210224131224.11481-1-chandni.cherukuri@arm.com> References: <20210224131224.11481-1-chandni.cherukuri@arm.com> From: Anurag Koul This patch adds initial Morello Platform Library support. It includes virtual memory map and helper functions for platform initialization. Co-authored-by: Chandni Cherukuri Signed-off-by: Chandni Cherukuri --- Platform/ARM/Morello/Library/PlatformLib/PlatformLib.inf | 52 ++++++ Platform/ARM/Morello/Include/MorelloPlatform.h | 67 +++++++ Platform/ARM/Morello/Library/PlatformLib/PlatformLib.c | 66 +++++++ Platform/ARM/Morello/Library/PlatformLib/PlatformLibMem.c | 194 ++++++++++++++++++++ Platform/ARM/Morello/Library/PlatformLib/AArch64/Helper.S | 83 +++++++++ 5 files changed, 462 insertions(+) diff --git a/Platform/ARM/Morello/Library/PlatformLib/PlatformLib.inf b/Platform/ARM/Morello/Library/PlatformLib/PlatformLib.inf new file mode 100644 index 000000000000..2066d1f3a3f8 --- /dev/null +++ b/Platform/ARM/Morello/Library/PlatformLib/PlatformLib.inf @@ -0,0 +1,52 @@ +## @file +# +# Copyright (c) 2021, ARM Limited. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = ArmMorelloLib + FILE_GUID = 36853D86-7200-47B4-9408-E962A00963FD + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = ArmPlatformLib + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Platform/ARM/Morello/MorelloPlatform.dec + +[Sources.common] + PlatformLibMem.c + PlatformLib.c + +[Sources.AARCH64] + AArch64/Helper.S | GCC + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmPrimaryCore + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + + gArmMorelloTokenSpaceGuid.PcdDramBlock2Base + + gArmMorelloTokenSpaceGuid.PcdPciBusMin + gArmMorelloTokenSpaceGuid.PcdPciBusMax + gArmMorelloTokenSpaceGuid.PcdPciMmio32Base + gArmMorelloTokenSpaceGuid.PcdPciMmio32Size + gArmMorelloTokenSpaceGuid.PcdPciMmio64Base + gArmMorelloTokenSpaceGuid.PcdPciMmio64Size + gArmMorelloTokenSpaceGuid.PcdPciExpressBaseAddress + gArmMorelloTokenSpaceGuid.PcdPciIoSize + +[Guids] + gEfiHobListGuid ## CONSUMES ## SystemTable + +[Ppis] + gArmMpCoreInfoPpiGuid diff --git a/Platform/ARM/Morello/Include/MorelloPlatform.h b/Platform/ARM/Morello/Include/MorelloPlatform.h new file mode 100644 index 000000000000..f61cfe7f9ee8 --- /dev/null +++ b/Platform/ARM/Morello/Include/MorelloPlatform.h @@ -0,0 +1,67 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef MORELLO_PLATFORM_H__ +#define MORELLO_PLATFORM_H__ + +#define MORELLO_DRAM_BLOCK1_SIZE SIZE_2GB + +// **************************************************************************** +// Platform Memory Map +// **************************************************************************** + +// SubSystem Peripherals - UART0 +#define MORELLO_UART0_BASE 0x2A400000 +#define MORELLO_UART0_SZ SIZE_64KB + +// SubSystem Peripherals - UART1 +#define MORELLO_UART1_BASE 0x2A410000 +#define MORELLO_UART1_SZ SIZE_64KB + +// SubSystem Peripherals - Generic Watchdog +#define MORELLO_GENERIC_WDOG_BASE 0x2A440000 +#define MORELLO_GENERIC_WDOG_SZ SIZE_128KB + +// SubSystem Peripherals - GIC(600) +#define MORELLO_GIC_BASE 0x30000000 +#define MORELLO_GICR_BASE 0x300C0000 +#define MORELLO_GIC_SZ SIZE_256KB +#define MORELLO_GICR_SZ SIZE_1MB + +// SubSystem non-secure SRAM +#define MORELLO_NON_SECURE_SRAM_BASE 0x06000000 +#define MORELLO_NON_SECURE_SRAM_SZ SIZE_64KB + +// AXI Expansion peripherals +#define MORELLO_EXP_PERIPH_BASE 0x1C000000 +#define MORELLO_EXP_PERIPH_BASE_SZ 0x1300000 + +// Platform information structure base address +#define MORELLO_PLAT_INFO_STRUCT_BASE MORELLO_NON_SECURE_SRAM_BASE + +/* + * Platform information structure stored in Non-secure SRAM. Platform + * information are passed from the trusted firmware with the below structure + * format. The elements of MORELLO_PLAT_INFO should be always in sync with + * the lower level firmware. + */ +#pragma pack(1) + +typedef struct { + /*! Local DDR memory size in Bytes */ + UINT64 LocalDdrSize; + /*! Remote DDR memory size in Bytes */ + UINT64 RemoteDdrSize; + /*! Slave count in C2C mode */ + UINT8 SlaveCount; + /*! 0 - Single Chip, 1 - Chip to Chip (C2C) */ + UINT8 Mode; +} MORELLO_PLAT_INFO; + +#pragma pack() + +#endif diff --git a/Platform/ARM/Morello/Library/PlatformLib/PlatformLib.c b/Platform/ARM/Morello/Library/PlatformLib/PlatformLib.c new file mode 100644 index 000000000000..cd06ca5ce53f --- /dev/null +++ b/Platform/ARM/Morello/Library/PlatformLib/PlatformLib.c @@ -0,0 +1,66 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + +STATIC ARM_CORE_INFO mCoreInfoTable[] = { + { 0x0, 0x0 }, // Cluster 0, Core 0 + { 0x0, 0x1 }, // Cluster 0, Core 1 + { 0x1, 0x0 }, // Cluster 1, Core 0 + { 0x1, 0x1 } // Cluster 1, Core 1 +}; + +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + +RETURN_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + return RETURN_SUCCESS; +} + +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + *CoreCount = sizeof (mCoreInfoTable) / sizeof (ARM_CORE_INFO); + *ArmCoreTable = mCoreInfoTable; + return EFI_SUCCESS; +} + +STATIC ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { + PrePeiCoreGetMpCoreInfo +}; + +STATIC EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + } +}; + +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + *PpiListSize = sizeof (gPlatformPpiTable); + *PpiList = gPlatformPpiTable; +} diff --git a/Platform/ARM/Morello/Library/PlatformLib/PlatformLibMem.c b/Platform/ARM/Morello/Library/PlatformLib/PlatformLibMem.c new file mode 100644 index 000000000000..140a6ec79bd3 --- /dev/null +++ b/Platform/ARM/Morello/Library/PlatformLib/PlatformLibMem.c @@ -0,0 +1,194 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include + +// The total number of descriptors, including the final "end-of-table" descriptor. +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 12 + +#if !defined(MDEPKG_NDEBUG) +STATIC CONST CHAR8 *tblAttrDesc[] = { + "UNCACHED_UNBUFFERED ", + "NONSECURE_UNCACHED_UNBUFFERED", + "WRITE_BACK ", + "NONSECURE_WRITE_BACK ", + "WB_NONSHAREABLE ", + "NONSECURE_WB_NONSHAREABLE ", + "WRITE_THROUGH ", + "NONSECURE_WRITE_THROUGH ", + "DEVICE ", + "NONSECURE_DEVICE " +}; +#endif + +#define LOG_MEM(desc) DEBUG (( \ + EFI_D_ERROR, \ + desc, \ + VirtualMemoryTable[Index].PhysicalBase, \ + (VirtualMemoryTable[Index].PhysicalBase + \ + VirtualMemoryTable[Index].Length - 1), \ + VirtualMemoryTable[Index].Length, \ + tblAttrDesc[VirtualMemoryTable[Index].Attributes] \ + )); + +/** + Returns the Virtual Memory Map of the platform. + + This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU + on your platform. + + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing + a Physical-to-Virtual Memory mapping. This array + must be ended by a zero-filled entry. +**/ +VOID +ArmPlatformGetVirtualMemoryMap ( + IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap + ) +{ + UINTN Index = 0; + ARM_MEMORY_REGION_DESCRIPTOR * VirtualMemoryTable; + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; + MORELLO_PLAT_INFO * PlatInfo; + UINT64 DramBlock2Size = 0; + + PlatInfo = (MORELLO_PLAT_INFO *)MORELLO_PLAT_INFO_STRUCT_BASE; + if (PlatInfo->LocalDdrSize > MORELLO_DRAM_BLOCK1_SIZE) + DramBlock2Size = PlatInfo->LocalDdrSize - MORELLO_DRAM_BLOCK1_SIZE; + + if (DramBlock2Size != 0) { + ResourceAttributes = + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED; + + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + FixedPcdGet64 (PcdDramBlock2Base), + DramBlock2Size); + } + + ASSERT (VirtualMemoryMap != NULL); + Index = 0; + + VirtualMemoryTable = AllocatePool (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * + MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + if (VirtualMemoryTable == NULL) { + return; + } + + DEBUG (( + EFI_D_ERROR, + " Memory Map\n----------------------------------------------------------\n" + )); + DEBUG (( + EFI_D_ERROR, + "Description : START - END " \ + "[ SIZE ] { ATTR }\n" + )); + + // SubSystem Peripherals - Generic Watchdog + VirtualMemoryTable[Index].PhysicalBase = MORELLO_GENERIC_WDOG_BASE; + VirtualMemoryTable[Index].VirtualBase = MORELLO_GENERIC_WDOG_BASE; + VirtualMemoryTable[Index].Length = MORELLO_GENERIC_WDOG_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + LOG_MEM ("Generic Watchdog : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n"); + + // SubSystem Peripherals - GIC-600 + VirtualMemoryTable[++Index].PhysicalBase = MORELLO_GIC_BASE; + VirtualMemoryTable[Index].VirtualBase = MORELLO_GIC_BASE; + VirtualMemoryTable[Index].Length = MORELLO_GIC_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + LOG_MEM ("GIC-600 : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n"); + + // SubSystem Peripherals - GICR-600 + VirtualMemoryTable[++Index].PhysicalBase = MORELLO_GICR_BASE; + VirtualMemoryTable[Index].VirtualBase = MORELLO_GICR_BASE; + VirtualMemoryTable[Index].Length = MORELLO_GICR_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + LOG_MEM ("GICR-600 : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n"); + + // SubSystem non-secure SRAM + VirtualMemoryTable[++Index].PhysicalBase = MORELLO_NON_SECURE_SRAM_BASE; + VirtualMemoryTable[Index].VirtualBase = MORELLO_NON_SECURE_SRAM_BASE; + VirtualMemoryTable[Index].Length = MORELLO_NON_SECURE_SRAM_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED; + LOG_MEM ("non-secure SRAM : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n"); + + // SubSystem Pheripherals - UART0 + VirtualMemoryTable[++Index].PhysicalBase = MORELLO_UART0_BASE; + VirtualMemoryTable[Index].VirtualBase = MORELLO_UART0_BASE; + VirtualMemoryTable[Index].Length = MORELLO_UART0_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + LOG_MEM ("UART0 : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n"); + + // DDR Primary + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase); + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase); + VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize); + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK; + LOG_MEM ("DDR Primary : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n"); + + // DDR Secondary + if (DramBlock2Size != 0) { + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdDramBlock2Base); + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdDramBlock2Base); + VirtualMemoryTable[Index].Length = DramBlock2Size; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK; + LOG_MEM ("DDR Secondary : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n"); + } + + // Expansion Peripherals + VirtualMemoryTable[++Index].PhysicalBase = MORELLO_EXP_PERIPH_BASE; + VirtualMemoryTable[Index].VirtualBase = MORELLO_EXP_PERIPH_BASE; + VirtualMemoryTable[Index].Length = MORELLO_EXP_PERIPH_BASE_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + LOG_MEM ("Expansion Peripherals : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n"); + + // PCI Configuration Space + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPciExpressBaseAddress); + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPciExpressBaseAddress); + VirtualMemoryTable[Index].Length = (FixedPcdGet32 (PcdPciBusMax) - + FixedPcdGet32 (PcdPciBusMin) + 1) * + SIZE_1MB; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + LOG_MEM ("PCI Configuration Space : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n"); + + // PCI MMIO32/IO Space + VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdPciMmio32Base); + VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdPciMmio32Base); + VirtualMemoryTable[Index].Length = PcdGet32 (PcdPciMmio32Size) + + PcdGet32 (PcdPciIoSize); + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + LOG_MEM ("PCI MMIO32 & IO Region : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n"); + + // PCI MMIO64 Space + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPciMmio64Base); + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPciMmio64Base); + VirtualMemoryTable[Index].Length = PcdGet64 (PcdPciMmio64Size); + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + LOG_MEM ("PCI MMIO64 Region : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n"); + + // End of Table + VirtualMemoryTable[++Index].PhysicalBase = 0; + VirtualMemoryTable[Index].VirtualBase = 0; + VirtualMemoryTable[Index].Length = 0; + VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0; + + ASSERT ((Index) < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + DEBUG ((DEBUG_INIT, "Virtual Memory Table setup complete.\n")); + + *VirtualMemoryMap = VirtualMemoryTable; +} diff --git a/Platform/ARM/Morello/Library/PlatformLib/AArch64/Helper.S b/Platform/ARM/Morello/Library/PlatformLib/AArch64/Helper.S new file mode 100644 index 000000000000..f6cc087a132c --- /dev/null +++ b/Platform/ARM/Morello/Library/PlatformLib/AArch64/Helper.S @@ -0,0 +1,83 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include + +.text +.align 3 + +GCC_ASM_EXPORT(ArmPlatformPeiBootAction) +GCC_ASM_EXPORT(ArmPlatformGetCorePosition) +GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId) +GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore) + +// +// First platform specific function to be called in the PEI phase +// +// This function is actually the first function called by the PrePi +// or PrePeiCore modules. It allows to retrieve arguments passed to +// the UEFI firmware through the CPU registers. +// +ASM_PFX(ArmPlatformPeiBootAction): + ret + +// +// Return the core position from the value of its MpId register +// +// This function returns core position from the position 0 in the processor. +// This function might be called from assembler before any stack is set. +// +// @return Return the core position +// +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +// With this function: CorePos = (ClusterId * 2) + CoreId +ASM_PFX(ArmPlatformGetCorePosition): + and x1, x0, #ARM_CORE_MASK + and x0, x0, #ARM_CLUSTER_MASK + add x0, x1, x0, LSR #7 + ret + +// +// Return the MpId of the primary core +// +// This function returns the MpId of the primary core. +// This function might be called from assembler before any stack is set. +// +// @return Return the MpId of the primary core +// +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_PFX(ArmPlatformGetPrimaryCoreMpId): + MOV32 (w0, FixedPcdGet32(PcdArmPrimaryCore)) + ret + +// +// Return a non-zero value if the callee is the primary core +// +// This function returns a non-zero value if the callee is the primary core. +// Primary core is the core responsible to initialize hardware and run UEFI. +// This function might be called from assembler before any stack is set. +// +// @return Return a non-zero value if the callee is the primary core. +// +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_PFX(ArmPlatformIsPrimaryCore): + MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCoreMask)) + and x0, x0, x1 + MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCore)) + cmp w0, w1 + cset x0, eq + ret -- 2.17.1