From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.6498.1614172361654057623 for ; Wed, 24 Feb 2021 05:12:41 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: chandni.cherukuri@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4D0731FB; Wed, 24 Feb 2021 05:12:41 -0800 (PST) Received: from usa.arm.com (a074744.blr.arm.com [10.162.17.16]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 584F43F70D; Wed, 24 Feb 2021 05:12:39 -0800 (PST) From: Chandni Cherukuri To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Sami Mujawar Subject: [edk2-platforms][PATCH V1 4/5] Platform/ARM/Morello: Add Configuration Manager for Morello Date: Wed, 24 Feb 2021 18:42:23 +0530 Message-Id: <20210224131224.11481-5-chandni.cherukuri@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210224131224.11481-1-chandni.cherukuri@arm.com> References: <20210224131224.11481-1-chandni.cherukuri@arm.com> This patch implements the configuration manager for Morello platform. It enables support for generating the following ACPI tables for Morello FVP Platform: 1. FADT 2. DSDT 3. GTDT 4. MADT 5. SPCR 6. DBG2 7. PPTT 8. IORT 9. MCFG 10. SSDT Structures have been created to add Common Platform information and FVP/Testchip platform specific information so that the same Dxe is usable for all variants of the platform. Co-authored-by: Jessica Clarke Signed-off-by: Chandni Cherukuri --- Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerFvp.dsc.inc | 16 + Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeFvp.inf | 94 ++ Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h | 304 ++++++ Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerFvp.h | 81 ++ Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/Platform.h | 91 ++ Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c | 1005 ++++++++++++++++++++ Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerFvp.c | 531 +++++++++++ Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/DsdtFvp.asl | 114 +++ Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPciFvp.asl | 130 +++ 9 files changed, 2366 insertions(+) diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerFvp.dsc.inc b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerFvp.dsc.inc new file mode 100644 index 000000000000..71916783c24c --- /dev/null +++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerFvp.dsc.inc @@ -0,0 +1,16 @@ +## @file +# dsc include file for Configuration Manager +# +# Copyright (c) 2021, ARM Limited. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + +[BuildOptions] + +[Components.common] + # Configuration Manager + Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeFvp.inf diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeFvp.inf b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeFvp.inf new file mode 100644 index 000000000000..9137de2dd118 --- /dev/null +++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeFvp.inf @@ -0,0 +1,94 @@ +## @file +# Configuration Manager Dxe +# +# Copyright (c) 2021, ARM Limited. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION = 0x0001001B + BASE_NAME = ConfigurationManagerDxe + FILE_GUID = 6F9C3B47-6F7D-44B6-87E5-4B7F44A60147 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = ConfigurationManagerDxeInitialize + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = AARCH64 +# + +[Sources] + AslTables/DsdtFvp.asl + AslTables/SsdtPciFvp.asl + ConfigurationManagerFvp.c + ConfigurationManager.c + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + DynamicTablesPkg/DynamicTablesPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Platform/ARM/Morello/MorelloPlatform.dec + +[LibraryClasses] + UefiDriverEntryPoint + UefiRuntimeServicesTableLib + +[Protocols] + gEdkiiConfigurationManagerProtocolGuid + +[FixedPcd] + ## PL011 Serial Debug UART + gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase + gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate + gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz + + gArmPlatformTokenSpaceGuid.PL011UartClkInHz + gArmPlatformTokenSpaceGuid.PL011UartInterrupt + + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + + # SBSA Generic Watchdog + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase + gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase + + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate + + gArmMorelloTokenSpaceGuid.PcdVirtioBlkBaseAddress + gArmMorelloTokenSpaceGuid.PcdVirtioBlkSize + gArmMorelloTokenSpaceGuid.PcdVirtioBlkInterrupt + + # PCI + gArmMorelloTokenSpaceGuid.PcdPciBusMin + gArmMorelloTokenSpaceGuid.PcdPciBusMax + gArmMorelloTokenSpaceGuid.PcdPciBusCount + gArmMorelloTokenSpaceGuid.PcdPciIoBase + gArmMorelloTokenSpaceGuid.PcdPciIoSize + gArmMorelloTokenSpaceGuid.PcdPciIoMaxBase + gArmMorelloTokenSpaceGuid.PcdPciIoTranslation + gArmMorelloTokenSpaceGuid.PcdPciMmio32Base + gArmMorelloTokenSpaceGuid.PcdPciMmio32Size + gArmMorelloTokenSpaceGuid.PcdPciMmio32MaxBase + gArmMorelloTokenSpaceGuid.PcdPciMmio32Translation + gArmMorelloTokenSpaceGuid.PcdPciMmio64Base + gArmMorelloTokenSpaceGuid.PcdPciMmio64Size + gArmMorelloTokenSpaceGuid.PcdPciMmio64MaxBase + gArmMorelloTokenSpaceGuid.PcdPciMmio64Translation + gArmMorelloTokenSpaceGuid.PcdPciExpressBaseAddress +[Pcd] + +[Depex] + TRUE diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h new file mode 100644 index 000000000000..b44270639001 --- /dev/null +++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h @@ -0,0 +1,304 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Glossary: + - Cm or CM - Configuration Manager + - Obj or OBJ - Object +**/ + +#ifndef CONFIGURATION_MANAGER_H__ +#define CONFIGURATION_MANAGER_H__ + +/** The configuration manager version. +*/ +#define CONFIGURATION_MANAGER_REVISION CREATE_REVISION (1, 0) + +/** The OEM ID +*/ +#define CFG_MGR_OEM_ID { 'A', 'R', 'M', 'L', 'T', 'D' } +#define CFG_MGR_OEM_REVISION 0x20181101 + +/** A helper macro for mapping a reference token +*/ +#define REFERENCE_TOKEN(Field) \ + (CM_OBJECT_TOKEN)((UINT8*)&CommonPlatformInfo + \ + OFFSET_OF (EDKII_COMMON_PLATFORM_REPOSITORY_INFO, Field)) + +/** A helper macro that constructs the MPID based on the + Aff0, Aff1, Aff2, Aff3 values +*/ +#define GET_MPID3(Aff3, Aff2, Aff1, Aff0) \ + (((Aff3##ULL) << 32) | ((Aff2) << 16) | ((Aff1) << 8) | (Aff0)) + +/** A helper macro for populating the GIC CPU information +*/ +#define GICC_ENTRY( \ + CPUInterfaceNumber, \ + Mpidr, \ + PmuIrq, \ + VGicIrq, \ + GicRedistBase, \ + EnergyEfficiency, \ + SpeIrq, \ + ProximityDomain, \ + ClockDomain \ + ) { \ + CPUInterfaceNumber, /* UINT32 CPUInterfaceNumber */ \ + CPUInterfaceNumber, /* UINT32 AcpiProcessorUid */ \ + EFI_ACPI_6_2_GIC_ENABLED, /* UINT32 Flags */ \ + 0, /* UINT32 ParkingProtocolVersion */ \ + PmuIrq, /* UINT32 PerformanceInterruptGsiv */ \ + 0, /* UINT64 ParkedAddress */ \ + FixedPcdGet64 ( \ + PcdGicInterruptInterfaceBase \ + ), /* UINT64 PhysicalBaseAddress */ \ + 0, /* UINT64 GICV */ \ + 0, /* UINT64 GICH */ \ + VGicIrq, /* UINT32 VGICMaintenanceInterrupt */ \ + GicRedistBase, /* UINT64 GICRBaseAddress */ \ + Mpidr, /* UINT64 MPIDR */ \ + EnergyEfficiency, /* UINT8 ProcessorPowerEfficiencyClass*/ \ + SpeIrq, /* UINT16 SpeOverflowInterrupt */ \ + ProximityDomain, /* UINT32 ProximityDomain */ \ + ClockDomain, /* UINT32 ClockDomain */ \ + EFI_ACPI_6_3_GICC_ENABLED,/* UINT32 Flags */ \ + } + +/** A helper macro for populating the Processor Hierarchy Node flags +*/ +#define PROC_NODE_FLAGS( \ + PhysicalPackage, \ + AcpiProcessorIdValid, \ + ProcessorIsThread, \ + NodeIsLeaf, \ + IdenticalImplementation \ + ) \ + ( \ + PhysicalPackage | \ + (AcpiProcessorIdValid << 1) | \ + (ProcessorIsThread << 2) | \ + (NodeIsLeaf << 3) | \ + (IdenticalImplementation << 4) \ + ) + +/** A helper macro for populating the Cache Type Structure's attributes +*/ +#define CACHE_ATTRIBUTES( \ + AllocationType, \ + CacheType, \ + WritePolicy \ + ) \ + ( \ + AllocationType | \ + (CacheType << 2) | \ + (WritePolicy << 4) \ + ) + +/** A helper macro for returning configuration manager objects +*/ +#define HANDLE_CM_OBJECT(ObjId, CmObjectId, Object, ObjectCount) \ + case ObjId: { \ + CmObject->ObjectId = CmObjectId; \ + CmObject->Size = sizeof (Object); \ + CmObject->Data = (VOID*)&Object; \ + CmObject->Count = ObjectCount; \ + DEBUG (( \ + DEBUG_INFO, \ + #CmObjectId ": Ptr = 0x%p, Size = %d, Count = %d\n", \ + CmObject->Data, \ + CmObject->Size, \ + CmObject->Count \ + )); \ + break; \ + } + +/** A helper macro for returning configuration manager objects + referenced by token +*/ +#define HANDLE_CM_OBJECT_REF_BY_TOKEN( \ + ObjId, \ + CmObjectId, \ + Object, \ + ObjectCount, \ + Token, \ + HandlerProc \ + ) \ + case ObjId: { \ + CmObject->ObjectId = CmObjectId; \ + if (Token == CM_NULL_TOKEN) { \ + CmObject->Size = sizeof (Object); \ + CmObject->Data = (VOID*)&Object; \ + CmObject->Count = ObjectCount; \ + DEBUG (( \ + DEBUG_INFO, \ + #CmObjectId ": Ptr = 0x%p, Size = %d, Count = %d\n", \ + CmObject->Data, \ + CmObject->Size, \ + CmObject->Count \ + )); \ + } else { \ + Status = HandlerProc (This, CmObjectId, Token, CmObject); \ + DEBUG (( \ + DEBUG_INFO, \ + #CmObjectId ": Token = 0x%p, Ptr = 0x%p, Size = %d, Count = %d\n", \ + (VOID*)Token, \ + CmObject->Data, \ + CmObject->Size, \ + CmObject->Count \ + )); \ + } \ + break; \ + } + +/** A helper macro for returning configuration manager objects referenced + by token when the entire platform repository is in scope and the + CM_NULL_TOKEN value is not allowed. +*/ +#define HANDLE_CM_OBJECT_SEARCH_PLAT_REPO( \ + ObjId, \ + CmObjectId, \ + Token, \ + HandlerProc \ + ) \ + case ObjId: { \ + CmObject->ObjectId = CmObjectId; \ + if (Token == CM_NULL_TOKEN) { \ + Status = EFI_INVALID_PARAMETER; \ + DEBUG (( \ + DEBUG_ERROR, \ + #ObjId ": CM_NULL_TOKEN value is not allowed when searching" \ + " the entire platform repository.\n" \ + )); \ + } else { \ + Status = HandlerProc (This, CmObjectId, Token, CmObject); \ + DEBUG (( \ + DEBUG_INFO, \ + #ObjId ": Token = 0x%p, Ptr = 0x%p, Size = %d, Count = %d\n", \ + (VOID*)Token, \ + CmObject->Data, \ + CmObject->Size, \ + CmObject->Count \ + )); \ + } \ + break; \ + } + +/** The number of CPUs +*/ +#define PLAT_CPU_COUNT 4 + +/** The number of platform generic timer blocks +*/ +#define PLAT_GTBLOCK_COUNT 1 + +/** The number of timer frames per generic timer block +*/ +#define PLAT_GTFRAME_COUNT 2 + +/** The number of Processor Hierarchy Nodes + - one package node + - two cluster nodes + - two cores in cluster 0 + - two cores in cluster 1 +*/ +#define PLAT_PROC_HIERARCHY_NODE_COUNT 7 + +/** The number of unique cache structures: + - cluster L3 unified cache + - core L1 instruction cache + - core L1 data cache + - core L2 cache + - slc unified cache +*/ +#define PLAT_CACHE_COUNT 5 + +/** The number of resources private to the cluster + - L3 cache +*/ +#define CLUSTER_RESOURCE_COUNT 1 + +/** The number of resources private to 'core instance + - L1 data cache + - L1 instruction cache + - L2 cache +*/ +#define CORE_RESOURCE_COUNT 3 + +/** The number of resources private to SoC + - slc cache + - Proc Node Id Info +*/ +#define SOC_RESOURCE_COUNT 2 + +/** A structure describing the platform configuration + manager repository information +*/ +typedef struct CommonPlatformRepositoryInfo { + /// Configuration Manager Information + CM_STD_OBJ_CONFIGURATION_MANAGER_INFO CmInfo; + + /// Boot architecture information + CM_ARM_BOOT_ARCH_INFO BootArchInfo; + +#ifdef HEADLESS_PLATFORM + /// Fixed feature flag information + CM_ARM_FIXED_FEATURE_FLAGS FixedFeatureFlags; +#endif + + /// Power management profile information + CM_ARM_POWER_MANAGEMENT_PROFILE_INFO PmProfileInfo; + + /// GIC CPU interface information + CM_ARM_GICC_INFO GicCInfo[PLAT_CPU_COUNT]; + + /// GIC distributor information + CM_ARM_GICD_INFO GicDInfo; + + /// GIC Redistributor information + CM_ARM_GIC_REDIST_INFO GicRedistInfo; + + /// Generic timer information + CM_ARM_GENERIC_TIMER_INFO GenericTimerInfo; + + /// Generic timer block information + CM_ARM_GTBLOCK_INFO GTBlockInfo[PLAT_GTBLOCK_COUNT]; + + /// Generic timer frame information + CM_ARM_GTBLOCK_TIMER_FRAME_INFO GTBlock0TimerInfo[PLAT_GTFRAME_COUNT]; + + /// Watchdog information + CM_ARM_GENERIC_WATCHDOG_INFO Watchdog; + + /** Serial port information for the + serial port console redirection port + */ + CM_ARM_SERIAL_PORT_INFO SpcrSerialPort; + + /// Serial port information for the DBG2 UART port + CM_ARM_SERIAL_PORT_INFO DbgSerialPort; + + // Processor topology information + CM_ARM_PROC_HIERARCHY_INFO ProcHierarchyInfo[PLAT_PROC_HIERARCHY_NODE_COUNT]; + + // Processor Node Id Info + CM_ARM_PROC_NODE_ID_INFO ProcNodeIdInfo; + + + // Cache information + CM_ARM_CACHE_INFO CacheInfo[PLAT_CACHE_COUNT]; + + // Cluster private resources + CM_ARM_OBJ_REF ClusterResources[CLUSTER_RESOURCE_COUNT]; + + // Core private resources + CM_ARM_OBJ_REF CoreResources[CORE_RESOURCE_COUNT]; + + // SoC Resources + CM_ARM_OBJ_REF SocResources[SOC_RESOURCE_COUNT]; + +} EDKII_COMMON_PLATFORM_REPOSITORY_INFO; + +#endif // CONFIGURATION_MANAGER_H__ diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerFvp.h b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerFvp.h new file mode 100644 index 000000000000..be0f02fab1ce --- /dev/null +++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerFvp.h @@ -0,0 +1,81 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Glossary: + - Cm or CM - Configuration Manager + - Obj or OBJ - Object +**/ + +#ifndef FVP_CONFIGURATION_MANAGER_H__ +#define FVP_CONFIGURATION_MANAGER_H__ + +#include "ConfigurationManager.h" + +/** The number of ACPI tables to install +*/ +#define PLAT_ACPI_TABLE_COUNT 10 + +/** A helper macro for mapping a reference token +*/ +#define REFERENCE_TOKEN_FVP(Field) \ + (CM_OBJECT_TOKEN)((UINT8*)&MorelloFvpRepositoryInfo + \ + OFFSET_OF (EDKII_FVP_PLATFORM_REPOSITORY_INFO, Field)) + +/** C array containing the compiled AML template. + These symbols are defined in the auto generated C file + containing the AML bytecode array. +*/ +extern CHAR8 dsdtfvp_aml_code[]; +extern CHAR8 ssdtpcifvp_aml_code[]; + +//Add FVP Platform specific information +typedef struct FvpPlatformRepositoryInfo { + /// List of ACPI tables + CM_STD_OBJ_ACPI_TABLE_INFO CmAcpiTableList[PLAT_ACPI_TABLE_COUNT]; + + /// GIC ITS information + CM_ARM_GIC_ITS_INFO GicItsInfo[2]; + + /// ITS Group node + CM_ARM_ITS_GROUP_NODE ItsGroupInfo[2]; + + /// ITS Identifier array + CM_ARM_ITS_IDENTIFIER ItsIdentifierArray[2]; + + /// SMMUv3 node + CM_ARM_SMMUV3_NODE SmmuV3Info[1]; + + /// PCI Root complex node + CM_ARM_ROOT_COMPLEX_NODE RootComplexInfo[1]; + + /// Array of DeviceID mapping + CM_ARM_ID_MAPPING DeviceIdMapping[2][2]; + + /// PCI configuration space information + CM_ARM_PCI_CONFIG_SPACE_INFO PciConfigInfo[1]; + +} EDKII_FVP_PLATFORM_REPOSITORY_INFO; + +typedef struct PlatformRepositoryInfo { + + EDKII_COMMON_PLATFORM_REPOSITORY_INFO * CommonPlatRepoInfo; + + EDKII_FVP_PLATFORM_REPOSITORY_INFO * FvpPlatRepoInfo; + +} EDKII_PLATFORM_REPOSITORY_INFO; + +extern EDKII_COMMON_PLATFORM_REPOSITORY_INFO CommonPlatformInfo; + +EFI_STATUS +EFIAPI +GetArmNameSpaceObjectPlat ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token OPTIONAL, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ); + +#endif // FVP_CONFIGURATION_MANAGER_H__ diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/Platform.h b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/Platform.h new file mode 100644 index 000000000000..2e5286e892df --- /dev/null +++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/Platform.h @@ -0,0 +1,91 @@ +/** @file + + Copyright (c) 2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef PLATFORM_H__ +#define PLATFORM_H__ + +#define ENABLE_MEM_MAPPED_TIMER + +#ifdef ENABLE_MEM_MAPPED_TIMER +// REFCLK CNTControl +#define MORELLO_SYSTEM_TIMER_BASE_ADDRESS 0x2A430000 +// REFCLK CNTRead +#define MORELLO_CNT_READ_BASE_ADDRESS 0x2A800000 +#else +#define MORELLO_SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF +#define MORELLO_CNT_READ_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF +#endif + +// GT Block Timer +// AP_REFCLK CNTCTL +#define MORELLO_GT_BLOCK_CTL_BASE 0x2A810000 +#define MORELLO_TIMER_FRAMES_COUNT 2 + +// GT Block Timer Frames +// AP_REFCLK_NS CNTBase0 +#define MORELLO_GT_BLOCK_FRAME0_CTL_BASE 0x2A830000 +#define MORELLO_GT_BLOCK_FRAME0_CTL_EL0_BASE 0xFFFFFFFFFFFFFFFF +#define MORELLO_GT_BLOCK_FRAME0_GSIV 92 + +// AP_REFCLK_S CNTBase1 +#define MORELLO_GT_BLOCK_FRAME1_CTL_BASE 0x2A820000 +#define MORELLO_GT_BLOCK_FRAME1_CTL_EL0_BASE 0xFFFFFFFFFFFFFFFF +#define MORELLO_GT_BLOCK_FRAME1_GSIV 91 + +#define GTDT_TIMER_EDGE_TRIGGERED \ + EFI_ACPI_6_3_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE +#define GTDT_TIMER_LEVEL_TRIGGERED 0 +#define GTDT_TIMER_ACTIVE_LOW \ + EFI_ACPI_6_3_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY +#define GTDT_TIMER_ACTIVE_HIGH 0 +#define GTDT_TIMER_SAVE_CONTEXT \ + EFI_ACPI_6_3_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY +#define GTDT_TIMER_LOSE_CONTEXT 0 + +#define MORELLO_GTDT_GTIMER_FLAGS (GTDT_TIMER_LOSE_CONTEXT | \ + GTDT_TIMER_ACTIVE_LOW | \ + GTDT_TIMER_LEVEL_TRIGGERED) + +// GT Block Timer Flags +#define GTX_TIMER_EDGE_TRIGGERED \ + EFI_ACPI_6_3_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE +#define GTX_TIMER_LEVEL_TRIGGERED 0 +#define GTX_TIMER_ACTIVE_LOW \ + EFI_ACPI_6_3_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY +#define GTX_TIMER_ACTIVE_HIGH 0 + +#define MORELLO_GTX_TIMER_FLAGS (GTX_TIMER_ACTIVE_HIGH | \ + GTX_TIMER_LEVEL_TRIGGERED) + +#define GTX_TIMER_SECURE \ + EFI_ACPI_6_3_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER +#define GTX_TIMER_NON_SECURE 0 +#define GTX_TIMER_SAVE_CONTEXT \ + EFI_ACPI_6_3_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY +#define GTX_TIMER_LOSE_CONTEXT 0 + +#define MORELLO_GTX_COMMON_FLAGS_S (GTX_TIMER_SAVE_CONTEXT | \ + GTX_TIMER_SECURE) +#define MORELLO_GTX_COMMON_FLAGS_NS (GTX_TIMER_SAVE_CONTEXT | \ + GTX_TIMER_NON_SECURE) + +// Watchdog +#define SBSA_WATCHDOG_EDGE_TRIGGERED \ + EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE +#define SBSA_WATCHDOG_LEVEL_TRIGGERED 0 +#define SBSA_WATCHDOG_ACTIVE_LOW \ + EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY +#define SBSA_WATCHDOG_ACTIVE_HIGH 0 +#define SBSA_WATCHDOG_SECURE \ + EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER +#define SBSA_WATCHDOG_NON_SECURE 0 + +#define MORELLO_SBSA_WATCHDOG_FLAGS (SBSA_WATCHDOG_NON_SECURE | \ + SBSA_WATCHDOG_ACTIVE_HIGH | \ + SBSA_WATCHDOG_LEVEL_TRIGGERED) + +#endif // PLATFORM_H__ diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c new file mode 100644 index 000000000000..e324cc50853f --- /dev/null +++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c @@ -0,0 +1,1005 @@ +/** @file + Configuration Manager Dxe + + Copyright (c) 2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Glossary: + - Cm or CM - Configuration Manager + - Obj or OBJ - Object +**/ + +#include +#include +#include +#include +#include + +#include "ConfigurationManagerFvp.h" +#include "ConfigurationManager.h" +#include "Platform.h" + +extern EDKII_PLATFORM_REPOSITORY_INFO MorelloRepositoryInfo; + +// The platform configuration repository information. +EDKII_COMMON_PLATFORM_REPOSITORY_INFO CommonPlatformInfo = { + // Configuration Manager information + { CONFIGURATION_MANAGER_REVISION, CFG_MGR_OEM_ID }, + + // Boot architecture information + { EFI_ACPI_6_3_ARM_PSCI_COMPLIANT }, // BootArchFlags + +#ifdef HEADLESS_PLATFORM + // Fixed feature flag information + { EFI_ACPI_6_3_HEADLESS }, // Fixed feature flags +#endif + + // Power management profile information + { EFI_ACPI_6_3_PM_PROFILE_ENTERPRISE_SERVER }, // PowerManagement Profile + + /* GIC CPU Interface information + GIC_ENTRY (CPUInterfaceNumber, Mpidr, PmuIrq, VGicIrq, GicRedistBase, + EnergyEfficiency, SpeIrq, ProximityDomain, ClockDomain) + */ + { + GICC_ENTRY (0, GET_MPID3 (0x0, 0x0, 0x0, 0x0), 23, 25, 0, 0, 21, 0, 0), + GICC_ENTRY (1, GET_MPID3 (0x0, 0x0, 0x1, 0x0), 23, 25, 0, 0, 21, 0, 0), + GICC_ENTRY (2, GET_MPID3 (0x0, 0x1, 0x0, 0x0), 23, 25, 0, 0, 21, 0, 0), + GICC_ENTRY (3, GET_MPID3 (0x0, 0x1, 0x1, 0x0), 23, 25, 0, 0, 21, 0, 0), + }, + + // GIC Distributor Info + { + FixedPcdGet64 (PcdGicDistributorBase), // UINT64 PhysicalBaseAddress + 0, // UINT32 SystemVectorBase + 3 // UINT8 GicVersion + }, + + // GIC Re-Distributor Info + { + // UINT64 DiscoveryRangeBaseAddress + FixedPcdGet64 (PcdGicRedistributorsBase), + // UINT32 DiscoveryRangeLength + SIZE_1MB + }, + + // Generic Timer Info + { + // The physical base address for the counter control frame + MORELLO_SYSTEM_TIMER_BASE_ADDRESS, + // The physical base address for the counter read frame + MORELLO_CNT_READ_BASE_ADDRESS, + // The secure PL1 timer interrupt + FixedPcdGet32 (PcdArmArchTimerSecIntrNum), + // The secure PL1 timer flags + MORELLO_GTDT_GTIMER_FLAGS, + // The non-secure PL1 timer interrupt + FixedPcdGet32 (PcdArmArchTimerIntrNum), + // The non-secure PL1 timer flags + MORELLO_GTDT_GTIMER_FLAGS, + // The virtual timer interrupt + FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), + // The virtual timer flags + MORELLO_GTDT_GTIMER_FLAGS, + // The non-secure PL2 timer interrupt + FixedPcdGet32 (PcdArmArchTimerHypIntrNum), + // The non-secure PL2 timer flags + MORELLO_GTDT_GTIMER_FLAGS + }, + + // Generic Timer Block Information + { + { + // The physical base address for the GT Block Timer structure + MORELLO_GT_BLOCK_CTL_BASE, + // The number of timer frames implemented in the GT Block + MORELLO_TIMER_FRAMES_COUNT, + // Reference token for the GT Block timer frame list + REFERENCE_TOKEN (GTBlock0TimerInfo) + } + }, + + // GT Block Timer Frames + { + // Frame 0 + { + 0, // UINT8 FrameNumber + MORELLO_GT_BLOCK_FRAME0_CTL_BASE, // UINT64 PhysicalAddressCntBase + MORELLO_GT_BLOCK_FRAME0_CTL_EL0_BASE, // UINT64 PhysicalAddressCntEL0Base + MORELLO_GT_BLOCK_FRAME0_GSIV, // UINT32 PhysicalTimerGSIV + MORELLO_GTX_TIMER_FLAGS, // UINT32 PhysicalTimerFlags + 0, // UINT32 VirtualTimerGSIV + 0, // UINT32 VirtualTimerFlags + MORELLO_GTX_COMMON_FLAGS_NS // UINT32 CommonFlags + }, + // Frame 1 + { + 1, // UINT8 FrameNumber + MORELLO_GT_BLOCK_FRAME1_CTL_BASE, // UINT64 PhysicalAddressCntBase + MORELLO_GT_BLOCK_FRAME1_CTL_EL0_BASE, // UINT64 PhysicalAddressCntEL0Base + MORELLO_GT_BLOCK_FRAME1_GSIV, // UINT32 PhysicalTimerGSIV + MORELLO_GTX_TIMER_FLAGS, // UINT32 PhysicalTimerFlags + 0, // UINT32 VirtualTimerGSIV + 0, // UINT32 VirtualTimerFlags + MORELLO_GTX_COMMON_FLAGS_S // UINT32 CommonFlags + }, + }, + + // Watchdog Info + { + // The physical base address of the SBSA Watchdog control frame + FixedPcdGet64 (PcdGenericWatchdogControlBase), + // The physical base address of the SBSA Watchdog refresh frame + FixedPcdGet64 (PcdGenericWatchdogRefreshBase), + // The watchdog interrupt + FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum), + // The watchdog flags + MORELLO_SBSA_WATCHDOG_FLAGS + }, + + // SPCR Serial Port + { + FixedPcdGet64 (PcdSerialRegisterBase), // BaseAddress + FixedPcdGet32 (PL011UartInterrupt), // Interrupt + FixedPcdGet64 (PcdUartDefaultBaudRate), // BaudRate + FixedPcdGet32 (PL011UartClkInHz), // Clock + EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_SBSA_GENERIC_UART // Port subtype + }, + + // Debug Serial Port + { + FixedPcdGet64 (PcdSerialDbgRegisterBase), // BaseAddress + 0, // Interrupt -unused + FixedPcdGet64 (PcdSerialDbgUartBaudRate), // BaudRate + FixedPcdGet32 (PcdSerialDbgUartClkInHz), // Clock + EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_SBSA_GENERIC_UART // Port subtype + }, + + // Processor Hierarchy Nodes + { + // Package + { + // CM_OBJECT_TOKEN Token + REFERENCE_TOKEN (ProcHierarchyInfo[0]), + // UINT32 Flags + PROC_NODE_FLAGS ( + EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL, + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, + EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL + ), + // CM_OBJECT_TOKEN ParentToken + CM_NULL_TOKEN, + // CM_OBJECT_TOKEN GicCToken + CM_NULL_TOKEN, + // UINT32 NoOfPrivateResources + SOC_RESOURCE_COUNT, + // CM_OBJECT_TOKEN PrivateResourcesArrayToken + REFERENCE_TOKEN (SocResources) + }, + + // Cluster0 + { + // CM_OBJECT_TOKEN Token + REFERENCE_TOKEN (ProcHierarchyInfo[1]), + // UINT32 Flags + PROC_NODE_FLAGS ( + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, + EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL + ), + // CM_OBJECT_TOKEN ParentToken + REFERENCE_TOKEN (ProcHierarchyInfo[0]), // -> Package + // CM_OBJECT_TOKEN GicCToken + CM_NULL_TOKEN, + // UINT32 NoOfPrivateResources + CLUSTER_RESOURCE_COUNT, + // CM_OBJECT_TOKEN PrivateResourcesArrayToken + REFERENCE_TOKEN (ClusterResources) + }, + // Cluster1 + { + // CM_OBJECT_TOKEN Token + REFERENCE_TOKEN (ProcHierarchyInfo[2]), + // UINT32 Flags + PROC_NODE_FLAGS ( + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, + EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL + ), + // CM_OBJECT_TOKEN ParentToken + REFERENCE_TOKEN (ProcHierarchyInfo[0]), // -> Package + // CM_OBJECT_TOKEN GicCToken + CM_NULL_TOKEN, + // UINT32 NoOfPrivateResources + CLUSTER_RESOURCE_COUNT, + // CM_OBJECT_TOKEN PrivateResourcesArrayToken + REFERENCE_TOKEN (ClusterResources) + }, + // Cluster0 - Cpu0 + { + // CM_OBJECT_TOKEN Token + REFERENCE_TOKEN (ProcHierarchyInfo[3]), + // UINT32 Flags + PROC_NODE_FLAGS ( + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, + EFI_ACPI_6_3_PPTT_NODE_IS_LEAF, + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_NOT_IDENTICAL + ), + // CM_OBJECT_TOKEN ParentToken + REFERENCE_TOKEN (ProcHierarchyInfo[1]), // -> 'cluster in Cluster0 + // CM_OBJECT_TOKEN GicCToken + REFERENCE_TOKEN (GicCInfo[0]), + // UINT32 NoOfPrivateResources + CORE_RESOURCE_COUNT, + // CM_OBJECT_TOKEN PrivateResourcesArrayToken + REFERENCE_TOKEN (CoreResources) + }, + // Cluster0 - Cpu1 + { + // CM_OBJECT_TOKEN Token + REFERENCE_TOKEN (ProcHierarchyInfo[4]), + // UINT32 Flags + PROC_NODE_FLAGS ( + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, + EFI_ACPI_6_3_PPTT_NODE_IS_LEAF, + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_NOT_IDENTICAL + ), + // CM_OBJECT_TOKEN ParentToken + REFERENCE_TOKEN (ProcHierarchyInfo[1]), // -> 'cluster in Cluster0 + // CM_OBJECT_TOKEN GicCToken + REFERENCE_TOKEN (GicCInfo[1]), + // UINT32 NoOfPrivateResources + CORE_RESOURCE_COUNT, + // CM_OBJECT_TOKEN PrivateResourcesArrayToken + REFERENCE_TOKEN (CoreResources) + }, + // Cluster1 - Cpu0 + { + // CM_OBJECT_TOKEN Token + REFERENCE_TOKEN (ProcHierarchyInfo[3]), + // UINT32 Flags + PROC_NODE_FLAGS ( + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, + EFI_ACPI_6_3_PPTT_NODE_IS_LEAF, + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_NOT_IDENTICAL + ), + // CM_OBJECT_TOKEN ParentToken + REFERENCE_TOKEN (ProcHierarchyInfo[2]), // -> 'cluster in Cluster1 + // CM_OBJECT_TOKEN GicCToken + REFERENCE_TOKEN (GicCInfo[2]), + // UINT32 NoOfPrivateResources + CORE_RESOURCE_COUNT, + // CM_OBJECT_TOKEN PrivateResourcesArrayToken + REFERENCE_TOKEN (CoreResources) + }, + + // Cluster1 - Cpu1 + { + // CM_OBJECT_TOKEN Token + REFERENCE_TOKEN (ProcHierarchyInfo[4]), + // UINT32 Flags + PROC_NODE_FLAGS ( + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, + EFI_ACPI_6_3_PPTT_NODE_IS_LEAF, + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_NOT_IDENTICAL + ), + // CM_OBJECT_TOKEN ParentToken + REFERENCE_TOKEN (ProcHierarchyInfo[2]), // -> 'cluster in Cluster1 + // CM_OBJECT_TOKEN GicCToken + REFERENCE_TOKEN (GicCInfo[3]), + // UINT32 NoOfPrivateResources + CORE_RESOURCE_COUNT, + // CM_OBJECT_TOKEN PrivateResourcesArrayToken + REFERENCE_TOKEN (CoreResources) + }, + }, + + // Processor Node Id Info + { + // A unique token used to identify this object + REFERENCE_TOKEN (ProcNodeIdInfo), + // Vendor ID (as described in ACPI ID registry) + SIGNATURE_32('A', 'R', 'M', 'H'), + // First level unique node ID + 0, + // Second level unique node ID + 0, + // Major revision of the node + 0, + // Minor revision of the node + 0, + // Spin revision of the node + 0 + }, + + // Cache information + { + // 'cluster's L3 cache + { + REFERENCE_TOKEN (CacheInfo[0]), // CM_OBJECT_TOKEN Token + CM_NULL_TOKEN, // CM_OBJECT_TOKEN NextLevelOfCacheToken + SIZE_1MB, // UINT32 Size + 2048, // UINT32 NumberOfSets + 8, // UINT32 Associativity + CACHE_ATTRIBUTES ( // UINT8 Attributes + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ, + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, + EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK + ), + 64 // UINT16 LineSize + }, + // 'core's L1 instruction cache + { + REFERENCE_TOKEN (CacheInfo[1]), // CM_OBJECT_TOKEN Token + REFERENCE_TOKEN (CacheInfo[3]), // CM_OBJECT_TOKEN NextLevelOfCacheToken + SIZE_64KB, // UINT32 Size + 256, // UINT32 NumberOfSets + 4, // UINT32 Associativity + CACHE_ATTRIBUTES ( // UINT8 Attributes + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ, + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, + EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK + ), + 64 // UINT16 LineSize + }, + // 'core's L1 data cache + { + REFERENCE_TOKEN (CacheInfo[2]), // CM_OBJECT_TOKEN Token + REFERENCE_TOKEN (CacheInfo[3]), // CM_OBJECT_TOKEN NextLevelOfCacheToken + SIZE_64KB, // UINT32 Size + 256, // UINT32 NumberOfSets + 4, // UINT32 Associativity + CACHE_ATTRIBUTES ( // UINT8 Attributes + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, + EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK + ), + 64 // UINT16 LineSize + }, + // cores's L2 cache + { + REFERENCE_TOKEN (CacheInfo[3]), // CM_OBJECT_TOKEN Token + CM_NULL_TOKEN, // CM_OBJECT_TOKEN NextLevelOfCacheToken + SIZE_1MB, // UINT32 Size + 2048, // UINT32 NumberOfSets + 8, // UINT32 Associativity + CACHE_ATTRIBUTES ( // UINT8 Attributes + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ, + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, + EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK + ), + 64 // UINT16 LineSize + }, + // slc cache + { + REFERENCE_TOKEN (CacheInfo[4]), // CM_OBJECT_TOKEN Token + CM_NULL_TOKEN, // CM_OBJECT_TOKEN NextLevelOfCacheToken + SIZE_8MB, // UINT32 Size + 4096, // UINT32 NumberOfSets + 16, // UINT32 Associativity + CACHE_ATTRIBUTES ( // UINT8 Attributes + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ, + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, + EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK + ), + 64 // UINT16 LineSize + }, + }, + // Resources private to the 'cluster (shared among cores) in Cluster + { + { REFERENCE_TOKEN (CacheInfo[0]) } // -> 'cluster's L3 cache in Cluster + }, + // Resources private to each individual 'core instance in Cluster + { + { REFERENCE_TOKEN (CacheInfo[1]) }, // -> 'core's L1 I-cache in Cluster + { REFERENCE_TOKEN (CacheInfo[2]) }, // -> 'core's L1 D-cache in Cluster + { REFERENCE_TOKEN (CacheInfo[3]) } // -> 'core's L2 cache in Cluster + }, + + // Resources private to the SoC + { + { REFERENCE_TOKEN (CacheInfo[4]) }, // -> slc for SoC + { REFERENCE_TOKEN (ProcNodeIdInfo) }, // -> ProcNodeIdInfo for SoC + }, +}; + +/** Initialize the Platform Configuration Repository. + + @param [in] This Pointer to the Platform Configuration Repository. + + @retval + EFI_SUCCESS Success +**/ +STATIC +EFI_STATUS +EFIAPI +InitializePlatformRepository ( + IN EDKII_PLATFORM_REPOSITORY_INFO * CONST PlatformRepo + ) +{ + return EFI_SUCCESS; +} + +/** Return a GT Block timer frame info list. + + @param [in] This Pointer to the Configuration Manager Protocol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token A token for identifying the object + @param [in, out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not found. +**/ +EFI_STATUS +EFIAPI +GetGTBlockTimerFrameInfo ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EDKII_COMMON_PLATFORM_REPOSITORY_INFO * PlatformRepo; + + if ((This == NULL) || (CmObject == NULL)) { + ASSERT (This != NULL); + ASSERT (CmObject != NULL); + return EFI_INVALID_PARAMETER; + } + + PlatformRepo = This->PlatRepoInfo->CommonPlatRepoInfo; + + if (Token != (CM_OBJECT_TOKEN)&PlatformRepo->GTBlock0TimerInfo) { + return EFI_NOT_FOUND; + } + + CmObject->ObjectId = CmObjectId; + CmObject->Size = sizeof (PlatformRepo->GTBlock0TimerInfo); + CmObject->Data = (VOID*)&PlatformRepo->GTBlock0TimerInfo; + CmObject->Count = sizeof (PlatformRepo->GTBlock0TimerInfo) / + sizeof (PlatformRepo->GTBlock0TimerInfo[0]); + return EFI_SUCCESS; +} + +/** Return GIC CPU Interface Info. + + @param [in] This Pointer to the Configuration Manager Protocol. + @param [in] CmObjectId The Object ID of the CM object requested + @param [in] SearchToken A unique token for identifying the requested + CM_ARM_GICC_INFO object. + @param [in, out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not found. +**/ +EFI_STATUS +EFIAPI +GetGicCInfo ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN SearchToken, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EDKII_COMMON_PLATFORM_REPOSITORY_INFO * PlatformRepo; + UINT32 TotalObjCount; + UINT32 ObjIndex; + + if ((This == NULL) || (CmObject == NULL)) { + ASSERT (This != NULL); + ASSERT (CmObject != NULL); + return EFI_INVALID_PARAMETER; + } + + PlatformRepo = This->PlatRepoInfo->CommonPlatRepoInfo; + TotalObjCount = PLAT_CPU_COUNT; + + for (ObjIndex = 0; ObjIndex < TotalObjCount; ObjIndex++) { + if (SearchToken == (CM_OBJECT_TOKEN)&PlatformRepo->GicCInfo[ObjIndex]) { + CmObject->ObjectId = CmObjectId; + CmObject->Size = sizeof (PlatformRepo->GicCInfo[ObjIndex]); + CmObject->Data = (VOID*)&PlatformRepo->GicCInfo[ObjIndex]; + CmObject->Count = 1; + return EFI_SUCCESS; + } + } + + return EFI_NOT_FOUND; +} + +/** Return a list of Configuration Manager object references pointed to by the + given input token. + + @param [in] This Pointer to the Configuration Manager Protocol. + @param [in] CmObjectId The Object ID of the CM object requested + @param [in] SearchToken A unique token for identifying the requested + CM_ARM_OBJ_REF list. + @param [in, out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not found. +**/ +EFI_STATUS +EFIAPI +GetCmObjRefs ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN SearchToken, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo; + + if ((This == NULL) || (CmObject == NULL)) { + ASSERT (This != NULL); + ASSERT (CmObject != NULL); + return EFI_INVALID_PARAMETER; + } + + PlatformRepo = This->PlatRepoInfo; + + if (SearchToken == (CM_OBJECT_TOKEN)&PlatformRepo->CommonPlatRepoInfo->ClusterResources) { + CmObject->Size = sizeof (PlatformRepo->CommonPlatRepoInfo->ClusterResources); + CmObject->Data = (VOID*)&PlatformRepo->CommonPlatRepoInfo->ClusterResources; + CmObject->Count = ARRAY_SIZE (PlatformRepo->CommonPlatRepoInfo->ClusterResources); + return EFI_SUCCESS; + } + if (SearchToken == (CM_OBJECT_TOKEN)&PlatformRepo->CommonPlatRepoInfo->CoreResources) { + CmObject->Size = sizeof (PlatformRepo->CommonPlatRepoInfo->CoreResources); + CmObject->Data = (VOID*)&PlatformRepo->CommonPlatRepoInfo->CoreResources; + CmObject->Count = ARRAY_SIZE (PlatformRepo->CommonPlatRepoInfo->CoreResources); + return EFI_SUCCESS; + } + if (SearchToken == (CM_OBJECT_TOKEN)&PlatformRepo->CommonPlatRepoInfo->SocResources) { + CmObject->Size = sizeof (PlatformRepo->CommonPlatRepoInfo->SocResources); + CmObject->Data = (VOID*)&PlatformRepo->CommonPlatRepoInfo->SocResources; + CmObject->Count = ARRAY_SIZE (PlatformRepo->CommonPlatRepoInfo->SocResources); + return EFI_SUCCESS; + } + + return EFI_NOT_FOUND; +} + +/** Return a standard namespace object. + + @param [in] This Pointer to the Configuration Manager Protocol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token An optional token identifying the object. If + unused this must be CM_NULL_TOKEN. + @param [in, out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not found. +**/ +EFI_STATUS +EFIAPI +GetStandardNameSpaceObject ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token OPTIONAL, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EFI_STATUS Status; + EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo; + + Status = EFI_SUCCESS; + if ((This == NULL) || (CmObject == NULL)) { + ASSERT (This != NULL); + ASSERT (CmObject != NULL); + return EFI_INVALID_PARAMETER; + } + PlatformRepo = This->PlatRepoInfo; + + switch (GET_CM_OBJECT_ID (CmObjectId)) { + HANDLE_CM_OBJECT ( + EStdObjCfgMgrInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->CmInfo, + 1 + ); + HANDLE_CM_OBJECT ( + EStdObjAcpiTableList, + CmObjectId, + PlatformRepo->FvpPlatRepoInfo->CmAcpiTableList, + (sizeof (PlatformRepo->FvpPlatRepoInfo->CmAcpiTableList) / + sizeof (PlatformRepo->FvpPlatRepoInfo->CmAcpiTableList[0])) + ); + default: { + Status = EFI_NOT_FOUND; + DEBUG (( + DEBUG_ERROR, + "ERROR: Object 0x%x. Status = %r\n", + CmObjectId, + Status + )); + break; + } + } + + return Status; +} + +/** Return an ARM namespace object. + + @param [in] This Pointer to the Configuration Manager Protocol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token An optional token identifying the object. If + unused this must be CM_NULL_TOKEN. + @param [in, out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not found. +**/ +EFI_STATUS +EFIAPI +GetArmNameSpaceObject ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token OPTIONAL, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EFI_STATUS Status; + EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo; + UINT32 GicRedistCount; + UINT32 GicCpuCount; + UINT32 ProcHierarchyInfoCount; + + Status = EFI_SUCCESS; + if ((This == NULL) || (CmObject == NULL)) { + ASSERT (This != NULL); + ASSERT (CmObject != NULL); + return EFI_INVALID_PARAMETER; + } + PlatformRepo = This->PlatRepoInfo; + + GicRedistCount = 1; + GicCpuCount = PLAT_CPU_COUNT; + ProcHierarchyInfoCount = PLAT_PROC_HIERARCHY_NODE_COUNT; + + Status = GetArmNameSpaceObjectPlat (This, CmObjectId, Token, CmObject); + + if (Status == EFI_NOT_FOUND) { + + Status = EFI_SUCCESS; + + switch (GET_CM_OBJECT_ID (CmObjectId)) { + HANDLE_CM_OBJECT ( + EArmObjBootArchInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->BootArchInfo, + 1 + ); + +#ifdef HEADLESS_PLATFORM + HANDLE_CM_OBJECT ( + EArmObjFixedFeatureFlags, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->FixedFeatureFlags, + 1 + ); +#endif + HANDLE_CM_OBJECT ( + EArmObjPowerManagementProfileInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->PmProfileInfo, + 1 + ); + HANDLE_CM_OBJECT ( + EArmObjGenericTimerInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->GenericTimerInfo, + 1 + ); + HANDLE_CM_OBJECT ( + EArmObjPlatformGenericWatchdogInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->Watchdog, + 1 + ); + HANDLE_CM_OBJECT ( + EArmObjPlatformGTBlockInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->GTBlockInfo, + (sizeof (PlatformRepo->CommonPlatRepoInfo->GTBlockInfo) / + sizeof (PlatformRepo->CommonPlatRepoInfo->GTBlockInfo[0])) + ); + HANDLE_CM_OBJECT_REF_BY_TOKEN ( + EArmObjGTBlockTimerFrameInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->GTBlock0TimerInfo, + (sizeof (PlatformRepo->CommonPlatRepoInfo->GTBlock0TimerInfo) / + sizeof (PlatformRepo->CommonPlatRepoInfo->GTBlock0TimerInfo[0])), + Token, + GetGTBlockTimerFrameInfo + ); + HANDLE_CM_OBJECT_REF_BY_TOKEN ( + EArmObjGicCInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->GicCInfo, + GicCpuCount, + Token, + GetGicCInfo + ); + HANDLE_CM_OBJECT ( + EArmObjGicDInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->GicDInfo, + 1 + ); + HANDLE_CM_OBJECT ( + EArmObjGicRedistributorInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->GicRedistInfo, + GicRedistCount + ); + HANDLE_CM_OBJECT ( + EArmObjSerialConsolePortInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->SpcrSerialPort, + 1 + ); + HANDLE_CM_OBJECT ( + EArmObjSerialDebugPortInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->DbgSerialPort, + 1 + ); + HANDLE_CM_OBJECT ( + EArmObjProcHierarchyInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->ProcHierarchyInfo, + ProcHierarchyInfoCount + ); + HANDLE_CM_OBJECT ( + EArmObjProcNodeIdInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->ProcNodeIdInfo, + 1 + ); + HANDLE_CM_OBJECT ( + EArmObjCacheInfo, + CmObjectId, + PlatformRepo->CommonPlatRepoInfo->CacheInfo, + ARRAY_SIZE (PlatformRepo->CommonPlatRepoInfo->CacheInfo) + ); + HANDLE_CM_OBJECT_SEARCH_PLAT_REPO ( + EArmObjCmRef, + CmObjectId, + Token, + GetCmObjRefs + ); + default: { + Status = EFI_NOT_FOUND; + DEBUG (( + DEBUG_INFO, + "INFO: Object 0x%x. Status = %r\n", + CmObjectId, + Status + )); + break; + } + }//switch + } + return Status; +} + +/** Return an OEM namespace object. + + @param [in] This Pointer to the Configuration Manager Protocol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token An optional token identifying the object. If + unused this must be CM_NULL_TOKEN. + @param [in, out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not found. +**/ +EFI_STATUS +EFIAPI +GetOemNameSpaceObject ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token OPTIONAL, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EFI_STATUS Status; + + Status = EFI_SUCCESS; + if ((This == NULL) || (CmObject == NULL)) { + ASSERT (This != NULL); + ASSERT (CmObject != NULL); + return EFI_INVALID_PARAMETER; + } + + switch (GET_CM_OBJECT_ID (CmObjectId)) { + default: { + Status = EFI_NOT_FOUND; + DEBUG (( + DEBUG_ERROR, + "ERROR: Object 0x%x. Status = %r\n", + CmObjectId, + Status + )); + break; + } + } + + return Status; +} + +/** The GetObject function defines the interface implemented by the + Configuration Manager Protocol for returning the Configuration + Manager Objects. + + @param [in] This Pointer to the Configuration Manager Protocol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token An optional token identifying the object. If + unused this must be CM_NULL_TOKEN. + @param [in, out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not found. +**/ +EFI_STATUS +EFIAPI +MorelloPlatformGetObject ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token OPTIONAL, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EFI_STATUS Status; + + if ((This == NULL) || (CmObject == NULL)) { + ASSERT (This != NULL); + ASSERT (CmObject != NULL); + return EFI_INVALID_PARAMETER; + } + + switch (GET_CM_NAMESPACE_ID (CmObjectId)) { + case EObjNameSpaceStandard: + Status = GetStandardNameSpaceObject (This, CmObjectId, Token, CmObject); + break; + case EObjNameSpaceArm: + Status = GetArmNameSpaceObject (This, CmObjectId, Token, CmObject); + break; + case EObjNameSpaceOem: + Status = GetOemNameSpaceObject (This, CmObjectId, Token, CmObject); + break; + default: { + Status = EFI_INVALID_PARAMETER; + DEBUG (( + DEBUG_ERROR, + "ERROR: Unknown Namespace Object = 0x%x. Status = %r\n", + CmObjectId, + Status + )); + break; + } + } + + return Status; +} + +/** The SetObject function defines the interface implemented by the + Configuration Manager Protocol for updating the Configuration + Manager Objects. + + @param [in] This Pointer to the Configuration Manager Protocol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token An optional token identifying the object. If + unused this must be CM_NULL_TOKEN. + @param [in] CmObject Pointer to the Configuration Manager Object + descriptor describing the Object. + + @retval EFI_UNSUPPORTED This operation is not supported. +**/ +EFI_STATUS +EFIAPI +MorelloPlatformSetObject ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token OPTIONAL, + IN CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + return EFI_UNSUPPORTED; +} + +/** A structure describing the configuration manager protocol interface. +*/ +STATIC +CONST +EDKII_CONFIGURATION_MANAGER_PROTOCOL MorelloPlatformConfigManagerProtocol = { + CREATE_REVISION(1,0), + MorelloPlatformGetObject, + MorelloPlatformSetObject, + &MorelloRepositoryInfo +}; + +/** + Entrypoint of Configuration Manager Dxe. + + @param ImageHandle + @param SystemTable + + @return EFI_SUCCESS + @return EFI_LOAD_ERROR + @return EFI_OUT_OF_RESOURCES + +**/ +EFI_STATUS +EFIAPI +ConfigurationManagerDxeInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE * SystemTable + ) +{ + EFI_STATUS Status; + + // Initialize the Platform Configuration Repository before installing the + // Configuration Manager Protocol + Status = InitializePlatformRepository ( + MorelloPlatformConfigManagerProtocol.PlatRepoInfo + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "ERROR: Failed to initialize the Platform Configuration Repository." \ + " Status = %r\n", + Status + )); + } + + Status = gBS->InstallProtocolInterface ( + &ImageHandle, + &gEdkiiConfigurationManagerProtocolGuid, + EFI_NATIVE_INTERFACE, + (VOID*)&MorelloPlatformConfigManagerProtocol + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "ERROR: Failed to get Install Configuration Manager Protocol." \ + " Status = %r\n", + Status + )); + goto error_handler; + } + +error_handler: + return Status; +} diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerFvp.c b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerFvp.c new file mode 100644 index 000000000000..b50a9db220a2 --- /dev/null +++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerFvp.c @@ -0,0 +1,531 @@ +/** @file + Configuration Manager Dxe + + Copyright (c) 2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Glossary: + - Cm or CM - Configuration Manager + - Obj or OBJ - Object +**/ + +#include +#include +#include +#include +#include +#include +#include + +#include "ConfigurationManagerFvp.h" +#include "Platform.h" + +EDKII_FVP_PLATFORM_REPOSITORY_INFO MorelloFvpRepositoryInfo = { + // ACPI Table List + { + // FADT Table + { + EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_REVISION, + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdFadt), + NULL + }, + // GTDT Table + { + EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION, + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdGtdt), + NULL + }, + // MADT Table + { + EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION, + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdMadt), + NULL + }, + // SPCR Table + { + EFI_ACPI_6_3_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION, + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdSpcr), + NULL + }, + // DSDT Table + { + EFI_ACPI_6_3_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE, + 0, // Unused + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdDsdt), + (EFI_ACPI_DESCRIPTION_HEADER*)dsdtfvp_aml_code + }, + // DBG2 Table + { + EFI_ACPI_6_3_DEBUG_PORT_2_TABLE_SIGNATURE, + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION, + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdDbg2), + NULL + }, + // PPTT Table + { + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION, + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdPptt), + NULL + }, + // IORT Table + { + EFI_ACPI_6_3_IO_REMAPPING_TABLE_SIGNATURE, + EFI_ACPI_IO_REMAPPING_TABLE_REVISION, + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdIort), + NULL + }, + // PCI MCFG Table + { + EFI_ACPI_6_3_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION, + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdMcfg), + NULL, + }, + // SSDT table describing the PCI root complex + { + EFI_ACPI_6_3_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE, + 0, // Unused + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdSsdt), + (EFI_ACPI_DESCRIPTION_HEADER*)ssdtpcifvp_aml_code + }, + }, + + // GIC ITS + { + // GIC ITS - PCIe TCU + { + // The GIC ITS ID. + 0, + // The physical address for the Interrupt Translation Service + 0x30060000, + //Proximity Domain + 0 + }, + // GIC ITS - PCIe RC + { + // The GIC ITS ID. + 1, + // The physical address for the Interrupt Translation Service + 0x300A0000, + //Proximity Domain + 0 + }, + }, + + // ITS group node + { + { + // Reference token for this Iort node + REFERENCE_TOKEN_FVP (ItsGroupInfo[0]), + // The number of ITS identifiers in the ITS node. + 1, + // Reference token for the ITS identifier array + REFERENCE_TOKEN_FVP (ItsIdentifierArray[0]) + }, + { + // Reference token for this Iort node + REFERENCE_TOKEN_FVP (ItsGroupInfo[1]), + // The number of ITS identifiers in the ITS node. + 1, + // Reference token for the ITS identifier array + REFERENCE_TOKEN_FVP (ItsIdentifierArray[1]) + }, + }, + + // ITS identifier array + { + { + // The ITS Identifier + 0 + }, + { + // The ITS Identifier + 1 + }, + }, + + // SMMUv3 Node + { + { + // Reference token for this Iort node + REFERENCE_TOKEN_FVP (SmmuV3Info[0]), + // Number of ID mappings + 2, + // Reference token for the ID mapping array + REFERENCE_TOKEN_FVP (DeviceIdMapping[0][0]), + // SMMU Base Address + 0x4F400000, + // SMMU flags + EFI_ACPI_IORT_SMMUv3_FLAG_COHAC_OVERRIDE, + // VATOS address + 0, + // Model + EFI_ACPI_IORT_SMMUv3_MODEL_GENERIC, + // GSIV of the Event interrupt if SPI based + 0x10B, + // PRI Interrupt if SPI based + 0, + // GERR interrupt if GSIV based + 0x10D, + // Sync interrupt if GSIV based + 0x10C, + // Proximity domain flag, ignored in this case + 0, + // Index into the array of ID mapping, ignored as SMMU + // control interrupts are GSIV based + 1 + }, + }, + + // Root Complex node info + { + { + // Reference token for this Iort node + REFERENCE_TOKEN_FVP (RootComplexInfo[0]), + // Number of ID mappings + 1, + // Reference token for the ID mapping array + REFERENCE_TOKEN_FVP (DeviceIdMapping[1][0]), + + // Memory access properties : Cache coherent attributes + EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, + // Memory access properties : Allocation hints + 0, + // Memory access properties : Memory access flags + 0, + // ATS attributes + EFI_ACPI_IORT_ROOT_COMPLEX_ATS_SUPPORTED, + // PCI segment number + 0, + // Memory address size limit + 42 + }, + }, + + // Array of Device ID mappings + { + // DeviceIdMapping[0][0] - [0][1] + { + /* Mapping SMMUv3 -> ITS Group + */ + + // SMMUv3 device ID mapping + { + // Input base + 0x0, + // Number of input IDs + 0x0000FFFF, + // Output Base + 0x0, + // Output reference + REFERENCE_TOKEN_FVP (ItsGroupInfo[1]), + // Flags + 0 + }, + // SMMUv3 device ID mapping + { + // Input base + 0x0, + // Number of input IDs + 0x00000001, + // Output Base + 0x0, + // Output reference token for the IORT node + REFERENCE_TOKEN_FVP (ItsGroupInfo[0]), + // Flags + EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE + } + }, + // DeviceIdMapping[1][0] + { + // Mapping for RootComplex -> SMMUv3 + + // Device ID mapping for Root complex node + { + // Input base + 0x0, + // Number of input IDs + 0x0000FFFF, + // Output Base + 0x0, + // Output reference + REFERENCE_TOKEN_FVP (SmmuV3Info[0]), + // Flags + 0 + }, + }, + }, + // PCI Configuration Space Info + { + // PCIe ECAM + { + FixedPcdGet64 (PcdPciExpressBaseAddress), // Base Address + 0x0, // Segment Group Number + FixedPcdGet32 (PcdPciBusMin), // Start Bus Number + FixedPcdGet32 (PcdPciBusMax) // End Bus Number + }, + }, +}; + +EDKII_PLATFORM_REPOSITORY_INFO MorelloRepositoryInfo = { + &CommonPlatformInfo, + &MorelloFvpRepositoryInfo +}; + +/** Return a device Id mapping array. + + @param [in] This Pointer to the Configuration Manager Protocol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token A token for identifying the object + @param [out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not found. +*/ +EFI_STATUS +EFIAPI +GetDeviceIdMappingArray ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EDKII_FVP_PLATFORM_REPOSITORY_INFO * PlatformRepo; + UINTN Count; + + if ((This == NULL) || (CmObject == NULL)) { + ASSERT (This != NULL); + ASSERT (CmObject != NULL); + return EFI_INVALID_PARAMETER; + } + + PlatformRepo = This->PlatRepoInfo->FvpPlatRepoInfo; + + DEBUG ((DEBUG_INFO, "DeviceIdMapping - Token = %p\n")); + + if (Token == (CM_OBJECT_TOKEN)&PlatformRepo->DeviceIdMapping[0][0]) { + Count = 2; + DEBUG ((DEBUG_INFO, "DeviceIdMapping - Found DeviceIdMapping[0][0]\n")); + } else if (Token == + (CM_OBJECT_TOKEN)&PlatformRepo->DeviceIdMapping[1][0]) { + Count = 1; + DEBUG ((DEBUG_INFO, "DeviceIdMapping - Found DeviceIdMapping[1][0]\n")); + } else { + DEBUG ((DEBUG_INFO, "DeviceIdMapping - Not Found\n")); + return EFI_NOT_FOUND; + } + + CmObject->Data = (VOID*)Token; + CmObject->ObjectId = CmObjectId; + CmObject->Count = Count; + CmObject->Size = Count * sizeof (CM_ARM_ID_MAPPING); + + return EFI_SUCCESS; +} + +/** Return an ITS identifier array. + + @param [in] This Pointer to the Configuration Manager Protocol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token A token for identifying the object + @param [out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not found. +*/ +EFI_STATUS +EFIAPI +GetItsIdentifierArray ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EDKII_FVP_PLATFORM_REPOSITORY_INFO * PlatformRepo; + UINTN Count; + UINTN Index; + + if ((This == NULL) || (CmObject == NULL)) { + ASSERT (This != NULL); + ASSERT (CmObject != NULL); + return EFI_INVALID_PARAMETER; + } + + PlatformRepo = This->PlatRepoInfo->FvpPlatRepoInfo; + + Count = sizeof (PlatformRepo->ItsIdentifierArray) / + sizeof (PlatformRepo->ItsIdentifierArray[0]); + + for (Index = 0; Index < Count; Index++) { + if (Token == (CM_OBJECT_TOKEN)&PlatformRepo->ItsIdentifierArray[Index]) { + CmObject->ObjectId = CmObjectId; + CmObject->Size = sizeof (PlatformRepo->ItsIdentifierArray[0]); + CmObject->Data = (VOID*)&PlatformRepo->ItsIdentifierArray[Index]; + CmObject->Count = 1; + return EFI_SUCCESS; + } + } + + return EFI_NOT_FOUND; +} + +/** Return an ITS group info. + + @param [in] This Pointer to the Configuration Manager Protocol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token A token for identifying the object + @param [out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not found. +*/ +EFI_STATUS +EFIAPI +GetItsGroupInfo ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EDKII_FVP_PLATFORM_REPOSITORY_INFO * PlatformRepo; + UINTN Count; + UINTN Index; + + if ((This == NULL) || (CmObject == NULL)) { + ASSERT (This != NULL); + ASSERT (CmObject != NULL); + return EFI_INVALID_PARAMETER; + } + + PlatformRepo = This->PlatRepoInfo->FvpPlatRepoInfo; + + Count = sizeof (PlatformRepo->ItsGroupInfo) / + sizeof (PlatformRepo->ItsGroupInfo[0]); + + for (Index = 0; Index < Count; Index++) { + if (Token == (CM_OBJECT_TOKEN)&PlatformRepo->ItsGroupInfo[Index]) { + CmObject->ObjectId = CmObjectId; + CmObject->Size = sizeof (PlatformRepo->ItsGroupInfo[0]); + CmObject->Data = (VOID*)&PlatformRepo->ItsGroupInfo[Index]; + CmObject->Count = 1; + return EFI_SUCCESS; + } + } + + return EFI_NOT_FOUND; +} + +/** Return an ARM namespace object. + + @param [in] This Pointer to the Configuration Manager Protocol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token An optional token identifying the object. If + unused this must be CM_NULL_TOKEN. + @param [in, out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not found. +**/ +EFI_STATUS +EFIAPI +GetArmNameSpaceObjectPlat ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token OPTIONAL, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EFI_STATUS Status; + EDKII_FVP_PLATFORM_REPOSITORY_INFO * PlatformRepo; + + Status = EFI_SUCCESS; + if ((This == NULL) || (CmObject == NULL)) { + ASSERT (This != NULL); + ASSERT (CmObject != NULL); + return EFI_INVALID_PARAMETER; + } + PlatformRepo = This->PlatRepoInfo->FvpPlatRepoInfo; + + switch (GET_CM_OBJECT_ID (CmObjectId)) { + HANDLE_CM_OBJECT ( + EArmObjGicItsInfo, + CmObjectId, + PlatformRepo->GicItsInfo, + (sizeof (PlatformRepo->GicItsInfo) / + sizeof (PlatformRepo->GicItsInfo[0])) + ); + + HANDLE_CM_OBJECT ( + EArmObjSmmuV3, + CmObjectId, + PlatformRepo->SmmuV3Info[0], + 1 + ); + + HANDLE_CM_OBJECT_REF_BY_TOKEN ( + EArmObjItsGroup, + CmObjectId, + PlatformRepo->ItsGroupInfo, + (sizeof (PlatformRepo->ItsGroupInfo) / + sizeof (PlatformRepo->ItsGroupInfo[0])), + Token, + GetItsGroupInfo + ); + + HANDLE_CM_OBJECT_REF_BY_TOKEN ( + EArmObjGicItsIdentifierArray, + CmObjectId, + PlatformRepo->ItsIdentifierArray, + (sizeof (PlatformRepo->ItsIdentifierArray) / + sizeof (PlatformRepo->ItsIdentifierArray[0])), + Token, + GetItsIdentifierArray + ); + + HANDLE_CM_OBJECT ( + EArmObjRootComplex, + CmObjectId, + PlatformRepo->RootComplexInfo[0], + 1 + ); + + HANDLE_CM_OBJECT_REF_BY_TOKEN ( + EArmObjIdMappingArray, + CmObjectId, + PlatformRepo->DeviceIdMapping, + (sizeof (PlatformRepo->DeviceIdMapping) / + sizeof (PlatformRepo->DeviceIdMapping[0][0])), + Token, + GetDeviceIdMappingArray + ); + + HANDLE_CM_OBJECT ( + EArmObjPciConfigSpaceInfo, + CmObjectId, + PlatformRepo->PciConfigInfo[0], + 1 + ); + default: { + Status = EFI_NOT_FOUND; + break; + } + }//switch + return Status; +} diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/DsdtFvp.asl b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/DsdtFvp.asl new file mode 100644 index 000000000000..f048f81d0646 --- /dev/null +++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/DsdtFvp.asl @@ -0,0 +1,114 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2021, ARM Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "ConfigurationManager.h" + +DefinitionBlock("Dsdt.aml", "DSDT", 1, "ARMLTD", "MORELLO", CFG_MGR_OEM_REVISION) { + Scope(_SB) { + Device(CP00) { // Cluster 0, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 0) + Name(_STA, 0xF) + } + + Device(CP01) { // Cluster 0, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 1) + Name(_STA, 0xF) + } + + Device(CP02) { // Cluster 1, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 2) + Name(_STA, 0xF) + } + + Device(CP03) { // Cluster 1, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 3) + Name(_STA, 0xF) + } + + // UART PL011 + Device(COM0) { + Name(_HID, "ARMH0011") + Name(_CID, "ARMH0011") + Name(_UID, 0) + + Method(_STA) { + Return(0xF) + } + + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x2A400000, 0x1000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 95 } + }) + } + + // VIRTIO DISK + Device(VR00) { + Name(_HID, "LNRO0005") + Name(_UID, 0) + + Name(_CRS, ResourceTemplate() { + Memory32Fixed( + ReadWrite, + FixedPcdGet32(PcdVirtioBlkBaseAddress), + FixedPcdGet32(PcdVirtioBlkSize) + ) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { + FixedPcdGet32(PcdVirtioBlkInterrupt) + } + }) + } + + // VIRTIO NET + Device(VR01) { + Name(_HID, "LNRO0005") + Name(_UID, 1) + + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x1C180000, 0x00000200) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 134 } + }) + } + + // VIRTIO RANDOM + Device(VR02) { + Name(_HID, "LNRO0005") + Name(_UID, 2) + + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x1C190000, 0x00000200) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 133 } + }) + } + + // VIRTIO P9 Device + Device(VR03) { + Name(_HID, "LNRO0005") + Name(_UID, 3) + + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x1C1A0000, 0x00000200) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 135 } + }) + } + + // SMC91X + Device(NET0) { + Name(_HID, "LNRO0003") + Name(_UID, 0) + + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x1D100000, 0x00001000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 130 } + }) + } + } // Scope(_SB) +} diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPciFvp.asl b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPciFvp.asl new file mode 100644 index 000000000000..bdf2f06aed69 --- /dev/null +++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPciFvp.asl @@ -0,0 +1,130 @@ +/** @file + Secondary System Description Table (SSDT) + + Copyright (c) 2021, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "ConfigurationManager.h" + +#define LNK_DEVICE(Unique_Id, Link_Name, irq) \ + Device(Link_Name) { \ + Name(_HID, EISAID("PNP0C0F")) \ + Name(_UID, Unique_Id) \ + Name(_PRS, ResourceTemplate() { \ + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { irq } \ + }) \ + Method (_CRS, 0) { Return (_PRS) } \ + Method (_SRS, 1) { } \ + Method (_DIS) { } \ +} + +#define PRT_ENTRY(Address, Pin, Link) \ + Package (4) { \ + Address, /* uses the same format as _ADR */ \ + Pin, /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC, 3-INTD) */ \ + Link, /* Interrupt allocated via Link device */ \ + Zero /* global system interrupt number (no used) */ \ +} + +#define ROOT_PRT_ENTRY(Pin, Link) PRT_ENTRY(0x0000FFFF, Pin, Link) // Device 0 for Bridge. + +DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "MORELLO", + CFG_MGR_OEM_REVISION) +{ + Scope (_SB) { + // + // PCI Root Complex + // + LNK_DEVICE(1, LNKA, 201) + LNK_DEVICE(2, LNKB, 202) + LNK_DEVICE(3, LNKC, 203) + LNK_DEVICE(4, LNKD, 204) + + // PCI Root Complex + Device(PCI0) { + Name (_HID, EISAID("PNP0A08")) // PCI Express Root Bridge + Name (_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge + Name (_SEG, Zero) // PCI Segment Group number + Name (_BBN, Zero) // PCI Base Bus Number + Name (_CCA, 1) // Cache Coherency Attribute + + // Root Complex 0 + Device (RP0) { + Name(_ADR, 0xF0000000) // Dev 0, Func 0 + } + + // PCI Routing Table + Name(_PRT, Package() { + ROOT_PRT_ENTRY(0, LNKA), // INTA + ROOT_PRT_ENTRY(1, LNKB), // INTB + ROOT_PRT_ENTRY(2, LNKC), // INTC + ROOT_PRT_ENTRY(3, LNKD), // INTD + }) + + // Root complex resources + Method (_CRS, 0, Serialized) { + Name (RBUF, ResourceTemplate () { + WordBusNumber ( // Bus numbers assigned to this root + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + 0, // AddressGranularity + FixedPcdGet32 (PcdPciBusMin), // AddressMinimum - Minimum Bus Number + FixedPcdGet32 (PcdPciBusMax), // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + FixedPcdGet32 (PcdPciBusCount) // RangeLength - Number of Busses + ) + + DWordMemory ( // 32-bit BAR Windows + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x00000000, // Granularity + FixedPcdGet32 (PcdPciMmio32Base), // Min Base Address + FixedPcdGet32 (PcdPciMmio32MaxBase), // Max Base Address + FixedPcdGet32 (PcdPciMmio32Translation), // Translate + FixedPcdGet32 (PcdPciMmio32Size) // Length + ) + + QWordMemory ( // 64-bit BAR Windows + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x00000000, // Granularity + FixedPcdGet64 (PcdPciMmio64Base), // Min Base Address + FixedPcdGet64 (PcdPciMmio64MaxBase), // Max Base Address + FixedPcdGet64 (PcdPciMmio64Translation), // Translate + FixedPcdGet64 (PcdPciMmio64Size) // Length + ) + + DWordIo ( // IO window + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x00000000, // Granularity + FixedPcdGet32 (PcdPciIoBase), // Min Base Address + FixedPcdGet32 (PcdPciIoMaxBase), // Max Base Address + FixedPcdGet32 (PcdPciIoTranslation), // Translate + FixedPcdGet32 (PcdPciIoSize), // Length + , + , + , + TypeTranslation + ) + }) // Name(RBUF) + Return (RBUF) + } // Method (_CRS) + } // Device (PCI0) + } // _SB +} // DB -- 2.17.1