From: "Leif Lindholm" <leif@nuviainc.com>
To: Ashish Singhal <ashishsingha@nvidia.com>
Cc: ardb+tianocore@kernel.org, devel@edk2.groups.io
Subject: Re: [PATCH] ArmPkg/ArmGicLib: Fix setting GICv3 Interrupt Priority
Date: Thu, 25 Feb 2021 20:07:23 +0000 [thread overview]
Message-ID: <20210225200723.GQ1664@vanye> (raw)
In-Reply-To: <0284001c888f058e59853e725d4f02a00840506a.1614273201.git.ashishsingha@nvidia.com>
Hi Ashish,
This bug was already reported by Ming (who also submitted a patch).
Tracked in https://bugzilla.tianocore.org/show_bug.cgi?id=3236, should
make it into the tree tomorrow.
Thank you for your contribution!
/
Leif
On Thu, Feb 25, 2021 at 10:19:46 -0700, Ashish Singhal wrote:
> Incorrect register is being set for configuring interrupt
> priority. Correct register is located in SGI space and not
> in RD space.
>
> Signed-off-by: Ashish Singhal <ashishsingha@nvidia.com>
> ---
> ArmPkg/Drivers/ArmGic/ArmGicLib.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.c b/ArmPkg/Drivers/ArmGic/ArmGicLib.c
> index 8ef32b3..3c0bee6 100644
> --- a/ArmPkg/Drivers/ArmGic/ArmGicLib.c
> +++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.c
> @@ -236,7 +236,7 @@ ArmGicSetInterruptPriority (
> }
>
> MmioAndThenOr32 (
> - GicCpuRedistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),
> + GicCpuRedistributorBase + ARM_GICR_CTLR_FRAME_SIZE + ARM_GIC_ICDIPR + (4 * RegOffset),
> ~(0xff << RegShift),
> Priority << RegShift
> );
> --
> 2.7.4
>
next prev parent reply other threads:[~2021-02-25 20:07 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-25 17:19 [PATCH] ArmPkg/ArmGicLib: Fix setting GICv3 Interrupt Priority Ashish Singhal
2021-02-25 20:07 ` Leif Lindholm [this message]
2021-03-01 14:48 ` Ashish Singhal
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