From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) by mx.groups.io with SMTP id smtpd.web09.1158.1614283647055783833 for ; Thu, 25 Feb 2021 12:07:27 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=u0MgVkqz; spf=pass (domain: nuviainc.com, ip: 209.85.221.42, mailfrom: leif@nuviainc.com) Received: by mail-wr1-f42.google.com with SMTP id 7so6483181wrz.0 for ; Thu, 25 Feb 2021 12:07:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=DE5Hi4q/b1IW/ecYkpFhNVfXy2UZG8mNKt5y10YydHo=; b=u0MgVkqz3puAVQMsiR5bL6dRwJWrmWjwiUvQJuA8EbwTQ8s8prS5vfuUANUcDS2Hh5 gZFZVq8pJf4NQpXWM6SNO1V5i7p7krIgu6NqK9V6QDnoPVRfkUVQ6kPTMJigpO1ZlYaP rbOGjjegNVCIqTM/oOz20X/7hfR0rCGr0mAu5eeKJRQmwTqR52BWaGt8tbgDCp7RJ3Dc 0CEYpsc4gK9+T+zt6oToGi3A12XAJAu2MmhCl8V5qQkXoP85G/CroTCWeZqiICxso95u K35YjVcSSFTx3NcPIElIgND17d2EzucwXULbpScXQicx1flEm99n1f7Xep8elBuIns1g ga5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=DE5Hi4q/b1IW/ecYkpFhNVfXy2UZG8mNKt5y10YydHo=; b=eeLud8CQlp0vYPBkjfwbIFP1LGqGggtfvaTTZci3Xyyq3HDIdB8PCmmn/FqEt5VWtt 8v+Qzq5HAf+3MU3ietC/tvjZIuASUOWNYvYrTGodFsuwP7N9X2AuKVWzMGHRn7P6ZjbR gkgatinDzFYGQJkMv3ySbhR+jXifzLM2s5IMxVS9+Duna8z3o/C4ZntFnRGvhQpkxyTt TLJoJKVxz2P9jPYCDcKMPwTNfPek2KzUbPd6JNtsYaiFWBciOBvz5g2uuOZdVUjkrZBj +WJq5RqX5+VBr0LmvuWn/T7Uoc545+aq/58GXLu7B8VduqcbW43D71eVLJm/UEQ1KN1M G0jg== X-Gm-Message-State: AOAM533RLM/oQH5SdGJm6GdAbyuvhcHzjJaCohB2lZEnrMTY9w4uQG52 Ruk+2EiFEwVyvdm9Ki9KHho7Jg== X-Google-Smtp-Source: ABdhPJzPZ86gW4OaztHeqTFNbHwMFwBZYQ1Ut0lxw1e+RGmhW4joO7gMAh/zP96HHrvedu6zPOAn0w== X-Received: by 2002:a5d:4e05:: with SMTP id p5mr5078587wrt.273.1614283645527; Thu, 25 Feb 2021 12:07:25 -0800 (PST) Return-Path: Received: from vanye (cpc1-cmbg19-2-0-cust915.5-4.cable.virginm.net. [82.27.183.148]) by smtp.gmail.com with ESMTPSA id h22sm9832314wmb.36.2021.02.25.12.07.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Feb 2021 12:07:25 -0800 (PST) Date: Thu, 25 Feb 2021 20:07:23 +0000 From: "Leif Lindholm" To: Ashish Singhal Cc: ardb+tianocore@kernel.org, devel@edk2.groups.io Subject: Re: [PATCH] ArmPkg/ArmGicLib: Fix setting GICv3 Interrupt Priority Message-ID: <20210225200723.GQ1664@vanye> References: <0284001c888f058e59853e725d4f02a00840506a.1614273201.git.ashishsingha@nvidia.com> MIME-Version: 1.0 In-Reply-To: <0284001c888f058e59853e725d4f02a00840506a.1614273201.git.ashishsingha@nvidia.com> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hi Ashish, This bug was already reported by Ming (who also submitted a patch). Tracked in https://bugzilla.tianocore.org/show_bug.cgi?id=3236, should make it into the tree tomorrow. Thank you for your contribution! / Leif On Thu, Feb 25, 2021 at 10:19:46 -0700, Ashish Singhal wrote: > Incorrect register is being set for configuring interrupt > priority. Correct register is located in SGI space and not > in RD space. > > Signed-off-by: Ashish Singhal > --- > ArmPkg/Drivers/ArmGic/ArmGicLib.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.c b/ArmPkg/Drivers/ArmGic/ArmGicLib.c > index 8ef32b3..3c0bee6 100644 > --- a/ArmPkg/Drivers/ArmGic/ArmGicLib.c > +++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.c > @@ -236,7 +236,7 @@ ArmGicSetInterruptPriority ( > } > > MmioAndThenOr32 ( > - GicCpuRedistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset), > + GicCpuRedistributorBase + ARM_GICR_CTLR_FRAME_SIZE + ARM_GIC_ICDIPR + (4 * RegOffset), > ~(0xff << RegShift), > Priority << RegShift > ); > -- > 2.7.4 >