[edk2-platforms][PATCH V2 0/2] Enable SMMUv3 for Arm SGI/RD platforms

[edk2-platforms][PATCH V2 0/2] Enable SMMUv3 for Arm SGI/RD platforms

[Vivek Kumar Gautam]

Arm's SMMUv3 present in various SGI/RD platforms provides address
translation support for devices such as the ones present over PCIe.
SMMUv3 also supports Address Translation Service (ATS) and Page
Request Interface (PRI) to work with PCIe devices.
ATS allows PCIe devices to request translation from a translation
agent such as SMMU, and then cache these translation in their private
cache called as Address Translation Cache (ATC).
Devices that support PRI can also enable the feature when ATS is
enabled as ATS is a prerequisite for PRI.

The I/O topology on SGI/RD platforms includes I/O devices (or PCIe
devices) connected to a SMMU-v3, and an GIC ITS block that facilitates
interrupt translations for message signaled interrupts. A typical view
of this topology is as below -

	 ---------------       ------------       ------------
	|  PCIe device  |---->|  SMMUv3    |---->|   ITS      |
	| (RequesterID) |     | (StreamID) |     | (DeviceID) |
	 ---------------       ------------       ------------

This patch series adds the SMMU-v3 node in iort table, and sets up the
connection between these iort nodes to forward the traffic in the right
manner.

Changes since v1:
- Addressed review comments given by Sami:
  - Replaced __builtin_offsetof() with OFFSET_OF() as suggested by Sami.
  - Updated the commit message for patches.

Vivek Gautam (2):
  Platform/Sgi: Add smmu-v3 node in the iort acpi table
  Platform/Sgi: Enable ATS mode over PCI root complex

 Platform/ARM/SgiPkg/AcpiTables/Iort.aslc | 60 ++++++++++++++++++--
 1 file changed, 55 insertions(+), 5 deletions(-)

-- 
2.17.1

[edk2-platforms][PATCH V2 1/2] Platform/Sgi: Add smmu-v3 node in the iort acpi table

[Vivek Kumar Gautam]

Arm's SMMU-v3 present in various SGI/RD platforms provides address
translation support for devices such as the ones present over PCIe
bus. SMMU-v3 also supports Address Translation Service (ATS) and
Page Request Interface (PRI) to work with PCIe devices.

The overall system topology looks as below:
	 ---------------       ------------       ------------
	|  PCIe device  |---->|  SMMUv3    |---->|   ITS      |
	| (RequesterID) |     | (StreamID) |     | (DeviceID) |
	 ---------------       ------------       ------------

SMMU-v3 accepts requests coming from the PCIe device, and forwards
the traffic to the GIC ITS block that can provide the translation for
interrupts coming from LPI sources.

Add this generic SMMUv3 type node in the iort table and setup the
rid->stream-id->device-id mapping accordingly.

Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
---
 Platform/ARM/SgiPkg/AcpiTables/Iort.aslc | 58 ++++++++++++++++++--
 1 file changed, 54 insertions(+), 4 deletions(-)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/Iort.aslc b/Platform/ARM/SgiPkg/AcpiTables/Iort.aslc
index 58ec31ddc837..ce8eefc585ea 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/Iort.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/Iort.aslc
@@ -20,6 +20,12 @@ typedef struct
   UINT32                                   ItsIdentifiers;
 } ARM_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE;
 
+typedef struct
+{
+  EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE     SmmuNode;
+  EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE       SmmuIdMap[2];
+} ARM_EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE;
+
 typedef struct
 {
   EFI_ACPI_6_0_IO_REMAPPING_RC_NODE        RcNode;
@@ -30,6 +36,7 @@ typedef struct
 {
   EFI_ACPI_6_0_IO_REMAPPING_TABLE          Header;
   ARM_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE   ItsNode;
+  ARM_EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE SmmuNode;
   ARM_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE    RcNode;
 } ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE;
 
@@ -45,7 +52,7 @@ ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort =
        ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE,
        EFI_ACPI_IO_REMAPPING_TABLE_REVISION
      ),
-     2,  // NumNodes
+     3,  // NumNodes
      sizeof (EFI_ACPI_6_0_IO_REMAPPING_TABLE),  // NodeOffset
      0,  // Reserved
   },
@@ -62,9 +69,52 @@ ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort =
         0,  // NumIdMappings
         0,  // IdReference
       },
-      1,    // GIC ITS Identifiers
+      1,    // ITS count
+    },
+    0,      // GIC ITS Identifiers
+  },
+  // SMMU
+  {
+    // EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE
+    {
+      // EFI_ACPI_6_0_IO_REMAPPING_NODE
+      {
+        EFI_ACPI_IORT_TYPE_SMMUv3, // Type
+        sizeof (ARM_EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE), // Length
+        2, // Revision
+        0, // Reserved
+        2, // NumIdMapping
+        OFFSET_OF (ARM_EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE, SmmuIdMap), // IdReference
+      },
+      0x4F000000, // Base address
+      EFI_ACPI_IORT_SMMUv3_FLAG_COHAC_OVERRIDE, // Flags
+      0,   // Reserved
+      0,   // VATOS address
+      EFI_ACPI_IORT_SMMUv3_MODEL_GENERIC, // SMMUv3 Model
+      260, // Event
+      0,   // Pri
+      262, // Gerror
+      261, // Sync
+      0,   // Proximity domain
+      1,   // DevIDMappingIndex
+    },
+    // EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE
+    {
+      {
+        0x0000, // InputBase
+        0xffff, // NumIds
+        0x0000, // OutputBase
+        OFFSET_OF (ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE, ItsNode), // OutputReference
+        0, // Flags
+      },
+      {
+        0x0,     // InputBase
+        0x1,     // NumIds
+        0x10000, // OutputBase
+        OFFSET_OF (ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE, ItsNode), // OutputReference
+        EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, // Flags
+      },
     },
-    0,
   },
   // ARM_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE
   {
@@ -91,7 +141,7 @@ ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort =
       0x0000,  // InputBase
       0xffff,  // NumIds
       0x0000,  // OutputBase
-      OFFSET_OF (ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE, ItsNode),  // OutputReference
+      OFFSET_OF (ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE, SmmuNode),  // OutputReference
       0,       // Flags
     }
   }
-- 
2.17.1

[edk2-platforms][PATCH V2 2/2] Platform/Sgi: Enable ATS mode over PCI root complex

[Vivek Kumar Gautam]

Enable Address Translation Service (ATS) support for the PCI root
complex listed in the iort table.
ATS allows PCIe devices to request an address translation before
starting the dma transaction, so that devices can cache these
translations in their private cache that is called as Address
Translation Cache (ATC).
Devices that support Page Request Interface (PRI) can also enable
the feature when ATS is enabled as ATS is a prerequisite for PRI.

Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
---
 Platform/ARM/SgiPkg/AcpiTables/Iort.aslc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/Iort.aslc b/Platform/ARM/SgiPkg/AcpiTables/Iort.aslc
index ce8eefc585ea..fcc28a71c82e 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/Iort.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/Iort.aslc
@@ -133,7 +133,7 @@ ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort =
       0,  // AllocationHints
       0,  // Reserved
       0,  // MemoryAccessFlags
-      EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED,  // AtsAttribute
+      EFI_ACPI_IORT_ROOT_COMPLEX_ATS_SUPPORTED,    // AtsAttribute
       0x0,                                         // PciSegmentNumber
     },
     // EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE
-- 
2.17.1