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From: "Shashi Mallela" <shashi.mallela@linaro.org>
To: leif@nuviainc.com, ardb+tianocore@kernel.org, graeme@nuviainc.com
Cc: devel@edk2.groups.io
Subject: [PATCH v1 2/2] Silicon/Qemu: Update MADT with GICv3 ITS info
Date: Thu, 11 Mar 2021 15:19:17 -0500	[thread overview]
Message-ID: <20210311201917.28939-3-shashi.mallela@linaro.org> (raw)
In-Reply-To: <20210311201917.28939-1-shashi.mallela@linaro.org>

For Qemu sbsa-ref platforms,to enable detection of GICv3 Interrupt
Translation Service capability in the ACPI MADT,the GIC ITS structure
is created with the relevant values for each of its fields.The
existing MADT functionality is extended to include GIC ITS structure
presence as well.

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Graeme Gregory <graeme@nuviainc.com>
Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
---
 Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf                   |  1 +
 Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf |  1 +
 Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h     | 10 ++++++++++
 Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c   | 10 +++++++++-
 4 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
index 9be34488eb7a..de58987b0044 100644
--- a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
@@ -34,6 +34,7 @@ [Packages]
 [FixedPcd]
   gArmTokenSpaceGuid.PcdGicDistributorBase
   gArmTokenSpaceGuid.PcdGicRedistributorsBase
+  gArmTokenSpaceGuid.PcdGicItsBase
 
   gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
   gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
index c6de685bd2c4..adf682fac564 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
@@ -59,6 +59,7 @@ [FixedPcd]
   gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
   gArmTokenSpaceGuid.PcdGicDistributorBase
   gArmTokenSpaceGuid.PcdGicRedistributorsBase
+  gArmTokenSpaceGuid.PcdGicItsBase
 
   gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId
   gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision
diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
index 4d5b05ba17c6..5f9e9477bf6a 100644
--- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
+++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
@@ -37,6 +37,16 @@
    SBSAQEMU_MADT_GICR_SIZE                   /* DiscoveryRangeLength */        \
    }
 
+// Macro for MADT GIC ITS Structure
+#define SBSAQEMU_MADT_GIC_ITS_INIT() {                                         \
+   EFI_ACPI_6_0_GIC_ITS,                     /* Type */                        \
+   sizeof (EFI_ACPI_6_0_GIC_ITS_STRUCTURE),  /* Length */                      \
+   EFI_ACPI_RESERVED_WORD,                   /* Reserved */                    \
+   0,                                        /* GicItsId */                    \
+   FixedPcdGet64 (PcdGicItsBase),            /* PhysicalBaseAddress */         \
+   EFI_ACPI_RESERVED_DWORD                   /* Reserved */                    \
+   }
+
 #define SBSAQEMU_ACPI_SCOPE_OP_MAX_LENGTH 5
 
 #define SBSAQEMU_ACPI_SCOPE_NAME         { '_', 'S', 'B', '_' }
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
index b8901030ecd0..4e0d24ed6608 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
@@ -91,6 +91,9 @@ AddMadtTable (
  // Initialize GIC Redistributor Structure
   EFI_ACPI_6_0_GICR_STRUCTURE Gicr = SBSAQEMU_MADT_GICR_INIT();
 
+  // Initialize GIC ITS Structure
+  EFI_ACPI_6_0_GIC_ITS_STRUCTURE Gic_Its = SBSAQEMU_MADT_GIC_ITS_INIT();
+
   // Get CoreCount which was determined eariler after parsing device tree
   NumCores = PcdGet32 (PcdCoreCount);
 
@@ -98,7 +101,8 @@ AddMadtTable (
   TableSize = sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER) +
                (sizeof (EFI_ACPI_6_0_GIC_STRUCTURE) * NumCores) +
                sizeof (EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE) +
-               sizeof (EFI_ACPI_6_0_GICR_STRUCTURE);
+               sizeof (EFI_ACPI_6_0_GICR_STRUCTURE) +
+               sizeof (EFI_ACPI_6_0_GIC_ITS_STRUCTURE);
 
   Status = gBS->AllocatePages (
                   AllocateAnyPages,
@@ -138,6 +142,10 @@ AddMadtTable (
   CopyMem (New, &Gicr, sizeof (EFI_ACPI_6_0_GICR_STRUCTURE));
   New += sizeof (EFI_ACPI_6_0_GICR_STRUCTURE);
 
+  // GIC ITS Structure
+  CopyMem (New, &Gic_Its, sizeof (EFI_ACPI_6_0_GIC_ITS_STRUCTURE));
+  New += sizeof (EFI_ACPI_6_0_GIC_ITS_STRUCTURE);
+
   AcpiPlatformChecksum ((UINT8*) PageAddress, TableSize);
 
   Status = AcpiTable->InstallAcpiTable (
-- 
2.27.0


  parent reply	other threads:[~2021-03-11 20:19 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-11 20:19 [PATCH v1 0/2] Add GIC ITS entry to MADT Shashi Mallela
2021-03-11 20:19 ` [PATCH v1 1/2] Platform/Qemu/SbsaQemu/SbsaQemu.dsc: define GICv3 ITS base address Shashi Mallela
2021-03-11 20:19 ` Shashi Mallela [this message]
  -- strict thread matches above, loose matches on Subject: below --
2021-03-12  0:59 [PATCH v1 0/2] Add GIC ITS entry to MADT Shashi Mallela
2021-03-12  0:59 ` [PATCH v1 2/2] Silicon/Qemu: Update MADT with GICv3 ITS info Shashi Mallela

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