* [PATCH v1 0/2] Add GIC ITS entry to MADT @ 2021-03-11 20:19 Shashi Mallela 2021-03-11 20:19 ` [PATCH v1 1/2] Platform/Qemu/SbsaQemu/SbsaQemu.dsc: define GICv3 ITS base address Shashi Mallela 2021-03-11 20:19 ` [PATCH v1 2/2] Silicon/Qemu: Update MADT with GICv3 ITS info Shashi Mallela 0 siblings, 2 replies; 4+ messages in thread From: Shashi Mallela @ 2021-03-11 20:19 UTC (permalink / raw) To: leif, ardb+tianocore, graeme; +Cc: devel This patchset implements ACPI MADT functionality extension to include the GICv3 ITS functionality. This enables devices to use message signalled LPI interrupts in addition to SPIs,PPIs supported on ARM SBSA reference qemu platforms. Shashi Mallela (2): Platform/Qemu/SbsaQemu/SbsaQemu.dsc: define GICv3 ITS base address Silicon/Qemu: Update MADT with GICv3 ITS info Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 1 + Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 1 + Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 1 + Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h | 10 ++++++++++ Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 10 +++++++++- 5 files changed, 22 insertions(+), 1 deletion(-) -- 2.27.0 ^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH v1 1/2] Platform/Qemu/SbsaQemu/SbsaQemu.dsc: define GICv3 ITS base address 2021-03-11 20:19 [PATCH v1 0/2] Add GIC ITS entry to MADT Shashi Mallela @ 2021-03-11 20:19 ` Shashi Mallela 2021-03-11 20:19 ` [PATCH v1 2/2] Silicon/Qemu: Update MADT with GICv3 ITS info Shashi Mallela 1 sibling, 0 replies; 4+ messages in thread From: Shashi Mallela @ 2021-03-11 20:19 UTC (permalink / raw) To: leif, ardb+tianocore, graeme; +Cc: devel Update the new pcd setting (defined in edk2 ArmPkg) with the base address of GICv3 Interrupt Translation Service.For Qemu sbsa-ref platforms,this enables the detection of GIC ITS capability within the GIC ITS structure of ACPI MADT. Cc: Leif Lindholm <leif@nuviainc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Graeme Gregory <graeme@nuviainc.com> Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org> --- Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 1 + 1 file changed, 1 insertion(+) diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc index c1f8a4696560..58da89232800 100644 --- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc @@ -404,6 +404,7 @@ [PcdsFixedAtBuild.common] # gArmTokenSpaceGuid.PcdGicDistributorBase|0x40060000 gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x40080000 + gArmTokenSpaceGuid.PcdGicItsBase|0x44090000 ## Default Terminal Type ## 0-PCANSI, 1-VT100, 2-VT00+, 3-UTF8, 4-TTYTERM -- 2.27.0 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v1 2/2] Silicon/Qemu: Update MADT with GICv3 ITS info 2021-03-11 20:19 [PATCH v1 0/2] Add GIC ITS entry to MADT Shashi Mallela 2021-03-11 20:19 ` [PATCH v1 1/2] Platform/Qemu/SbsaQemu/SbsaQemu.dsc: define GICv3 ITS base address Shashi Mallela @ 2021-03-11 20:19 ` Shashi Mallela 1 sibling, 0 replies; 4+ messages in thread From: Shashi Mallela @ 2021-03-11 20:19 UTC (permalink / raw) To: leif, ardb+tianocore, graeme; +Cc: devel For Qemu sbsa-ref platforms,to enable detection of GICv3 Interrupt Translation Service capability in the ACPI MADT,the GIC ITS structure is created with the relevant values for each of its fields.The existing MADT functionality is extended to include GIC ITS structure presence as well. Cc: Leif Lindholm <leif@nuviainc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Graeme Gregory <graeme@nuviainc.com> Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org> --- Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 1 + Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 1 + Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h | 10 ++++++++++ Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 10 +++++++++- 4 files changed, 21 insertions(+), 1 deletion(-) diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf index 9be34488eb7a..de58987b0044 100644 --- a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf @@ -34,6 +34,7 @@ [Packages] [FixedPcd] gArmTokenSpaceGuid.PcdGicDistributorBase gArmTokenSpaceGuid.PcdGicRedistributorsBase + gArmTokenSpaceGuid.PcdGicItsBase gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum gArmTokenSpaceGuid.PcdArmArchTimerIntrNum diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf index c6de685bd2c4..adf682fac564 100644 --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf @@ -59,6 +59,7 @@ [FixedPcd] gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision gArmTokenSpaceGuid.PcdGicDistributorBase gArmTokenSpaceGuid.PcdGicRedistributorsBase + gArmTokenSpaceGuid.PcdGicItsBase gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h index 4d5b05ba17c6..5f9e9477bf6a 100644 --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h @@ -37,6 +37,16 @@ SBSAQEMU_MADT_GICR_SIZE /* DiscoveryRangeLength */ \ } +// Macro for MADT GIC ITS Structure +#define SBSAQEMU_MADT_GIC_ITS_INIT() { \ + EFI_ACPI_6_0_GIC_ITS, /* Type */ \ + sizeof (EFI_ACPI_6_0_GIC_ITS_STRUCTURE), /* Length */ \ + EFI_ACPI_RESERVED_WORD, /* Reserved */ \ + 0, /* GicItsId */ \ + FixedPcdGet64 (PcdGicItsBase), /* PhysicalBaseAddress */ \ + EFI_ACPI_RESERVED_DWORD /* Reserved */ \ + } + #define SBSAQEMU_ACPI_SCOPE_OP_MAX_LENGTH 5 #define SBSAQEMU_ACPI_SCOPE_NAME { '_', 'S', 'B', '_' } diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c index b8901030ecd0..4e0d24ed6608 100644 --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c @@ -91,6 +91,9 @@ AddMadtTable ( // Initialize GIC Redistributor Structure EFI_ACPI_6_0_GICR_STRUCTURE Gicr = SBSAQEMU_MADT_GICR_INIT(); + // Initialize GIC ITS Structure + EFI_ACPI_6_0_GIC_ITS_STRUCTURE Gic_Its = SBSAQEMU_MADT_GIC_ITS_INIT(); + // Get CoreCount which was determined eariler after parsing device tree NumCores = PcdGet32 (PcdCoreCount); @@ -98,7 +101,8 @@ AddMadtTable ( TableSize = sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER) + (sizeof (EFI_ACPI_6_0_GIC_STRUCTURE) * NumCores) + sizeof (EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE) + - sizeof (EFI_ACPI_6_0_GICR_STRUCTURE); + sizeof (EFI_ACPI_6_0_GICR_STRUCTURE) + + sizeof (EFI_ACPI_6_0_GIC_ITS_STRUCTURE); Status = gBS->AllocatePages ( AllocateAnyPages, @@ -138,6 +142,10 @@ AddMadtTable ( CopyMem (New, &Gicr, sizeof (EFI_ACPI_6_0_GICR_STRUCTURE)); New += sizeof (EFI_ACPI_6_0_GICR_STRUCTURE); + // GIC ITS Structure + CopyMem (New, &Gic_Its, sizeof (EFI_ACPI_6_0_GIC_ITS_STRUCTURE)); + New += sizeof (EFI_ACPI_6_0_GIC_ITS_STRUCTURE); + AcpiPlatformChecksum ((UINT8*) PageAddress, TableSize); Status = AcpiTable->InstallAcpiTable ( -- 2.27.0 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v1 0/2] Add GIC ITS entry to MADT @ 2021-03-12 0:59 Shashi Mallela 2021-03-12 0:59 ` [PATCH v1 2/2] Silicon/Qemu: Update MADT with GICv3 ITS info Shashi Mallela 0 siblings, 1 reply; 4+ messages in thread From: Shashi Mallela @ 2021-03-12 0:59 UTC (permalink / raw) To: leif, ardb+tianocore, graeme; +Cc: devel This patchset implements ACPI MADT functionality extension to include the GICv3 ITS functionality. This enables devices to use message signalled LPI interrupts in addition to SPIs,PPIs supported on ARM SBSA reference qemu platforms. Shashi Mallela (2): Platform/Qemu/SbsaQemu/SbsaQemu.dsc: define GICv3 ITS base address Silicon/Qemu: Update MADT with GICv3 ITS info Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 3 +++ Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 3 +++ Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 2 ++ Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 2 ++ Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h | 10 ++++++++++ Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 10 +++++++++- 6 files changed, 29 insertions(+), 1 deletion(-) -- 2.27.0 ^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH v1 2/2] Silicon/Qemu: Update MADT with GICv3 ITS info 2021-03-12 0:59 [PATCH v1 0/2] Add GIC ITS entry to MADT Shashi Mallela @ 2021-03-12 0:59 ` Shashi Mallela 0 siblings, 0 replies; 4+ messages in thread From: Shashi Mallela @ 2021-03-12 0:59 UTC (permalink / raw) To: leif, ardb+tianocore, graeme; +Cc: devel For Qemu sbsa-ref platforms,to enable detection of GICv3 Interrupt Translation Service capability in the ACPI MADT,the GIC ITS structure is created with the relevant values for each of its fields.The existing MADT functionality is extended to include GIC ITS structure presence as well. Cc: Leif Lindholm <leif@nuviainc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Graeme Gregory <graeme@nuviainc.com> Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org> --- Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 3 +++ Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 2 ++ Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 2 ++ Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h | 10 ++++++++++ Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 10 +++++++++- 5 files changed, 26 insertions(+), 1 deletion(-) diff --git a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec index 9448852967b6..8654cc7c858c 100644 --- a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec +++ b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec @@ -36,6 +36,9 @@ [PcdsFixedAtBuild.common] gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciSize|0x10000|UINT32|0x00000004 gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress|0x10000000000|UINT64|0x00000005 + # ARM Generic Interrupt Controller ITS + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdGicItsBase|0|UINT64|0x0000000F + # PCDs complementing PCIe layout pulled into ACPI tables # Limit = Base + Size - 1 gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciIoLimit|0x0000ffff|UINT32|0x00000006 diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf index 9be34488eb7a..5616b73178ff 100644 --- a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf @@ -74,3 +74,5 @@ [FixedPcd] gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformAhciSize gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciBase gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciSize + + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdGicItsBase diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf index c6de685bd2c4..2eb6577fd077 100644 --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf @@ -65,3 +65,5 @@ [FixedPcd] gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision + + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdGicItsBase diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h index 4d5b05ba17c6..5f9e9477bf6a 100644 --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h @@ -37,6 +37,16 @@ SBSAQEMU_MADT_GICR_SIZE /* DiscoveryRangeLength */ \ } +// Macro for MADT GIC ITS Structure +#define SBSAQEMU_MADT_GIC_ITS_INIT() { \ + EFI_ACPI_6_0_GIC_ITS, /* Type */ \ + sizeof (EFI_ACPI_6_0_GIC_ITS_STRUCTURE), /* Length */ \ + EFI_ACPI_RESERVED_WORD, /* Reserved */ \ + 0, /* GicItsId */ \ + FixedPcdGet64 (PcdGicItsBase), /* PhysicalBaseAddress */ \ + EFI_ACPI_RESERVED_DWORD /* Reserved */ \ + } + #define SBSAQEMU_ACPI_SCOPE_OP_MAX_LENGTH 5 #define SBSAQEMU_ACPI_SCOPE_NAME { '_', 'S', 'B', '_' } diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c index b8901030ecd0..4e0d24ed6608 100644 --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c @@ -91,6 +91,9 @@ AddMadtTable ( // Initialize GIC Redistributor Structure EFI_ACPI_6_0_GICR_STRUCTURE Gicr = SBSAQEMU_MADT_GICR_INIT(); + // Initialize GIC ITS Structure + EFI_ACPI_6_0_GIC_ITS_STRUCTURE Gic_Its = SBSAQEMU_MADT_GIC_ITS_INIT(); + // Get CoreCount which was determined eariler after parsing device tree NumCores = PcdGet32 (PcdCoreCount); @@ -98,7 +101,8 @@ AddMadtTable ( TableSize = sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER) + (sizeof (EFI_ACPI_6_0_GIC_STRUCTURE) * NumCores) + sizeof (EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE) + - sizeof (EFI_ACPI_6_0_GICR_STRUCTURE); + sizeof (EFI_ACPI_6_0_GICR_STRUCTURE) + + sizeof (EFI_ACPI_6_0_GIC_ITS_STRUCTURE); Status = gBS->AllocatePages ( AllocateAnyPages, @@ -138,6 +142,10 @@ AddMadtTable ( CopyMem (New, &Gicr, sizeof (EFI_ACPI_6_0_GICR_STRUCTURE)); New += sizeof (EFI_ACPI_6_0_GICR_STRUCTURE); + // GIC ITS Structure + CopyMem (New, &Gic_Its, sizeof (EFI_ACPI_6_0_GIC_ITS_STRUCTURE)); + New += sizeof (EFI_ACPI_6_0_GIC_ITS_STRUCTURE); + AcpiPlatformChecksum ((UINT8*) PageAddress, TableSize); Status = AcpiTable->InstallAcpiTable ( -- 2.27.0 ^ permalink raw reply related [flat|nested] 4+ messages in thread
end of thread, other threads:[~2021-03-12 0:59 UTC | newest] Thread overview: 4+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2021-03-11 20:19 [PATCH v1 0/2] Add GIC ITS entry to MADT Shashi Mallela 2021-03-11 20:19 ` [PATCH v1 1/2] Platform/Qemu/SbsaQemu/SbsaQemu.dsc: define GICv3 ITS base address Shashi Mallela 2021-03-11 20:19 ` [PATCH v1 2/2] Silicon/Qemu: Update MADT with GICv3 ITS info Shashi Mallela -- strict thread matches above, loose matches on Subject: below -- 2021-03-12 0:59 [PATCH v1 0/2] Add GIC ITS entry to MADT Shashi Mallela 2021-03-12 0:59 ` [PATCH v1 2/2] Silicon/Qemu: Update MADT with GICv3 ITS info Shashi Mallela
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