* [PATCH v3 00/46] Added support for FT2000/4 chip @ 2021-03-12 10:55 Ling Jia 2021-03-12 10:55 ` [PATCH v3 01/46] TigerlakeOpenBoardPkg: Fix build errors with GCC5 Ling Jia 2021-03-12 10:55 ` [PATCH v3 14/46] Silicon/Phytium: Added Acpi support to FT2000/4 Ling Jia 0 siblings, 2 replies; 6+ messages in thread From: Ling Jia @ 2021-03-12 10:55 UTC (permalink / raw) To: devel; +Cc: Leif Lindholm, Peng Xie, Yiqi Shu, Ling Jia The modules could be runed at the silicon of FT2000/4. They supported Acpi parameter configuration, Pci bus scaning, flash read-write and erase abd operating system boot function. Maintainers.txt: Added maintainers and reviewers for the DurianPkg. The public git repository is : https://github.com/jialing2020/edk2-platforms/tree/phytium_opensource_for_FT2000-4_v3 v3: Optimized the codes to meet the specification. In the process of submitting V3 version, the master branch is ahead of the current branch. So, there was a lot of submission from someone else. In this case, what should we to do? *** BLURB HERE *** Heng Luo (2): Fix wrong information of TigerLake in Readme.md Fix wrong information of TigerLake in Readme.md Jeremy Linton (2): Platform/RaspberryPi/Acpitables: Correct duplicate _UIDs Platform/RaspberryPi/Acpitables: Correct duplicate _UIDs Leif Lindholm (2): Silicon/Qemu: Move SbsaQemu MPIDR-retrieval function to FdtHelperLib Silicon/Qemu: Move SbsaQemu MPIDR-retrieval function to FdtHelperLib Ling Jia (20): Silicon/Phytium: Added PlatformLib to FT2000/4 Silicon/Phytium: Added Acpi support to FT2000/4 Silicon/Phytium: Added SMBIOS support to FT2000/4 Silicon/Phytium: Added PciSegmentLib to FT2000/4 Silicon/Phytium: Added PciHostBridgeLib to FT2000/4 Silicon/Phytium: Added Spi driver support to FT2000/4 Silicon/Phytium: Added flash driver support to Phytium Silicon Silicon/Phytium: Added fvb driver for norflash Silicon/Phytium: Added Rtc driver to FT2000/4 Maintainers.txt: Added maintainers and reviewers for the DurianPkg Silicon/Phytium: Added PlatformLib to FT2000/4 Silicon/Phytium: Added Acpi support to FT2000/4 Silicon/Phytium: Added SMBIOS support to FT2000/4 Silicon/Phytium: Added PciSegmentLib to FT2000/4 Silicon/Phytium: Added PciHostBridgeLib to FT2000/4 Silicon/Phytium: Added Spi driver support to FT2000/4 Silicon/Phytium: Added flash driver support to Phytium Silicon Silicon/Phytium: Added fvb driver for norflash Silicon/Phytium: Added Rtc driver to FT2000/4 Maintainers.txt: Added maintainers and reviewers for the DurianPkg Liu, Zhiguang (2): Intel/BoardModulePkg: sort load option in the first boot Intel/BoardModulePkg: sort load option in the first boot Marcin Juszkiewicz (2): drop Tanmay Jagdale from sbsa-ref maintainers drop Tanmay Jagdale from sbsa-ref maintainers Rebecca Cran (8): SbsaQemu: Add FdtHelperLib SbsaQemu: Update SbsaQemuAcpiDxe to use FdtHelperLib Platform/Qemu/SbsaQemu: Add SMBIOS tables Silicon/Qemu: Don't re-use NumCores as loop index in AddMadtTable SbsaQemu: Add FdtHelperLib SbsaQemu: Update SbsaQemuAcpiDxe to use FdtHelperLib Platform/Qemu/SbsaQemu: Add SMBIOS tables Silicon/Qemu: Don't re-use NumCores as loop index in AddMadtTable Takuto Naito (8): TigerlakeOpenBoardPkg: Fix build errors with GCC5 TigerlakeSiliconPkg/IpBlock: Fix build errors with GCC5 TigerlakeSiliconPkg: Fix build error with GCC5 TigerlakeOpenBoardPkg: Fix build error with GCC5 TigerlakeOpenBoardPkg: Fix build errors with GCC5 TigerlakeSiliconPkg/IpBlock: Fix build errors with GCC5 TigerlakeSiliconPkg: Fix build error with GCC5 TigerlakeOpenBoardPkg: Fix build error with GCC5 Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec | 52 + Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 17 + Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dsc.inc | 345 +++++ Platform/Phytium/DurianPkg/DurianPkg.dsc | 331 +++++ Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 50 +- Platform/Phytium/DurianPkg/DurianPkg.fdf | 235 ++++ Platform/Qemu/SbsaQemu/SbsaQemu.fdf | 7 + Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf | 2 +- Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf | 53 + Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiTables.inf | 56 + Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf | 47 + Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf | 44 + Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf | 48 + Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf | 47 + Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.inf | 28 + Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLib.inf | 55 + Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib.inf | 39 + Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf | 53 + Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.inf | 61 + Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 3 +- Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.inf | 33 + Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.h | 64 + Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.h | 99 ++ Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib.h | 24 + Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.h | 104 ++ Silicon/Phytium/PhytiumCommonPkg/Include/Platform.h | 80 ++ Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiNorFlashProtocol.h | 74 + Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiProtocol.h | 51 + Silicon/Phytium/PhytiumCommonPkg/Include/SystemServiceInterface.h | 112 ++ Silicon/Qemu/SbsaQemu/Include/Library/FdtHelperLib.h | 36 + Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.c | 72 +- Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c | 196 --- Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c | 2 +- Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/PeiTigerlakeURvpInitPreMemLib.c | 2 + Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c | 241 ++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/DxePchPcieRpPolicyLib/DxePchPcieRpPolicyLib.c | 2 +- Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/PcieClientRpLib/PcieClientRpLib.c | 2 - Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitLib.c | 5 - Silicon/Intel/TigerlakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmiHelperClient.c | 2 - Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c | 943 +++++++++++++ Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.c | 198 +++ Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.c | 424 ++++++ Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.c | 181 +++ Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.c | 1434 ++++++++++++++++++++ Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLib.c | 137 ++ Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLibMem.c | 156 +++ Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib.c | 462 +++++++ Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatform.c | 250 ++++ Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.c | 1304 ++++++++++++++++++ Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 95 +- Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.c | 98 ++ Maintainers.txt | 9 +- Platform/Intel/Readme.md | 2 +- Platform/RaspberryPi/AcpiTables/Emmc.asl | 2 +- Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiSsdtRootPci.asl | 209 +++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dbg2.aslc | 80 ++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Cpu.asl | 85 ++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Dsdt.asl | 15 + Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Uart.asl | 65 + Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Fadt.aslc | 77 ++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Gtdt.aslc | 83 ++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Iort.aslc | 89 ++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Madt.aslc | 67 + Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Mcfg.aslc | 65 + Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Pptt.aslc | 219 +++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Spcr.aslc | 73 + Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/AArch64/PhytiumPlatformHelper.S | 76 ++ Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.fdf.inc | 119 ++ 68 files changed, 9456 insertions(+), 335 deletions(-) create mode 100644 Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec create mode 100644 Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dsc.inc create mode 100644 Platform/Phytium/DurianPkg/DurianPkg.dsc create mode 100644 Platform/Phytium/DurianPkg/DurianPkg.fdf create mode 100644 Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiTables.inf create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.inf create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLib.inf create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib.inf create mode 100644 Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf create mode 100644 Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.inf create mode 100644 Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.inf create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.h create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.h create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib.h create mode 100644 Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.h create mode 100644 Silicon/Phytium/PhytiumCommonPkg/Include/Platform.h create mode 100644 Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiNorFlashProtocol.h create mode 100644 Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiProtocol.h create mode 100644 Silicon/Phytium/PhytiumCommonPkg/Include/SystemServiceInterface.h create mode 100644 Silicon/Qemu/SbsaQemu/Include/Library/FdtHelperLib.h create mode 100644 Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.c create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.c create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.c create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.c create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLib.c create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLibMem.c create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib.c create mode 100644 Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatform.c create mode 100644 Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.c create mode 100644 Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.c create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiSsdtRootPci.asl create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dbg2.aslc create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Cpu.asl create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Dsdt.asl create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Uart.asl create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Fadt.aslc create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Gtdt.aslc create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Iort.aslc create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Madt.aslc create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Mcfg.aslc create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Pptt.aslc create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Spcr.aslc create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/AArch64/PhytiumPlatformHelper.S create mode 100644 Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.fdf.inc -- 2.25.1 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v3 01/46] TigerlakeOpenBoardPkg: Fix build errors with GCC5 2021-03-12 10:55 [PATCH v3 00/46] Added support for FT2000/4 chip Ling Jia @ 2021-03-12 10:55 ` Ling Jia 2021-04-01 19:19 ` Nate DeSimone 2021-03-12 10:55 ` [PATCH v3 14/46] Silicon/Phytium: Added Acpi support to FT2000/4 Ling Jia 1 sibling, 1 reply; 6+ messages in thread From: Ling Jia @ 2021-03-12 10:55 UTC (permalink / raw) To: devel Cc: Leif Lindholm, Peng Xie, Yiqi Shu, Takuto Naito, Sai Chaganty, Nate DeSimone, Heng Luo From: Takuto Naito <naitaku@gmail.com> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3224 - Fix the path of TigerLakeFspBinPkg - Fix misuse of RETURN_ERROR - Remove unused function CheckNationalSio. Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Heng Luo <heng.luo@intel.com> Signed-off-by: Takuto Naito <naitaku@gmail.com> Reviewed-by: Heng Luo <heng.luo@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> --- Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf | 2 +- Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c | 188 -------------------- Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c | 2 +- 3 files changed, 2 insertions(+), 190 deletions(-) diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf index 9d85d855f501..708fbac08fd6 100644 --- a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf +++ b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf @@ -52,7 +52,7 @@ [Packages] MdeModulePkg/MdeModulePkg.dec IntelFsp2Pkg/IntelFsp2Pkg.dec TigerlakeSiliconPkg/SiPkg.dec - TigerLakeFspBinPkg/TigerLakeFspBinPkg.dec + TigerLakeFspBinPkg/Client/TigerLakeFspBinPkg.dec TigerlakeOpenBoardPkg/OpenBoardPkg.dec UefiCpuPkg/UefiCpuPkg.dec IntelSiliconPkg/IntelSiliconPkg.dec diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c b/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c index 6209e5045061..cc5337698b8a 100644 --- a/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c +++ b/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c @@ -94,194 +94,6 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTableWinbond_x374[] = { {0x30, 0x01} // Enable it with Activation bit }; -/** - Detect if a National 393 SIO is docked. If yes, enable the docked SIO - and its serial port, and disable the onboard serial port. - - @retval EFI_SUCCESS Operations performed successfully. -**/ -STATIC -VOID -CheckNationalSio ( - VOID - ) -{ - UINT8 Data8; - - // - // Pc87393 access is through either (0x2e, 0x2f) or (0x4e, 0x4f). - // We use (0x2e, 0x2f) which is determined by BADD default strapping - // - - // - // Read the Pc87393 signature - // - IoWrite8 (0x2e, 0x20); - Data8 = IoRead8 (0x2f); - - if (Data8 == 0xea) { - // - // Signature matches - National PC87393 SIO is docked - // - - // - // Enlarge the LPC decode scope to accommodate the Docking LPC Switch - // Register (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS is allocated at - // SIO_BASE_ADDRESS + 0x10) - // - PchLpcGenIoRangeSet ((FixedPcdGet16 (PcdSioBaseAddress) & (UINT16)~0x7F), 0x20); - - // - // Enable port switch - // - IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x06); - - // - // Turn on docking power - // - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x8c); - - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x9c); - - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0xBc); - - // - // Enable port switch - // - IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x7); - - // - // GPIO setting - // - IoWrite8 (0x2e, 0x24); - IoWrite8 (0x2f, 0x29); - - // - // Enable chip clock - // - IoWrite8 (0x2e, 0x29); - IoWrite8 (0x2f, 0x1e); - - - // - // Enable serial port - // - - // - // Select com1 - // - IoWrite8 (0x2e, 0x7); - IoWrite8 (0x2f, 0x3); - - // - // Base address: 0x3f8 - // - IoWrite8 (0x2e, 0x60); - IoWrite8 (0x2f, 0x03); - IoWrite8 (0x2e, 0x61); - IoWrite8 (0x2f, 0xf8); - - // - // Interrupt: 4 - // - IoWrite8 (0x2e, 0x70); - IoWrite8 (0x2f, 0x04); - - // - // Enable bank selection - // - IoWrite8 (0x2e, 0xf0); - IoWrite8 (0x2f, 0x82); - - // - // Activate - // - IoWrite8 (0x2e, 0x30); - IoWrite8 (0x2f, 0x01); - - // - // Disable onboard serial port - // - IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0x55); - - // - // Power Down UARTs - // - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x2); - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x00); - - // - // Dissable COM1 decode - // - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x24); - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0); - - // - // Disable COM2 decode - // - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x25); - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0); - - // - // Disable interrupt - // - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x28); - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x0); - - IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA); - - // - // Enable floppy - // - - // - // Select floppy - // - IoWrite8 (0x2e, 0x7); - IoWrite8 (0x2f, 0x0); - - // - // Base address: 0x3f0 - // - IoWrite8 (0x2e, 0x60); - IoWrite8 (0x2f, 0x03); - IoWrite8 (0x2e, 0x61); - IoWrite8 (0x2f, 0xf0); - - // - // Interrupt: 6 - // - IoWrite8 (0x2e, 0x70); - IoWrite8 (0x2f, 0x06); - - // - // DMA 2 - // - IoWrite8 (0x2e, 0x74); - IoWrite8 (0x2f, 0x02); - - // - // Activate - // - IoWrite8 (0x2e, 0x30); - IoWrite8 (0x2f, 0x01); - - } else { - - // - // No National pc87393 SIO is docked, turn off dock power and - // disable port switch - // - // IoWrite8 (SIO_BASE_ADDRESS + 0x0E, 0xbf); - // IoWrite8 (0x690, 0); - - // - // If no National pc87393, just return - // - return ; - } -} - /** Check whether the IT8628 SIO present on LPC. If yes, enable its serial ports diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c index 2eee9958beea..410a8d1073a9 100644 --- a/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c +++ b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c @@ -88,8 +88,8 @@ SiliconPolicyUpdateLate ( // GOP Dxe Policy Initialization // Status = GopPolicyInitDxe (gImageHandle); - RETURN_ERROR (Status); DEBUG ((DEBUG_INFO, "GOP Dxe Policy Initialization done\n")); + ASSERT_EFI_ERROR (Status); } return Policy; -- 2.25.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v3 01/46] TigerlakeOpenBoardPkg: Fix build errors with GCC5 2021-03-12 10:55 ` [PATCH v3 01/46] TigerlakeOpenBoardPkg: Fix build errors with GCC5 Ling Jia @ 2021-04-01 19:19 ` Nate DeSimone 2021-04-02 8:46 ` Ling Jia 0 siblings, 1 reply; 6+ messages in thread From: Nate DeSimone @ 2021-04-01 19:19 UTC (permalink / raw) To: Ling Jia, devel@edk2.groups.io Cc: Leif Lindholm, Peng Xie, Yiqi Shu, Takuto Naito, Chaganty, Rangasai V, Luo, Heng Hi Ling, This appears to be a duplicate of a patch that has already been applied: https://edk2.groups.io/g/devel/message/71894 https://github.com/tianocore/edk2-platforms/commit/12ef75dc Was this message sent in error? Thanks, Nate > -----Original Message----- > From: Ling Jia <jialing@phytium.com.cn> > Sent: Friday, March 12, 2021 2:56 AM > To: devel@edk2.groups.io > Cc: Leif Lindholm <leif@nuviainc.com>; Peng Xie > <xiepeng@phytium.com.cn>; Yiqi Shu <shuyiqi@phytium.com.cn>; Takuto > Naito <naitaku@gmail.com>; Chaganty, Rangasai V > <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L > <nathaniel.l.desimone@intel.com>; Luo, Heng <heng.luo@intel.com> > Subject: [PATCH v3 01/46] TigerlakeOpenBoardPkg: Fix build errors with > GCC5 > > From: Takuto Naito <naitaku@gmail.com> > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3224 > > - Fix the path of TigerLakeFspBinPkg > - Fix misuse of RETURN_ERROR > - Remove unused function CheckNationalSio. > > Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> > Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> > Cc: Heng Luo <heng.luo@intel.com> > Signed-off-by: Takuto Naito <naitaku@gmail.com> > Reviewed-by: Heng Luo <heng.luo@intel.com> > Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> > --- > > Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInit > Lib/PeiFspPolicyInitLib.inf | 2 +- > > Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePl > atformHookLib.c | 188 -------------------- > > Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdat > eLib/DxeSiliconPolicyUpdateLate.c | 2 +- > 3 files changed, 2 insertions(+), 190 deletions(-) > > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI > nitLib/PeiFspPolicyInitLib.inf > b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI > nitLib/PeiFspPolicyInitLib.inf > index 9d85d855f501..708fbac08fd6 100644 > --- > a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI > nitLib/PeiFspPolicyInitLib.inf > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI > nitLib/PeiFspPolicyInitLib.inf > @@ -52,7 +52,7 @@ [Packages] > MdeModulePkg/MdeModulePkg.dec > > IntelFsp2Pkg/IntelFsp2Pkg.dec > > TigerlakeSiliconPkg/SiPkg.dec > > - TigerLakeFspBinPkg/TigerLakeFspBinPkg.dec > > + TigerLakeFspBinPkg/Client/TigerLakeFspBinPkg.dec > > TigerlakeOpenBoardPkg/OpenBoardPkg.dec > > UefiCpuPkg/UefiCpuPkg.dec > > IntelSiliconPkg/IntelSiliconPkg.dec > > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/Bas > ePlatformHookLib.c > b/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/Bas > ePlatformHookLib.c > index 6209e5045061..cc5337698b8a 100644 > --- > a/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/Bas > ePlatformHookLib.c > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/Bas > ePlatformHookLib.c > @@ -94,194 +94,6 @@ GLOBAL_REMOVE_IF_UNREFERENCED > EFI_SIO_TABLE mSioTableWinbond_x374[] = { > {0x30, 0x01} // Enable it with Activation bit > > }; > > > > -/** > > - Detect if a National 393 SIO is docked. If yes, enable the docked SIO > > - and its serial port, and disable the onboard serial port. > > - > > - @retval EFI_SUCCESS Operations performed successfully. > > -**/ > > -STATIC > > -VOID > > -CheckNationalSio ( > > - VOID > > - ) > > -{ > > - UINT8 Data8; > > - > > - // > > - // Pc87393 access is through either (0x2e, 0x2f) or (0x4e, 0x4f). > > - // We use (0x2e, 0x2f) which is determined by BADD default strapping > > - // > > - > > - // > > - // Read the Pc87393 signature > > - // > > - IoWrite8 (0x2e, 0x20); > > - Data8 = IoRead8 (0x2f); > > - > > - if (Data8 == 0xea) { > > - // > > - // Signature matches - National PC87393 SIO is docked > > - // > > - > > - // > > - // Enlarge the LPC decode scope to accommodate the Docking LPC Switch > > - // Register (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS is allocated > at > > - // SIO_BASE_ADDRESS + 0x10) > > - // > > - PchLpcGenIoRangeSet ((FixedPcdGet16 (PcdSioBaseAddress) & > (UINT16)~0x7F), 0x20); > > - > > - // > > - // Enable port switch > > - // > > - IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x06); > > - > > - // > > - // Turn on docking power > > - // > > - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x8c); > > - > > - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x9c); > > - > > - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0xBc); > > - > > - // > > - // Enable port switch > > - // > > - IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x7); > > - > > - // > > - // GPIO setting > > - // > > - IoWrite8 (0x2e, 0x24); > > - IoWrite8 (0x2f, 0x29); > > - > > - // > > - // Enable chip clock > > - // > > - IoWrite8 (0x2e, 0x29); > > - IoWrite8 (0x2f, 0x1e); > > - > > - > > - // > > - // Enable serial port > > - // > > - > > - // > > - // Select com1 > > - // > > - IoWrite8 (0x2e, 0x7); > > - IoWrite8 (0x2f, 0x3); > > - > > - // > > - // Base address: 0x3f8 > > - // > > - IoWrite8 (0x2e, 0x60); > > - IoWrite8 (0x2f, 0x03); > > - IoWrite8 (0x2e, 0x61); > > - IoWrite8 (0x2f, 0xf8); > > - > > - // > > - // Interrupt: 4 > > - // > > - IoWrite8 (0x2e, 0x70); > > - IoWrite8 (0x2f, 0x04); > > - > > - // > > - // Enable bank selection > > - // > > - IoWrite8 (0x2e, 0xf0); > > - IoWrite8 (0x2f, 0x82); > > - > > - // > > - // Activate > > - // > > - IoWrite8 (0x2e, 0x30); > > - IoWrite8 (0x2f, 0x01); > > - > > - // > > - // Disable onboard serial port > > - // > > - IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0x55); > > - > > - // > > - // Power Down UARTs > > - // > > - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x2); > > - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x00); > > - > > - // > > - // Dissable COM1 decode > > - // > > - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x24); > > - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0); > > - > > - // > > - // Disable COM2 decode > > - // > > - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x25); > > - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0); > > - > > - // > > - // Disable interrupt > > - // > > - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x28); > > - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x0); > > - > > - IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA); > > - > > - // > > - // Enable floppy > > - // > > - > > - // > > - // Select floppy > > - // > > - IoWrite8 (0x2e, 0x7); > > - IoWrite8 (0x2f, 0x0); > > - > > - // > > - // Base address: 0x3f0 > > - // > > - IoWrite8 (0x2e, 0x60); > > - IoWrite8 (0x2f, 0x03); > > - IoWrite8 (0x2e, 0x61); > > - IoWrite8 (0x2f, 0xf0); > > - > > - // > > - // Interrupt: 6 > > - // > > - IoWrite8 (0x2e, 0x70); > > - IoWrite8 (0x2f, 0x06); > > - > > - // > > - // DMA 2 > > - // > > - IoWrite8 (0x2e, 0x74); > > - IoWrite8 (0x2f, 0x02); > > - > > - // > > - // Activate > > - // > > - IoWrite8 (0x2e, 0x30); > > - IoWrite8 (0x2f, 0x01); > > - > > - } else { > > - > > - // > > - // No National pc87393 SIO is docked, turn off dock power and > > - // disable port switch > > - // > > - // IoWrite8 (SIO_BASE_ADDRESS + 0x0E, 0xbf); > > - // IoWrite8 (0x690, 0); > > - > > - // > > - // If no National pc87393, just return > > - // > > - return ; > > - } > > -} > > - > > /** > > Check whether the IT8628 SIO present on LPC. If yes, enable its serial ports > > > > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpd > ateLib/DxeSiliconPolicyUpdateLate.c > b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUp > dateLib/DxeSiliconPolicyUpdateLate.c > index 2eee9958beea..410a8d1073a9 100644 > --- > a/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpd > ateLib/DxeSiliconPolicyUpdateLate.c > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUp > dateLib/DxeSiliconPolicyUpdateLate.c > @@ -88,8 +88,8 @@ SiliconPolicyUpdateLate ( > // GOP Dxe Policy Initialization > > // > > Status = GopPolicyInitDxe (gImageHandle); > > - RETURN_ERROR (Status); > > DEBUG ((DEBUG_INFO, "GOP Dxe Policy Initialization done\n")); > > + ASSERT_EFI_ERROR (Status); > > } > > > > return Policy; > > -- > 2.25.1 ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v3 01/46] TigerlakeOpenBoardPkg: Fix build errors with GCC5 2021-04-01 19:19 ` Nate DeSimone @ 2021-04-02 8:46 ` Ling Jia 0 siblings, 0 replies; 6+ messages in thread From: Ling Jia @ 2021-04-02 8:46 UTC (permalink / raw) To: Desimone, Nathaniel L Cc: devel@edk2.groups.io, Leif Lindholm, Peng Xie, Yiqi Shu, Takuto Naito, Chaganty, Rangasai V, Luo, Heng Hi, Nate, Yes, It was an error message. I'm sorry about this, because I didn't operate git cherry pick well, resulting in the wrong patches. But I have corrected it. Please ignore it. Thanks, Ling > -----原始邮件----- > 发件人: "Desimone, Nathaniel L" <nathaniel.l.desimone@intel.com> > 发送时间: 2021-04-02 03:19:58 (星期五) > 收件人: "Ling Jia" <jialing@phytium.com.cn>, "devel@edk2.groups.io" <devel@edk2.groups.io> > 抄送: "Leif Lindholm" <leif@nuviainc.com>, "Peng Xie" <xiepeng@phytium.com.cn>, "Yiqi Shu" <shuyiqi@phytium.com.cn>, "Takuto Naito" <naitaku@gmail.com>, "Chaganty, Rangasai V" <rangasai.v.chaganty@intel.com>, "Luo, Heng" <heng.luo@intel.com> > 主题: RE: [PATCH v3 01/46] TigerlakeOpenBoardPkg: Fix build errors with GCC5 > > Hi Ling, > > This appears to be a duplicate of a patch that has already been applied: > > https://edk2.groups.io/g/devel/message/71894 > https://github.com/tianocore/edk2-platforms/commit/12ef75dc > > Was this message sent in error? > > Thanks, > Nate > > > > -----Original Message----- > > From: Ling Jia <jialing@phytium.com.cn> > > Sent: Friday, March 12, 2021 2:56 AM > > To: devel@edk2.groups.io > > Cc: Leif Lindholm <leif@nuviainc.com>; Peng Xie > > <xiepeng@phytium.com.cn>; Yiqi Shu <shuyiqi@phytium.com.cn>; Takuto > > Naito <naitaku@gmail.com>; Chaganty, Rangasai V > > <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L > > <nathaniel.l.desimone@intel.com>; Luo, Heng <heng.luo@intel.com> > > Subject: [PATCH v3 01/46] TigerlakeOpenBoardPkg: Fix build errors with > > GCC5 > > > > From: Takuto Naito <naitaku@gmail.com> > > > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3224 > > > > - Fix the path of TigerLakeFspBinPkg > > - Fix misuse of RETURN_ERROR > > - Remove unused function CheckNationalSio. > > > > Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> > > Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> > > Cc: Heng Luo <heng.luo@intel.com> > > Signed-off-by: Takuto Naito <naitaku@gmail.com> > > Reviewed-by: Heng Luo <heng.luo@intel.com> > > Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> > > --- > > > > Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInit > > Lib/PeiFspPolicyInitLib.inf | 2 +- > > > > Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePl > > atformHookLib.c | 188 -------------------- > > > > Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdat > > eLib/DxeSiliconPolicyUpdateLate.c | 2 +- > > 3 files changed, 2 insertions(+), 190 deletions(-) > > > > diff --git > > a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI > > nitLib/PeiFspPolicyInitLib.inf > > b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI > > nitLib/PeiFspPolicyInitLib.inf > > index 9d85d855f501..708fbac08fd6 100644 > > --- > > a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI > > nitLib/PeiFspPolicyInitLib.inf > > +++ > > b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI > > nitLib/PeiFspPolicyInitLib.inf > > @@ -52,7 +52,7 @@ [Packages] > > MdeModulePkg/MdeModulePkg.dec > > > > IntelFsp2Pkg/IntelFsp2Pkg.dec > > > > TigerlakeSiliconPkg/SiPkg.dec > > > > - TigerLakeFspBinPkg/TigerLakeFspBinPkg.dec > > > > + TigerLakeFspBinPkg/Client/TigerLakeFspBinPkg.dec > > > > TigerlakeOpenBoardPkg/OpenBoardPkg.dec > > > > UefiCpuPkg/UefiCpuPkg.dec > > > > IntelSiliconPkg/IntelSiliconPkg.dec > > > > diff --git > > a/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/Bas > > ePlatformHookLib.c > > b/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/Bas > > ePlatformHookLib.c > > index 6209e5045061..cc5337698b8a 100644 > > --- > > a/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/Bas > > ePlatformHookLib.c > > +++ > > b/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/Bas > > ePlatformHookLib.c > > @@ -94,194 +94,6 @@ GLOBAL_REMOVE_IF_UNREFERENCED > > EFI_SIO_TABLE mSioTableWinbond_x374[] = { > > {0x30, 0x01} // Enable it with Activation bit > > > > }; > > > > > > > > -/** > > > > - Detect if a National 393 SIO is docked. If yes, enable the docked SIO > > > > - and its serial port, and disable the onboard serial port. > > > > - > > > > - @retval EFI_SUCCESS Operations performed successfully. > > > > -**/ > > > > -STATIC > > > > -VOID > > > > -CheckNationalSio ( > > > > - VOID > > > > - ) > > > > -{ > > > > - UINT8 Data8; > > > > - > > > > - // > > > > - // Pc87393 access is through either (0x2e, 0x2f) or (0x4e, 0x4f). > > > > - // We use (0x2e, 0x2f) which is determined by BADD default strapping > > > > - // > > > > - > > > > - // > > > > - // Read the Pc87393 signature > > > > - // > > > > - IoWrite8 (0x2e, 0x20); > > > > - Data8 = IoRead8 (0x2f); > > > > - > > > > - if (Data8 == 0xea) { > > > > - // > > > > - // Signature matches - National PC87393 SIO is docked > > > > - // > > > > - > > > > - // > > > > - // Enlarge the LPC decode scope to accommodate the Docking LPC Switch > > > > - // Register (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS is allocated > > at > > > > - // SIO_BASE_ADDRESS + 0x10) > > > > - // > > > > - PchLpcGenIoRangeSet ((FixedPcdGet16 (PcdSioBaseAddress) & > > (UINT16)~0x7F), 0x20); > > > > - > > > > - // > > > > - // Enable port switch > > > > - // > > > > - IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x06); > > > > - > > > > - // > > > > - // Turn on docking power > > > > - // > > > > - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x8c); > > > > - > > > > - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x9c); > > > > - > > > > - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0xBc); > > > > - > > > > - // > > > > - // Enable port switch > > > > - // > > > > - IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x7); > > > > - > > > > - // > > > > - // GPIO setting > > > > - // > > > > - IoWrite8 (0x2e, 0x24); > > > > - IoWrite8 (0x2f, 0x29); > > > > - > > > > - // > > > > - // Enable chip clock > > > > - // > > > > - IoWrite8 (0x2e, 0x29); > > > > - IoWrite8 (0x2f, 0x1e); > > > > - > > > > - > > > > - // > > > > - // Enable serial port > > > > - // > > > > - > > > > - // > > > > - // Select com1 > > > > - // > > > > - IoWrite8 (0x2e, 0x7); > > > > - IoWrite8 (0x2f, 0x3); > > > > - > > > > - // > > > > - // Base address: 0x3f8 > > > > - // > > > > - IoWrite8 (0x2e, 0x60); > > > > - IoWrite8 (0x2f, 0x03); > > > > - IoWrite8 (0x2e, 0x61); > > > > - IoWrite8 (0x2f, 0xf8); > > > > - > > > > - // > > > > - // Interrupt: 4 > > > > - // > > > > - IoWrite8 (0x2e, 0x70); > > > > - IoWrite8 (0x2f, 0x04); > > > > - > > > > - // > > > > - // Enable bank selection > > > > - // > > > > - IoWrite8 (0x2e, 0xf0); > > > > - IoWrite8 (0x2f, 0x82); > > > > - > > > > - // > > > > - // Activate > > > > - // > > > > - IoWrite8 (0x2e, 0x30); > > > > - IoWrite8 (0x2f, 0x01); > > > > - > > > > - // > > > > - // Disable onboard serial port > > > > - // > > > > - IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0x55); > > > > - > > > > - // > > > > - // Power Down UARTs > > > > - // > > > > - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x2); > > > > - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x00); > > > > - > > > > - // > > > > - // Dissable COM1 decode > > > > - // > > > > - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x24); > > > > - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0); > > > > - > > > > - // > > > > - // Disable COM2 decode > > > > - // > > > > - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x25); > > > > - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0); > > > > - > > > > - // > > > > - // Disable interrupt > > > > - // > > > > - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x28); > > > > - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x0); > > > > - > > > > - IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA); > > > > - > > > > - // > > > > - // Enable floppy > > > > - // > > > > - > > > > - // > > > > - // Select floppy > > > > - // > > > > - IoWrite8 (0x2e, 0x7); > > > > - IoWrite8 (0x2f, 0x0); > > > > - > > > > - // > > > > - // Base address: 0x3f0 > > > > - // > > > > - IoWrite8 (0x2e, 0x60); > > > > - IoWrite8 (0x2f, 0x03); > > > > - IoWrite8 (0x2e, 0x61); > > > > - IoWrite8 (0x2f, 0xf0); > > > > - > > > > - // > > > > - // Interrupt: 6 > > > > - // > > > > - IoWrite8 (0x2e, 0x70); > > > > - IoWrite8 (0x2f, 0x06); > > > > - > > > > - // > > > > - // DMA 2 > > > > - // > > > > - IoWrite8 (0x2e, 0x74); > > > > - IoWrite8 (0x2f, 0x02); > > > > - > > > > - // > > > > - // Activate > > > > - // > > > > - IoWrite8 (0x2e, 0x30); > > > > - IoWrite8 (0x2f, 0x01); > > > > - > > > > - } else { > > > > - > > > > - // > > > > - // No National pc87393 SIO is docked, turn off dock power and > > > > - // disable port switch > > > > - // > > > > - // IoWrite8 (SIO_BASE_ADDRESS + 0x0E, 0xbf); > > > > - // IoWrite8 (0x690, 0); > > > > - > > > > - // > > > > - // If no National pc87393, just return > > > > - // > > > > - return ; > > > > - } > > > > -} > > > > - > > > > /** > > > > Check whether the IT8628 SIO present on LPC. If yes, enable its serial ports > > > > > > > > diff --git > > a/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpd > > ateLib/DxeSiliconPolicyUpdateLate.c > > b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUp > > dateLib/DxeSiliconPolicyUpdateLate.c > > index 2eee9958beea..410a8d1073a9 100644 > > --- > > a/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpd > > ateLib/DxeSiliconPolicyUpdateLate.c > > +++ > > b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUp > > dateLib/DxeSiliconPolicyUpdateLate.c > > @@ -88,8 +88,8 @@ SiliconPolicyUpdateLate ( > > // GOP Dxe Policy Initialization > > > > // > > > > Status = GopPolicyInitDxe (gImageHandle); > > > > - RETURN_ERROR (Status); > > > > DEBUG ((DEBUG_INFO, "GOP Dxe Policy Initialization done\n")); > > > > + ASSERT_EFI_ERROR (Status); > > > > } > > > > > > > > return Policy; > > > > -- > > 2.25.1 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v3 14/46] Silicon/Phytium: Added Acpi support to FT2000/4 2021-03-12 10:55 [PATCH v3 00/46] Added support for FT2000/4 chip Ling Jia 2021-03-12 10:55 ` [PATCH v3 01/46] TigerlakeOpenBoardPkg: Fix build errors with GCC5 Ling Jia @ 2021-03-12 10:55 ` Ling Jia 1 sibling, 0 replies; 6+ messages in thread From: Ling Jia @ 2021-03-12 10:55 UTC (permalink / raw) To: devel; +Cc: Leif Lindholm, Peng Xie, Yiqi Shu, Ling Jia Added Acpi driver and table to FT2000/4, the ACPI Tables providing library AcpiTables.inf uses a lot of information that is available in the form of PCDs for differnt platforms. v3: Optimize code to conform to specifications. Signed-off-by: Ling Jia <jialing@phytium.com.cn> Reviewed-by: Leif Lindholm <leif@nuviainc.com> --- Platform/Phytium/DurianPkg/DurianPkg.dsc | 6 + Platform/Phytium/DurianPkg/DurianPkg.fdf | 7 + Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiTables.inf | 56 +++++ Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf | 53 +++++ Silicon/Phytium/PhytiumCommonPkg/Include/Platform.h | 80 +++++++ Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatform.c | 250 ++++++++++++++++++++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiSsdtRootPci.asl | 209 ++++++++++++++++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dbg2.aslc | 80 +++++++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Cpu.asl | 85 +++++++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Dsdt.asl | 15 ++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Uart.asl | 65 +++++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Fadt.aslc | 77 ++++++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Gtdt.aslc | 83 +++++++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Iort.aslc | 89 +++++++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Madt.aslc | 67 ++++++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Mcfg.aslc | 65 +++++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Pptt.aslc | 219 +++++++++++++++++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Spcr.aslc | 73 ++++++ 18 files changed, 1579 insertions(+) diff --git a/Platform/Phytium/DurianPkg/DurianPkg.dsc b/Platform/Phytium/DurianPkg/DurianPkg.dsc index b523ecd6584b..6f38acb6361c 100644 --- a/Platform/Phytium/DurianPkg/DurianPkg.dsc +++ b/Platform/Phytium/DurianPkg/DurianPkg.dsc @@ -279,6 +279,12 @@ [Components.common] # MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + # + # ACPI Support + # + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiTables.inf + Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf # # Bds diff --git a/Platform/Phytium/DurianPkg/DurianPkg.fdf b/Platform/Phytium/DurianPkg/DurianPkg.fdf index 9d75b072c6dc..f435f7cb51c2 100644 --- a/Platform/Phytium/DurianPkg/DurianPkg.fdf +++ b/Platform/Phytium/DurianPkg/DurianPkg.fdf @@ -111,6 +111,13 @@ [FV.FvMain] INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + # + # ACPI Support + # + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + INF RuleOverride=ACPITABLE Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiTables.inf + INF Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf + # # Multiple Console IO support # diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiTables.inf b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiTables.inf new file mode 100644 index 000000000000..e3fd86f19733 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiTables.inf @@ -0,0 +1,56 @@ +#/** @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001b + BASE_NAME = AcpiTables + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + +[Sources] + AcpiSsdtRootPci.asl + Dsdt/Dsdt.asl + Fadt.aslc + Iort.aslc + Gtdt.aslc + Madt.aslc + Mcfg.aslc + Pptt.aslc + Spcr.aslc + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec + +[FixedPcd] + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase + + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate + gArmPlatformTokenSpaceGuid.PL011UartClkInHz + gArmPlatformTokenSpaceGuid.PL011UartInterrupt + + gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase + gArmPlatformTokenSpaceGuid.PcdWatchdogCount diff --git a/Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf b/Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf new file mode 100644 index 000000000000..0f6d46fdba91 --- /dev/null +++ b/Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf @@ -0,0 +1,53 @@ +#/** @file +# Sample ACPI Platform Driver. +# +# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001b + BASE_NAME = AcpiPlatform + FILE_GUID = d51068e8-40dc-11eb-9322-1f6d234e9e6e + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = AcpiPlatformEntryPoint + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[Sources] + AcpiPlatform.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec + +[LibraryClasses] + BaseMemoryLib + DebugLib + DxeServicesLib + UefiLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[Guids] + +[Protocols] + gEfiAcpiTableProtocolGuid ## CONSUMES + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile ## CONSUMES + +[FixedPcd] + gArmTokenSpaceGuid.PcdGicRedistributorsBase + +[Depex] + gEfiAcpiTableProtocolGuid diff --git a/Silicon/Phytium/PhytiumCommonPkg/Include/Platform.h b/Silicon/Phytium/PhytiumCommonPkg/Include/Platform.h new file mode 100644 index 000000000000..d5e3907e377a --- /dev/null +++ b/Silicon/Phytium/PhytiumCommonPkg/Include/Platform.h @@ -0,0 +1,80 @@ +/** @file + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef PHYTIUM_H_ +#define PHYTIUM_H_ + +#include <IndustryStandard/Acpi.h> + +#define EFI_ACPI_6_1_GIC_ITS_INIT(GicITSHwId, GicITSBase) \ + { \ + EFI_ACPI_6_1_GIC_ITS, sizeof (EFI_ACPI_6_1_GIC_ITS_STRUCTURE), EFI_ACPI_RESERVED_WORD, \ + GicITSHwId, GicITSBase, EFI_ACPI_RESERVED_DWORD \ + } + +#define EFI_ACPI_5_1_GICR_STRUCTURE_INIT( \ + GicRBase, GicRlength) \ + { \ + EFI_ACPI_5_1_GICR, sizeof (EFI_ACPI_5_1_GICR_STRUCTURE), EFI_ACPI_RESERVED_WORD, \ + GicRBase, GicRlength \ + } + +#define EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT( \ + ProximityDomain, ACPIProcessorUID, Flags, ClockDomain) \ + { \ + 3, sizeof (EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE),ProximityDomain , \ + ACPIProcessorUID, Flags, ClockDomain \ + } + +#define EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT( \ + ProximityDomain, AddressBaseLow, AddressBaseHigh, LengthLow, LengthHigh, Flags) \ + { \ + 1, sizeof (EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE),ProximityDomain , EFI_ACPI_RESERVED_WORD, \ + AddressBaseLow, AddressBaseHigh, LengthLow, LengthHigh, EFI_ACPI_RESERVED_DWORD, Flags, \ + EFI_ACPI_RESERVED_QWORD \ + } + +#define EFI_ACPI_6_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags, PmuIrq, \ + GicBase, GicVBase, GicHBase, GsivId, GicRBase, ProcessorPowerEfficiencyClass) \ + { \ + EFI_ACPI_6_1_GIC, sizeof (EFI_ACPI_6_1_GIC_STRUCTURE), EFI_ACPI_RESERVED_WORD, \ + GicId, AcpiCpuUid, Flags, 0, PmuIrq, 0, GicBase, GicVBase, GicHBase, \ + GsivId, GicRBase, Mpidr, ProcessorPowerEfficiencyClass, {0, 0, 0} \ + } + +#define EFI_ACPI_6_1_GIC_DISTRIBUTOR_INIT(GicDistHwId, GicDistBase, GicDistVector, GicVersion) \ + { \ + EFI_ACPI_6_1_GICD, sizeof (EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE), EFI_ACPI_RESERVED_WORD, \ + GicDistHwId, GicDistBase, GicDistVector, GicVersion, \ + {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE} \ + } + +// +// ACPI table information used to initialize tables. +// +#define EFI_ACPI_PHYTIUM_OEM_ID 'F','T','-','L','T','D' // OEMID 6 bytes long +#define EFI_ACPI_PHYTIUM_OEM_TABLE_ID SIGNATURE_64('P','H','Y','T','I','U','M',' ') // OEM table id 8 bytes long +#define EFI_ACPI_PHYTIUM_OEM_REVISION 0x20201111 +#define EFI_ACPI_PHYTIUM_CREATOR_ID SIGNATURE_32('P','H','Y','T') +#define EFI_ACPI_PHYTIUM_CREATOR_REVISION 0x20201111 + +// A macro to initialise the common header part of EFI ACPI tables as defined by +// EFI_ACPI_DESCRIPTION_HEADER structure. +#define PHYTIUM_ACPI_HEADER(Signature, Type, Revision) { \ + Signature, /* UINT32 Signature */ \ + sizeof (Type), /* UINT32 Length */ \ + Revision, /* UINT8 Revision */ \ + 0, /* UINT8 Checksum */ \ + { EFI_ACPI_PHYTIUM_OEM_ID }, /* UINT8 OemId[6] */ \ + EFI_ACPI_PHYTIUM_OEM_TABLE_ID, /* UINT64 OemTableId */ \ + EFI_ACPI_PHYTIUM_OEM_REVISION, /* UINT32 OemRevision */ \ + EFI_ACPI_PHYTIUM_CREATOR_ID, /* UINT32 CreatorId */ \ + EFI_ACPI_PHYTIUM_CREATOR_REVISION /* UINT32 CreatorRevision */ \ + } + +#endif diff --git a/Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatform.c b/Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatform.c new file mode 100644 index 000000000000..c48ed74f5386 --- /dev/null +++ b/Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatform.c @@ -0,0 +1,250 @@ +/** @file + Sample ACPI Platform Driver. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <IndustryStandard/Acpi.h> +#include <Library/BaseLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/DebugLib.h> +#include <Library/UefiLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <PiDxe.h> +#include <Protocol/AcpiTable.h> +#include <Protocol/FirmwareVolume2.h> + +/** + Locate the first instance of a protocol. If the protocol requested is an + FV protocol, then it will return the first FV that contains the ACPI table + storage file. + + @param[out] Instance Return pointer to the first instance of the protocol. + + @return EFI_SUCCESS The function completed successfully. + + @return EFI_NOT_FOUND The protocol could not be located. + + @return EFI_OUT_OF_RESOURCES There are not enough resources to find the protocol. + +**/ +EFI_STATUS +LocateFvInstanceWithTables ( + OUT EFI_FIRMWARE_VOLUME2_PROTOCOL **Instance + ) +{ + EFI_STATUS Status; + EFI_HANDLE *HandleBuffer; + UINTN NumberOfHandles; + EFI_FV_FILETYPE FileType; + UINT32 FvStatus; + EFI_FV_FILE_ATTRIBUTES Attributes; + UINTN Size; + UINTN Index; + EFI_FIRMWARE_VOLUME2_PROTOCOL *FvInstance; + + FvStatus = 0; + + // + // Locate protocol. + // + Status = gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiFirmwareVolume2ProtocolGuid, + NULL, + &NumberOfHandles, + &HandleBuffer + ); + if (EFI_ERROR (Status)) { + // + // Defined errors at this time are not found and out of resources. + // + return Status; + } + + // + // Looking for FV with ACPI storage file + // + + for (Index = 0; Index < NumberOfHandles; Index++) { + // + // Get the protocol on this handle + // This should not fail because of LocateHandleBuffer + // + Status = gBS->HandleProtocol ( + HandleBuffer[Index], + &gEfiFirmwareVolume2ProtocolGuid, + (VOID **)&FvInstance + ); + ASSERT_EFI_ERROR (Status); + + // + // See if it has the ACPI storage file + // + Status = FvInstance->ReadFile ( + FvInstance, + (EFI_GUID *)PcdGetPtr (PcdAcpiTableStorageFile), + NULL, + &Size, + &FileType, + &Attributes, + &FvStatus + ); + + // + // If we found it, then we are done + // + if (Status == EFI_SUCCESS) { + *Instance = FvInstance; + break; + } + } + + // + // Free any allocated buffers + // + gBS->FreePool (HandleBuffer); + + return Status; +} + + +/** + This function calculates and updates an UINT8 checksum. + + @param[in] Buffer Pointer to buffer to checksum. + + @param[in] Size Number of bytes to checksum. + +**/ +VOID +AcpiPlatformChecksum ( + IN UINT8 *Buffer, + IN UINTN Size + ) +{ + UINTN ChecksumOffset; + + ChecksumOffset = OFFSET_OF (EFI_ACPI_DESCRIPTION_HEADER, Checksum); + + // + // Set checksum to 0 first + // + Buffer[ChecksumOffset] = 0; + + // + // Update checksum value + // + Buffer[ChecksumOffset] = CalculateCheckSum8 (Buffer, Size); +} + + +/** + This function is the entrypoint of the acpi platform. + + @param[in] ImageHandle The firmware allocated handle for the EFI image. + + @param[in] SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + + @retval other Some error occurs when executing this entry point. + +**/ +EFI_STATUS +EFIAPI +AcpiPlatformEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_ACPI_TABLE_PROTOCOL *AcpiTable; + EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol; + INTN Instance; + EFI_ACPI_COMMON_HEADER *CurrentTable; + UINTN TableHandle; + UINT32 FvStatus; + UINTN TableSize; + UINTN Size; + + Instance = 0; + CurrentTable = NULL; + TableHandle = 0; + + // + // Find the AcpiTable protocol + // + Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID **)&AcpiTable); + if (EFI_ERROR (Status)) { + return EFI_ABORTED; + } + + // + // Locate the firmware volume protocol + // + Status = LocateFvInstanceWithTables (&FwVol); + if (EFI_ERROR (Status)) { + return EFI_ABORTED; + } + // + // Read tables from the storage file. + // + while (Status == EFI_SUCCESS) { + + Status = FwVol->ReadSection ( + FwVol, + (EFI_GUID *)PcdGetPtr (PcdAcpiTableStorageFile), + EFI_SECTION_RAW, + Instance, + (VOID **)&CurrentTable, + &Size, + &FvStatus + ); + if ( ! EFI_ERROR (Status)) { + // + // Add the table + // + TableHandle = 0; + + TableSize = ((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable)->Length; + ASSERT (Size >= TableSize); + + // + // Checksum ACPI table + // + AcpiPlatformChecksum ((UINT8 *)CurrentTable, TableSize); + + // + // Install ACPI table + // + Status = AcpiTable->InstallAcpiTable ( + AcpiTable, + CurrentTable, + TableSize, + &TableHandle + ); + + // + // Free memory allocated by ReadSection + // + gBS->FreePool (CurrentTable); + + if (EFI_ERROR (Status)) { + return EFI_ABORTED; + } + + // + // Increment the instance + // + Instance++; + CurrentTable = NULL; + } + } + + return EFI_SUCCESS; +} + diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiSsdtRootPci.asl b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiSsdtRootPci.asl new file mode 100644 index 000000000000..667f8cc8fb65 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiSsdtRootPci.asl @@ -0,0 +1,209 @@ +/** @file + Phytium ACPI ASL Sources. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <Platform.h> + +#define LNK_DEVICE(Unique_Id, Link_Name, irq) \ + Device (Link_Name) { \ + Name (_HID, EISAID ("PNP0C0F")) \ + Name (_UID, Unique_Id) \ + Name (_PRS, ResourceTemplate () { \ + Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive) { irq } \ + }) \ + Method (_CRS, 0) { Return (_PRS) } \ + Method (_SRS, 1) { } \ + Method (_DIS) { } \ + } + +#define PRT_ENTRY(Address, Pin, Link) \ + Package (4) { \ + Address, \ + Pin, \ + Link, \ + Zero \ + } + +#define ROOT_PRT_ENTRY(Dev, Pin, Link) PRT_ENTRY(Dev * 0x10000 + 0xFFFF, Pin, Link) + + +DefinitionBlock ("SsdtPci.aml", "SSDT", 2, "FT-LTD", "PHYTIUM ", EFI_ACPI_PHYTIUM_OEM_REVISION) { + Scope (_SB) { + // + // PCI Root Complex + // + LNK_DEVICE (1, LNKA, 60) + LNK_DEVICE (2, LNKB, 61) + LNK_DEVICE (3, LNKC, 62) + LNK_DEVICE (4, LNKD, 63) + + // reserve ECAM memory range + Device (RES0) + { + Name (_HID, EISAID ("PNP0C02")) + Name (_UID, 0) + Name (_CRS, ResourceTemplate () { + QWordMemory (ResourceConsumer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0, // Granularity + 0x40000000, // Range Minimum + 0x4FFFFFFF, // Range Maximum + 0, // Translation Offset + 0x10000000, // Length + ,,) + }) + } + + Device (PCI0) + { + Name (_HID, EISAID ("PNP0A08")) // PCI Express Root Bridge + Name (_CID, EISAID ("PNP0A03")) // Compatible PCI Root Bridge + Name (_SEG, Zero) // PCI Segment Group number + Name (_BBN, 0) // PCI Base Bus Number + Name (_CCA, 1) + + // Root Complex + Device (RP0) { + Name (_ADR, 0x00000000) // Dev 0, Func 0 + } + // PCI Routing Table + Name (_PRT, Package () { + ROOT_PRT_ENTRY (0, 0, LNKA), // INTA + ROOT_PRT_ENTRY (0, 1, LNKB), // INTB + ROOT_PRT_ENTRY (0, 2, LNKC), // INTC + ROOT_PRT_ENTRY (0, 3, LNKD), // INTD + + ROOT_PRT_ENTRY (1, 0, LNKA), // INTA + ROOT_PRT_ENTRY (1, 1, LNKB), // INTB + ROOT_PRT_ENTRY (1, 2, LNKC), // INTC + ROOT_PRT_ENTRY (1, 3, LNKD), // INTD + + ROOT_PRT_ENTRY (2, 0, LNKA), // INTA + ROOT_PRT_ENTRY (2, 1, LNKB), // INTB + ROOT_PRT_ENTRY (2, 2, LNKC), // INTC + ROOT_PRT_ENTRY (2, 3, LNKD), // INTD + + ROOT_PRT_ENTRY (3, 0, LNKA), // INTA + ROOT_PRT_ENTRY (3, 1, LNKB), // INTB + ROOT_PRT_ENTRY (3, 2, LNKC), // INTC + ROOT_PRT_ENTRY (3, 3, LNKD), // INTD + + ROOT_PRT_ENTRY (4, 0, LNKA), // INTA + ROOT_PRT_ENTRY (4, 1, LNKB), // INTB + ROOT_PRT_ENTRY (4, 2, LNKC), // INTC + ROOT_PRT_ENTRY (4, 3, LNKD), // INTD + + ROOT_PRT_ENTRY (5, 0, LNKA), // INTA + ROOT_PRT_ENTRY (5, 1, LNKB), // INTB + ROOT_PRT_ENTRY (5, 2, LNKC), // INTC + ROOT_PRT_ENTRY (5, 3, LNKD), // INTD + }) + + // Root complex resources + Method (_CRS, 0, Serialized) { + Name (RBUF, ResourceTemplate () { + WordBusNumber ( + ResourceProducer, + MinFixed, MaxFixed, PosDecode, + 0, // AddressGranularity + 0, // AddressMinimum - Minimum Bus Number + 255, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 256 // RangeLength - Number of Busses + ) + + DWordMemory ( // 32-bit BAR Windows + ResourceProducer, PosDecode, + MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x58000000, // Min Base Address + 0x7FFFFFFF, // Max Base Address + 0x00000000, // Translate + 0x28000000 // Length + ) + + QWordMemory ( // 64-bit BAR Windows + ResourceProducer, PosDecode, + MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x1000000000, // Min Base Address + 0x1FFFFFFFFF, // Max Base Address + 0x0000000000, // Translate + 0x1000000000 // Length + ) + + DWordIo ( // IO window + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x00000000, // Granularity + 0x00000000, // Min Base Address + 0x00efffff, // Max Base Address + 0x50000000, // Translate + 0x00f00000, // Length + ,,, TypeTranslation + ) + }) // Name(RBUF) + + Return (RBUF) + } // Method(_CRS) + + // + // OS Control Handoff + // + Name (SUPP, Zero) // PCI _OSC Support Field value + Name (CTRL, Zero) // PCI _OSC Control Field value + + /* + See [1] 6.2.10, [2] 4.5 + */ + Method (_OSC, 4) { + // Check for proper UUID + If (LEqual (Arg0, ToUUID ("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + // Create DWord-adressable fields from the Capabilities Buffer + CreateDWordField (Arg3, 0, CDW1) + CreateDWordField (Arg3, 4, CDW2) + CreateDWordField (Arg3, 8, CDW3) + + // Save Capabilities DWord2 & 3 + Store (CDW2, SUPP) + Store (CDW3, CTRL) + + // Only allow native hot plug control if OS supports: + // * ASPM + // * Clock PM + // * MSI/MSI-X + If (LNotEqual (And (SUPP, 0x16), 0x16)) { + And (CTRL, 0x1E, CTRL) // Mask bit 0 (and undefined bits) + } + + // Do not allow native PME, AER (no dependencies) + // Never allow SHPC (no SHPC controller in this system) + And (CTRL, 0x10, CTRL) + + If (LNotEqual (Arg1, One)) { // Unknown revision + Or (CDW1, 0x08, CDW1) + } + + If (LNotEqual (CDW3, CTRL)) { // Capabilities bits were masked + Or (CDW1, 0x10, CDW1) + } + // Update DWORD3 in the buffer + Store (CTRL, CDW3) + Return (Arg3) + } Else { + Or (CDW1, 4, CDW1) // Unrecognized UUID + Return (Arg3) + } + } + } + } +} diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dbg2.aslc b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dbg2.aslc new file mode 100644 index 000000000000..5349f6364b3d --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dbg2.aslc @@ -0,0 +1,80 @@ +/** @file + Phytium ACPI ASL Sources. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <IndustryStandard/Acpi.h> +#include <IndustryStandard/DebugPort2Table.h> +#include <Library/AcpiLib.h> +#include <Library/ArmLib.h> +#include <Library/PcdLib.h> +#include <Platform.h> + +#define NUMBER_DEBUG_DEVICE_INFO 1 +#define NUMBER_OF_GENERIC_ADDRESS 1 +#define NAMESPACE_STRING_SIZE 8 + +#pragma pack(1) + +typedef struct { + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT DdiHeader; + EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE Address[NUMBER_OF_GENERIC_ADDRESS]; + UINT32 AddressSize[NUMBER_OF_GENERIC_ADDRESS]; + CHAR8 NamespaceString[NAMESPACE_STRING_SIZE]; +} EFI_ACPI_DBG2_DDI_STRUCT; + +typedef struct { + EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Desc; + EFI_ACPI_DBG2_DDI_STRUCT Ddi[NUMBER_DEBUG_DEVICE_INFO]; +} EFI_ACPI_DEBUG_PORT_2_TABLE; + +#pragma pack() + +EFI_ACPI_DEBUG_PORT_2_TABLE Dbg2 = { + { + PHYTIUM_ACPI_HEADER ( + EFI_ACPI_6_1_DEBUG_PORT_2_TABLE_SIGNATURE, + EFI_ACPI_DEBUG_PORT_2_TABLE, + EFI_ACPI_DEBUG_PORT_2_TABLE_REVISION + ), + OFFSET_OF (EFI_ACPI_DEBUG_PORT_2_TABLE, Ddi), + NUMBER_DEBUG_DEVICE_INFO + }, + { + { + { + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION, + sizeof (EFI_ACPI_DBG2_DDI_STRUCT), + NUMBER_OF_GENERIC_ADDRESS, + NAMESPACE_STRING_SIZE, + OFFSET_OF (EFI_ACPI_DBG2_DDI_STRUCT, NamespaceString), + 0, + 0, + EFI_ACPI_DBG2_PORT_TYPE_SERIAL, + EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_PL011_UART, + {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}, + OFFSET_OF (EFI_ACPI_DBG2_DDI_STRUCT, Address), + OFFSET_OF (EFI_ACPI_DBG2_DDI_STRUCT, AddressSize), + }, + { + { + EFI_ACPI_6_1_SYSTEM_MEMORY, + 32, + 0, + EFI_ACPI_6_1_DWORD, + FixedPcdGet64 (PcdSerialRegisterBase) + } + }, + { + 0x1000 + }, + "COM0" + } + } +}; + +VOID * CONST ReferenceAcpiTable = &Dbg2; diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Cpu.asl b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Cpu.asl new file mode 100644 index 000000000000..219a129fa540 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Cpu.asl @@ -0,0 +1,85 @@ +/** @file + Phytium ACPI ASL Sources. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Scope (_SB) +{ + Device (CLU0) { + Name (_HID, "ACPI0010") + Name (_UID, 0) + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + Device (CPU0) { + Name (_HID, "ACPI0007") + Name (_UID, 0) + Name (_DSD, Package () { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"clock-name", "c0"}, + Package () {"clock-domain", 0}, + } + }) + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + } + + Device (CPU1) { + Name (_HID, "ACPI0007") + Name (_UID, 1) + Name (_DSD, Package () { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"clock-name", "c0"}, + Package () {"clock-domain", 0}, + } + }) + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + } + } + + Device (CLU1) { + Name (_HID, "ACPI0010") + Name (_UID, 1) + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + Device (CPU2) { + Name (_HID, "ACPI0007") + Name (_UID, 2) + Name (_DSD, Package () { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"clock-name", "c1"}, + Package () {"clock-domain", 1}, + } + }) + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + } + + Device (CPU3) { + Name (_HID, "ACPI0007") + Name (_UID, 3) + Name (_DSD, Package () { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"clock-name", "c1"}, + Package () {"clock-domain", 1}, + } + }) + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + } + } +} diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Dsdt.asl b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Dsdt.asl new file mode 100644 index 000000000000..b21431ca36dc --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Dsdt.asl @@ -0,0 +1,15 @@ +/** @file + Phytium ACPI ASL Sources. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <Platform.h> + +DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "FT-LTD", "PHYTIUM ", EFI_ACPI_PHYTIUM_OEM_REVISION) { + include ("Cpu.asl") + include ("Uart.asl") +} diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Uart.asl b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Uart.asl new file mode 100644 index 000000000000..25752036b550 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Uart.asl @@ -0,0 +1,65 @@ +/** @file + Phytium ACPI ASL Sources. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Scope (_SB) +{ + //UART 0 + Device (UAR0) { + Name (_HID, "ARMH0011") + Name (_UID, 0) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0x28000000, 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 38 } + }) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + } + + //UART 1 + Device (UAR1) { + Name (_HID, "ARMH0011") + Name (_UID, 1) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0x28001000, 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {39} + }) + + Method (_STA, 0, NotSerialized) { Return (0x0F) } + } + + //UART 2 + Device (UAR2) { + Name (_HID, "ARMH0011") + Name (_UID, 2) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0x28002000, 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {40} + }) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + } + + //UART 3 + Device (UAR3) { + Name (_HID, "ARMH0011") + Name (_UID, 3) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0x28003000, 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {41} + }) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + } +} diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Fadt.aslc b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Fadt.aslc new file mode 100644 index 000000000000..10612c136876 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Fadt.aslc @@ -0,0 +1,77 @@ +/** @file + Phytium ACPI ASL Sources. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <IndustryStandard/Acpi.h> +#include <Library/AcpiLib.h> +#include <Platform.h> + +EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = { + PHYTIUM_ACPI_HEADER ( + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE, + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION + ), + 0, // UINT32 FirmwareCtrl + 0, // UINT32 Dsdt + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0 + EFI_ACPI_6_1_PM_PROFILE_ENTERPRISE_SERVER, // UINT8 PreferredPmProfile + 0, // UINT16 SciInt + 0, // UINT32 SmiCmd + 0, // UINT8 AcpiEnable + 0, // UINT8 AcpiDisable + 0, // UINT8 S4BiosReq + 0, // UINT8 PstateCnt + 0, // UINT32 Pm1aEvtBlk + 0, // UINT32 Pm1bEvtBlk + 0, // UINT32 Pm1aCntBlk + 0, // UINT32 Pm1bCntBlk + 0, // UINT32 Pm2CntBlk + 0, // UINT32 PmTmrBlk + 0, // UINT32 Gpe0Blk + 0, // UINT32 Gpe1Blk + 0, // UINT8 Pm1EvtLen + 0, // UINT8 Pm1CntLen + 0, // UINT8 Pm2CntLen + 0, // UINT8 PmTmrLen + 0, // UINT8 Gpe0BlkLen + 0, // UINT8 Gpe1BlkLen + 0, // UINT8 Gpe1Base + 0, // UINT8 CstCnt + 0, // UINT16 PLvl2Lat + 0, // UINT16 PLvl3Lat + 0, // UINT16 FlushSize + 0, // UINT16 FlushStride + 0, // UINT8 DutyOffset + 0, // UINT8 DutyWidth + 0, // UINT8 DayAlrm + 0, // UINT8 MonAlrm + 0, // UINT8 Century + 0, // UINT16 IaPcBootArch + 0, // UINT8 Reserved1 + EFI_ACPI_6_1_HW_REDUCED_ACPI | EFI_ACPI_6_1_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE ResetReg + 0, // UINT8 ResetValue + EFI_ACPI_6_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision + 0, // UINT64 XFirmwareCtrl + 0, // UINT64 XDsdt + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPm2CntBlk + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPmTmrBlk + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XGpe0Blk + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XGpe1Blk + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE SleepControlReg + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE SleepStatusReg + 0 // UINT64 Hypervisor Vendor Identify +}; + +VOID * CONST ReferenceAcpiTable = &Fadt; diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Gtdt.aslc b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Gtdt.aslc new file mode 100644 index 000000000000..67468db2d4bd --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Gtdt.aslc @@ -0,0 +1,83 @@ +/** @file + Phytium ACPI ASL Sources. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <IndustryStandard/Acpi.h> +#include <Library/AcpiLib.h> +#include <Library/PcdLib.h> +#include <Platform.h> + +#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_6_1_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT +#define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0 +#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_6_1_GTDT_GLOBAL_FLAG_INTERRUPT_MODE +#define GTDT_GLOBAL_FLAGS_LEVEL 0 + +#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE +#define GTDT_TIMER_LEVEL_TRIGGERED 0 +#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY +#define GTDT_TIMER_ACTIVE_HIGH 0 +#define GTDT_TIMER_ALWAYS_ON_CAPABILITY EFI_ACPI_6_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY + +#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED \ + | EFI_ACPI_6_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY) + +#pragma pack (1) + +typedef struct { + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; + EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[2]; +} EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES; + +#pragma pack () + +EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { + { + PHYTIUM_ACPI_HEADER ( + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES, + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION + ), + 0xFFFFFFFFFFFFFFFF, // UINT64 PhysicalAddress + 0, // UINT32 Reserved + FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags + FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags + FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags + FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags + 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress + 2, + sizeof (EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE) + }, + + { + { + 1, //Type + 28, //Size of this structure + 0, //reserved + 0x2800a000, //RefreshFrame Physical Address + 0x2800b000, //WatchdogControlFrame Physical Address + 48, //Watchdog Timer GSIV + 0, //Watchdog Timer Flags high level + }, + + { + 1, + 28, + 0, + 0x28016000, + 0x28017000, + 49, + 0, + } + } +}; + +VOID * CONST ReferenceAcpiTable = &Gtdt; diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Iort.aslc b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Iort.aslc new file mode 100644 index 000000000000..4239499b68e5 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Iort.aslc @@ -0,0 +1,89 @@ +/** @file + Phytium ACPI ASL Sources. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <IndustryStandard/IoRemappingTable.h> +#include <Platform.h> + +#define FIELD_OFFSET(type, name) __builtin_offsetof(type, name) + +#pragma pack(1) +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE Node; + UINT32 Identifiers[1]; +} PHYTIUM_ITS_NODE; + +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_RC_NODE Node; + EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping; +} PHYTIUM_RC_NODE; + +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort; + PHYTIUM_ITS_NODE ItsNode; + PHYTIUM_RC_NODE RcNode[1]; +} PHYTIUM_IO_REMAPPING_STRUCTURE; + +#define __PHYTIUM_ID_MAPPING(In, Num, Out, Ref, Flags) \ + { \ + In, \ + Num, \ + Out, \ + FIELD_OFFSET (PHYTIUM_IO_REMAPPING_STRUCTURE, Ref), \ + Flags \ + } + +STATIC PHYTIUM_IO_REMAPPING_STRUCTURE Iort = { + { + PHYTIUM_ACPI_HEADER (EFI_ACPI_6_0_IO_REMAPPING_TABLE_SIGNATURE, + PHYTIUM_IO_REMAPPING_STRUCTURE, + EFI_ACPI_IO_REMAPPING_TABLE_REVISION), + 2, // NumNodes + sizeof (EFI_ACPI_6_0_IO_REMAPPING_TABLE), // NodeOffset + 0 // Reserved + }, { + // ItsNode + { + { + EFI_ACPI_IORT_TYPE_ITS_GROUP, // Type + sizeof (PHYTIUM_ITS_NODE), // Length + 0x0, // Revision + 0x0, // Reserved + 0x0, // NumIdMappings + 0x0, // IdReference + }, + 1, + }, { + 0x0 + }, + }, { + { + // PciRcNode + { + { + EFI_ACPI_IORT_TYPE_ROOT_COMPLEX, // Type + sizeof (PHYTIUM_RC_NODE), // Length + 0x0, // Revision + 0x0, // Reserved + 0x1, // NumIdMappings + FIELD_OFFSET (PHYTIUM_RC_NODE, RcIdMapping), // IdReference + }, + EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, // CacheCoherent + 0x0, // AllocationHints + 0x0, // Reserved + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM, // MemoryAccessFlags + EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED, // AtsAttribute + 0x0, // PciSegmentNumber + }, + __PHYTIUM_ID_MAPPING (0x0, 0xffff, 0x0, ItsNode, 0), + } + } +}; +#pragma pack() +# +VOID * CONST ReferenceAcpiTable = &Iort; diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Madt.aslc b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Madt.aslc new file mode 100644 index 000000000000..ef6d94837fa2 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Madt.aslc @@ -0,0 +1,67 @@ +/** @file + Phytium ACPI ASL Sources. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <IndustryStandard/Acpi.h> +#include <Library/AcpiLib.h> +#include <Library/ArmLib.h> +#include <Library/PcdLib.h> +#include <Platform.h> + + +#define PLATFORM_GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId)) + +#define EFI_GICC_STRUCTURE(AcpiCpuUid, Mpidr, GicRBaseOffset) \ + EFI_ACPI_6_1_GICC_STRUCTURE_INIT(0, AcpiCpuUid, Mpidr, EFI_ACPI_6_1_GIC_ENABLED, 23, \ + FixedPcdGet64(PcdGicInterruptInterfaceBase), FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, \ + FixedPcdGet64(PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicRedistributorsBase) + GicRBaseOffset, 0) +#define CORE_NUM 4 +// +// Multiple APIC Description Table +// +#pragma pack (1) + +typedef struct { + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_6_1_GIC_STRUCTURE GicInterfaces[CORE_NUM]; + EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; + EFI_ACPI_6_1_GIC_ITS_STRUCTURE GicITS[1]; +} EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE; + +#pragma pack () + +// +// Multiple APIC Description Table +// +EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { + { + PHYTIUM_ACPI_HEADER ( + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE, + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION + ), + // + // MADT specific fields + // + 0, // LocalApicAddress + 0, // Flags + }, + { + EFI_GICC_STRUCTURE (0x00, PLATFORM_GET_MPID (0x00, 0), 0x000000), + EFI_GICC_STRUCTURE (0x01, PLATFORM_GET_MPID (0x00, 1), 0x020000), + EFI_GICC_STRUCTURE (0x02, PLATFORM_GET_MPID (0x01, 0), 0x040000), + EFI_GICC_STRUCTURE (0x03, PLATFORM_GET_MPID (0x01, 1), 0x060000), + }, + + EFI_ACPI_6_1_GIC_DISTRIBUTOR_INIT (0, FixedPcdGet32 (PcdGicDistributorBase), 0, 0x3), + { + EFI_ACPI_6_1_GIC_ITS_INIT (0, FixedPcdGet64 (PcdGicDistributorBase) + 0x20000), + } +}; + +VOID * CONST ReferenceAcpiTable = &Madt; diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Mcfg.aslc b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Mcfg.aslc new file mode 100644 index 000000000000..34eebd6aeec9 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Mcfg.aslc @@ -0,0 +1,65 @@ +/** @file + Phytium ACPI ASL Sources. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <IndustryStandard/Acpi.h> +#include <Platform.h> + +#define ACPI_6_1_MCFG_VERSION 0x1 + +#pragma pack(1) +typedef struct +{ + UINT64 BaseAddress; + UINT16 SegGroupNum; + UINT8 StartBusNum; + UINT8 EndBusNum; + UINT32 Reserved2; +} EFI_ACPI_6_1_MCFG_CONFIG_STRUCTURE; + +typedef struct +{ + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT64 Reserved1; +} EFI_ACPI_6_1_MCFG_TABLE_CONFIG; + +typedef struct +{ + EFI_ACPI_6_1_MCFG_TABLE_CONFIG Acpi_Table_Mcfg; + EFI_ACPI_6_1_MCFG_CONFIG_STRUCTURE Config_Structure[1]; +} EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE; +#pragma pack() + +EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg= +{ + { + { + EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, + sizeof (EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE), + ACPI_6_1_MCFG_VERSION, + 0x00, // Checksum will be updated at runtime + {EFI_ACPI_PHYTIUM_OEM_ID}, + EFI_ACPI_PHYTIUM_OEM_TABLE_ID, + EFI_ACPI_PHYTIUM_OEM_REVISION, + EFI_ACPI_PHYTIUM_CREATOR_ID, + EFI_ACPI_PHYTIUM_CREATOR_REVISION + }, + 0x0000000000000000, //Reserved + }, + { + { + 0x40000000, //Base Address + 0, //Segment Group Number + 0, //Start Bus Number + 0xff, //End Bus Number + 0x00000000, //Reserved + }, + } +}; + +VOID * CONST ReferenceAcpiTable = &Mcfg; diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Pptt.aslc b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Pptt.aslc new file mode 100644 index 000000000000..ae1a21df23b9 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Pptt.aslc @@ -0,0 +1,219 @@ +/** @file + Phytium ACPI ASL Sources. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <IndustryStandard/Acpi.h> +#include <Platform.h> + +#define FIELD_OFFSET(type, name) __builtin_offsetof(type, name) + +#pragma pack(1) +typedef struct { + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Core; + UINT32 Offset[2]; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE DCache; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE ICache; +} PHYTIUM_PPTT_CORE; + +typedef struct { + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Cluster; + UINT32 Offset[1]; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L2Cache; + PHYTIUM_PPTT_CORE Cores[2]; +} PHYTIUM_PPTT_CLUSTER; + +typedef struct { + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Package; + UINT32 Offset[1]; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L3Cache; + PHYTIUM_PPTT_CLUSTER Clusters[2]; + EFI_ACPI_6_2_PPTT_STRUCTURE_ID ID; +} PHYTIUM_PPTT_PACKAGE; + +typedef struct { + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Pptt; + PHYTIUM_PPTT_PACKAGE Packages[1]; +} PHYTIUM_PPTT_TABLE; +#pragma pack() + +#define PPTT_CORE(pid, cid, id) { \ + { \ + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, \ + FIELD_OFFSET (PHYTIUM_PPTT_CORE, DCache), \ + {}, \ + { \ + 0, /* PhysicalPackage */ \ + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID, /* AcpiProcessorIdValid */ \ + }, \ + FIELD_OFFSET (PHYTIUM_PPTT_TABLE, \ + Packages[pid].Clusters[cid]), /* Parent */ \ + 8 * (pid) + 4 * (cid) + (id), /* AcpiProcessorId */ \ + 2, /* NumberOfPrivateResources */\ + }, { \ + FIELD_OFFSET (PHYTIUM_PPTT_TABLE, \ + Packages[pid].Clusters[cid].Cores[id].DCache), \ + FIELD_OFFSET (PHYTIUM_PPTT_TABLE, \ + Packages[pid].Clusters[cid].Cores[id].ICache), \ + }, { \ + EFI_ACPI_6_2_PPTT_TYPE_CACHE, \ + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \ + {}, \ + { \ + 1, /* SizePropertyValid */ \ + 1, /* NumberOfSetsValid */ \ + 1, /* AssociativityValid */ \ + 1, /* AllocationTypeValid */ \ + 1, /* CacheTypeValid */ \ + 1, /* WritePolicyValid */ \ + 1, /* LineSizeValid */ \ + }, \ + 0, /* NextLevelOfCache */ \ + SIZE_32KB, /* Size */ \ + 256, /* NumberOfSets */ \ + 2, /* Associativity */ \ + { \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \ + }, \ + 64 /* LineSize */ \ + }, { \ + EFI_ACPI_6_2_PPTT_TYPE_CACHE, \ + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \ + {}, \ + { \ + 1, /* SizePropertyValid */ \ + 1, /* NumberOfSetsValid */ \ + 1, /* AssociativityValid */ \ + 1, /* AllocationTypeValid */ \ + 1, /* CacheTypeValid */ \ + 0, /* WritePolicyValid */ \ + 1, /* LineSizeValid */ \ + }, \ + 0, /* NextLevelOfCache */ \ + SIZE_32KB, /* Size */ \ + 256, /* NumberOfSets */ \ + 2, /* Associativity */ \ + { \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ, /* AllocationType */ \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, \ + 0, /* WritePolicy */ \ + }, \ + 64 /* LineSize */ \ + } \ +} + +#define PPTT_CLUSTER(pid, cid) { \ + { \ + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, \ + FIELD_OFFSET (PHYTIUM_PPTT_CLUSTER, L2Cache), \ + {}, \ + { \ + 0, /* PhysicalPackage */ \ + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ \ + }, \ + FIELD_OFFSET (PHYTIUM_PPTT_TABLE, Packages[pid]), /* Parent */ \ + 0, /* AcpiProcessorId */ \ + 1, /* NumberOfPrivateResources */ \ + }, { \ + FIELD_OFFSET (PHYTIUM_PPTT_TABLE, Packages[pid].Clusters[cid].L2Cache), \ + }, { \ + EFI_ACPI_6_2_PPTT_TYPE_CACHE, \ + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \ + {}, \ + { \ + 1, /* SizePropertyValid */ \ + 1, /* NumberOfSetsValid */ \ + 1, /* AssociativityValid */ \ + 1, /* AllocationTypeValid */ \ + 1, /* CacheTypeValid */ \ + 1, /* WritePolicyValid */ \ + 1, /* LineSizeValid */ \ + }, \ + 0, /* NextLevelOfCache */ \ + SIZE_2MB, /* Size */ \ + 2048, /* NumberOfSets */ \ + 16, /* Associativity */ \ + { \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \ + }, \ + 64 /* LineSize */ \ + }, { \ + PPTT_CORE (pid, cid, 0), \ + PPTT_CORE (pid, cid, 1), \ + } \ +} + +#define PPTT_PANEL(pid) { \ + { \ + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, \ + FIELD_OFFSET (PHYTIUM_PPTT_PACKAGE, L3Cache), \ + {}, \ + { \ + 1, /* PhysicalPackage */ \ + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ \ + }, \ + 0, /* Parent */ \ + 0, /* AcpiProcessorId */ \ + 1, /* NumberOfPrivateResources */ \ + }, { \ + FIELD_OFFSET (PHYTIUM_PPTT_TABLE, Packages[pid].L3Cache), \ + }, { \ + EFI_ACPI_6_2_PPTT_TYPE_CACHE, \ + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \ + {}, \ + { \ + 1, /* SizePropertyValid */ \ + 1, /* NumberOfSetsValid */ \ + 1, /* AssociativityValid */ \ + 0, /* AllocationTypeValid */ \ + 1, /* CacheTypeValid */ \ + 1, /* WritePolicyValid */ \ + 1, /* LineSizeValid */ \ + }, \ + 0, /* NextLevelOfCache */ \ + SIZE_4MB, /* Size */ \ + 4096, /* NumberOfSets */ \ + 16, /* Associativity */ \ + { \ + 0, \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \ + }, \ + 64 /* LineSize */ \ + }, { \ + PPTT_CLUSTER (pid, 0), \ + PPTT_CLUSTER (pid, 1), \ + }, { \ + EFI_ACPI_6_2_PPTT_TYPE_ID, \ + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID), \ + {0}, \ + 0x54594850, \ + 0x3, \ + 0x1, \ + 0, \ + 0, \ + 0, \ + } \ +} + + +STATIC PHYTIUM_PPTT_TABLE mPhytiumPpttTable = { + { + PHYTIUM_ACPI_HEADER (EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + PHYTIUM_PPTT_TABLE, + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION), + }, + { + PPTT_PANEL (0) + } +}; + +VOID * CONST ReferenceAcpiTable = &mPhytiumPpttTable; diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Spcr.aslc b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Spcr.aslc new file mode 100644 index 000000000000..00ffb7e7a90d --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Spcr.aslc @@ -0,0 +1,73 @@ +/** @file + Phytium ACPI ASL Sources. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <IndustryStandard/Acpi.h> +#include <IndustryStandard/SerialPortConsoleRedirectionTable.h> +#include <Library/AcpiLib.h> +#include <Library/ArmLib.h> +#include <Library/PcdLib.h> +#include <Platform.h> + +/// +/// SPCR Flow Control +/// +#define SPCR_FLOW_CONTROL_NONE 0 + + +STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = { + PHYTIUM_ACPI_HEADER (EFI_ACPI_5_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION), + // UINT8 InterfaceType; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART, + // UINT8 Reserved1[3]; + { + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE + }, + // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE BaseAddress; + ARM_GAS32 (FixedPcdGet64 (PcdSerialRegisterBase)), + // UINT8 InterruptType; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC, + // UINT8 Irq; + 0, // Not used on ARM + // UINT32 GlobalSystemInterrupt; + FixedPcdGet32 (PL011UartInterrupt), + // UINT8 BaudRate; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200, + // UINT8 Parity; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY, + // UINT8 StopBits; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1, + // UINT8 FlowControl; + SPCR_FLOW_CONTROL_NONE, + // UINT8 TerminalType; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI, + // UINT8 Reserved2; + EFI_ACPI_RESERVED_BYTE, + // UINT16 PciDeviceId; + 0xFFFF, + // UINT16 PciVendorId; + 0xFFFF, + // UINT8 PciBusNumber; + 0x00, + // UINT8 PciDeviceNumber; + 0x00, + // UINT8 PciFunctionNumber; + 0x00, + // UINT32 PciFlags; + 0x00000000, + // UINT8 PciSegment; + 0x00, + // UINT32 Reserved3; + EFI_ACPI_RESERVED_DWORD +}; + +VOID * CONST ReferenceAcpiTable = &Spcr; -- 2.25.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v3 00/46] Added support for FT2000/4 chip @ 2021-03-12 11:01 Ling Jia 2021-03-12 11:01 ` [PATCH v3 14/46] Silicon/Phytium: Added Acpi support to FT2000/4 Ling Jia 0 siblings, 1 reply; 6+ messages in thread From: Ling Jia @ 2021-03-12 11:01 UTC (permalink / raw) To: devel; +Cc: Leif Lindholm, Peng Xie, Yiqi Shu, Ling Jia The modules could be runed at the silicon of FT2000/4. They supported Acpi parameter configuration, Pci bus scaning, flash read-write and erase abd operating system boot function. Maintainers.txt: Added maintainers and reviewers for the DurianPkg. The public git repository is : https://github.com/jialing2020/edk2-platforms/tree/phytium_opensource_for_FT2000-4_v3 v3: Optimized the codes to meet the specification. In the process of submitting V3 version, the master branch is ahead of the current branch. So, there was a lot of submission from someone else. In this case, what should we to do? *** BLURB HERE *** Heng Luo (2): Fix wrong information of TigerLake in Readme.md Fix wrong information of TigerLake in Readme.md Jeremy Linton (2): Platform/RaspberryPi/Acpitables: Correct duplicate _UIDs Platform/RaspberryPi/Acpitables: Correct duplicate _UIDs Leif Lindholm (2): Silicon/Qemu: Move SbsaQemu MPIDR-retrieval function to FdtHelperLib Silicon/Qemu: Move SbsaQemu MPIDR-retrieval function to FdtHelperLib Ling Jia (20): Silicon/Phytium: Added PlatformLib to FT2000/4 Silicon/Phytium: Added Acpi support to FT2000/4 Silicon/Phytium: Added SMBIOS support to FT2000/4 Silicon/Phytium: Added PciSegmentLib to FT2000/4 Silicon/Phytium: Added PciHostBridgeLib to FT2000/4 Silicon/Phytium: Added Spi driver support to FT2000/4 Silicon/Phytium: Added flash driver support to Phytium Silicon Silicon/Phytium: Added fvb driver for norflash Silicon/Phytium: Added Rtc driver to FT2000/4 Maintainers.txt: Added maintainers and reviewers for the DurianPkg Silicon/Phytium: Added PlatformLib to FT2000/4 Silicon/Phytium: Added Acpi support to FT2000/4 Silicon/Phytium: Added SMBIOS support to FT2000/4 Silicon/Phytium: Added PciSegmentLib to FT2000/4 Silicon/Phytium: Added PciHostBridgeLib to FT2000/4 Silicon/Phytium: Added Spi driver support to FT2000/4 Silicon/Phytium: Added flash driver support to Phytium Silicon Silicon/Phytium: Added fvb driver for norflash Silicon/Phytium: Added Rtc driver to FT2000/4 Maintainers.txt: Added maintainers and reviewers for the DurianPkg Liu, Zhiguang (2): Intel/BoardModulePkg: sort load option in the first boot Intel/BoardModulePkg: sort load option in the first boot Marcin Juszkiewicz (2): drop Tanmay Jagdale from sbsa-ref maintainers drop Tanmay Jagdale from sbsa-ref maintainers Rebecca Cran (8): SbsaQemu: Add FdtHelperLib SbsaQemu: Update SbsaQemuAcpiDxe to use FdtHelperLib Platform/Qemu/SbsaQemu: Add SMBIOS tables Silicon/Qemu: Don't re-use NumCores as loop index in AddMadtTable SbsaQemu: Add FdtHelperLib SbsaQemu: Update SbsaQemuAcpiDxe to use FdtHelperLib Platform/Qemu/SbsaQemu: Add SMBIOS tables Silicon/Qemu: Don't re-use NumCores as loop index in AddMadtTable Takuto Naito (8): TigerlakeOpenBoardPkg: Fix build errors with GCC5 TigerlakeSiliconPkg/IpBlock: Fix build errors with GCC5 TigerlakeSiliconPkg: Fix build error with GCC5 TigerlakeOpenBoardPkg: Fix build error with GCC5 TigerlakeOpenBoardPkg: Fix build errors with GCC5 TigerlakeSiliconPkg/IpBlock: Fix build errors with GCC5 TigerlakeSiliconPkg: Fix build error with GCC5 TigerlakeOpenBoardPkg: Fix build error with GCC5 Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec | 52 + Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 17 + Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dsc.inc | 345 +++++ Platform/Phytium/DurianPkg/DurianPkg.dsc | 331 +++++ Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 50 +- Platform/Phytium/DurianPkg/DurianPkg.fdf | 235 ++++ Platform/Qemu/SbsaQemu/SbsaQemu.fdf | 7 + Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf | 2 +- Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf | 53 + Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiTables.inf | 56 + Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf | 47 + Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf | 44 + Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf | 48 + Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf | 47 + Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.inf | 28 + Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLib.inf | 55 + Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib.inf | 39 + Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf | 53 + Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.inf | 61 + Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 3 +- Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.inf | 33 + Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.h | 64 + Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.h | 99 ++ Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib.h | 24 + Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.h | 104 ++ Silicon/Phytium/PhytiumCommonPkg/Include/Platform.h | 80 ++ Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiNorFlashProtocol.h | 74 + Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiProtocol.h | 51 + Silicon/Phytium/PhytiumCommonPkg/Include/SystemServiceInterface.h | 112 ++ Silicon/Qemu/SbsaQemu/Include/Library/FdtHelperLib.h | 36 + Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.c | 72 +- Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c | 196 --- Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c | 2 +- Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/PeiTigerlakeURvpInitPreMemLib.c | 2 + Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c | 241 ++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/DxePchPcieRpPolicyLib/DxePchPcieRpPolicyLib.c | 2 +- Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/PcieClientRpLib/PcieClientRpLib.c | 2 - Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitLib.c | 5 - Silicon/Intel/TigerlakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmiHelperClient.c | 2 - Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c | 943 +++++++++++++ Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.c | 198 +++ Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.c | 424 ++++++ Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.c | 181 +++ Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.c | 1434 ++++++++++++++++++++ Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLib.c | 137 ++ Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLibMem.c | 156 +++ Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib.c | 462 +++++++ Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatform.c | 250 ++++ Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.c | 1304 ++++++++++++++++++ Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 95 +- Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.c | 98 ++ Maintainers.txt | 9 +- Platform/Intel/Readme.md | 2 +- Platform/RaspberryPi/AcpiTables/Emmc.asl | 2 +- Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiSsdtRootPci.asl | 209 +++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dbg2.aslc | 80 ++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Cpu.asl | 85 ++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Dsdt.asl | 15 + Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Uart.asl | 65 + Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Fadt.aslc | 77 ++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Gtdt.aslc | 83 ++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Iort.aslc | 89 ++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Madt.aslc | 67 + Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Mcfg.aslc | 65 + Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Pptt.aslc | 219 +++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Spcr.aslc | 73 + Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/AArch64/PhytiumPlatformHelper.S | 76 ++ Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.fdf.inc | 119 ++ 68 files changed, 9456 insertions(+), 335 deletions(-) create mode 100644 Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec create mode 100644 Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dsc.inc create mode 100644 Platform/Phytium/DurianPkg/DurianPkg.dsc create mode 100644 Platform/Phytium/DurianPkg/DurianPkg.fdf create mode 100644 Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiTables.inf create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.inf create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLib.inf create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib.inf create mode 100644 Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf create mode 100644 Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.inf create mode 100644 Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.inf create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.h create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.h create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib.h create mode 100644 Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.h create mode 100644 Silicon/Phytium/PhytiumCommonPkg/Include/Platform.h create mode 100644 Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiNorFlashProtocol.h create mode 100644 Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiProtocol.h create mode 100644 Silicon/Phytium/PhytiumCommonPkg/Include/SystemServiceInterface.h create mode 100644 Silicon/Qemu/SbsaQemu/Include/Library/FdtHelperLib.h create mode 100644 Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.c create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.c create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.c create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.c create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLib.c create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLibMem.c create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib.c create mode 100644 Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatform.c create mode 100644 Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.c create mode 100644 Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.c create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiSsdtRootPci.asl create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dbg2.aslc create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Cpu.asl create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Dsdt.asl create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Uart.asl create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Fadt.aslc create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Gtdt.aslc create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Iort.aslc create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Madt.aslc create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Mcfg.aslc create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Pptt.aslc create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Spcr.aslc create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/AArch64/PhytiumPlatformHelper.S create mode 100644 Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.fdf.inc -- 2.25.1 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v3 14/46] Silicon/Phytium: Added Acpi support to FT2000/4 2021-03-12 11:01 [PATCH v3 00/46] Added support for FT2000/4 chip Ling Jia @ 2021-03-12 11:01 ` Ling Jia 0 siblings, 0 replies; 6+ messages in thread From: Ling Jia @ 2021-03-12 11:01 UTC (permalink / raw) To: devel; +Cc: Leif Lindholm, Peng Xie, Yiqi Shu, Ling Jia Added Acpi driver and table to FT2000/4, the ACPI Tables providing library AcpiTables.inf uses a lot of information that is available in the form of PCDs for differnt platforms. v3: Optimize code to conform to specifications. Signed-off-by: Ling Jia <jialing@phytium.com.cn> Reviewed-by: Leif Lindholm <leif@nuviainc.com> --- Platform/Phytium/DurianPkg/DurianPkg.dsc | 6 + Platform/Phytium/DurianPkg/DurianPkg.fdf | 7 + Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiTables.inf | 56 +++++ Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf | 53 +++++ Silicon/Phytium/PhytiumCommonPkg/Include/Platform.h | 80 +++++++ Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatform.c | 250 ++++++++++++++++++++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiSsdtRootPci.asl | 209 ++++++++++++++++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dbg2.aslc | 80 +++++++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Cpu.asl | 85 +++++++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Dsdt.asl | 15 ++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Uart.asl | 65 +++++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Fadt.aslc | 77 ++++++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Gtdt.aslc | 83 +++++++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Iort.aslc | 89 +++++++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Madt.aslc | 67 ++++++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Mcfg.aslc | 65 +++++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Pptt.aslc | 219 +++++++++++++++++ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Spcr.aslc | 73 ++++++ 18 files changed, 1579 insertions(+) diff --git a/Platform/Phytium/DurianPkg/DurianPkg.dsc b/Platform/Phytium/DurianPkg/DurianPkg.dsc index b523ecd6584b..6f38acb6361c 100644 --- a/Platform/Phytium/DurianPkg/DurianPkg.dsc +++ b/Platform/Phytium/DurianPkg/DurianPkg.dsc @@ -279,6 +279,12 @@ [Components.common] # MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + # + # ACPI Support + # + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiTables.inf + Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf # # Bds diff --git a/Platform/Phytium/DurianPkg/DurianPkg.fdf b/Platform/Phytium/DurianPkg/DurianPkg.fdf index 9d75b072c6dc..f435f7cb51c2 100644 --- a/Platform/Phytium/DurianPkg/DurianPkg.fdf +++ b/Platform/Phytium/DurianPkg/DurianPkg.fdf @@ -111,6 +111,13 @@ [FV.FvMain] INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + # + # ACPI Support + # + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + INF RuleOverride=ACPITABLE Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiTables.inf + INF Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf + # # Multiple Console IO support # diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiTables.inf b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiTables.inf new file mode 100644 index 000000000000..e3fd86f19733 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiTables.inf @@ -0,0 +1,56 @@ +#/** @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001b + BASE_NAME = AcpiTables + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + +[Sources] + AcpiSsdtRootPci.asl + Dsdt/Dsdt.asl + Fadt.aslc + Iort.aslc + Gtdt.aslc + Madt.aslc + Mcfg.aslc + Pptt.aslc + Spcr.aslc + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec + +[FixedPcd] + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase + + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate + gArmPlatformTokenSpaceGuid.PL011UartClkInHz + gArmPlatformTokenSpaceGuid.PL011UartInterrupt + + gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase + gArmPlatformTokenSpaceGuid.PcdWatchdogCount diff --git a/Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf b/Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf new file mode 100644 index 000000000000..0f6d46fdba91 --- /dev/null +++ b/Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf @@ -0,0 +1,53 @@ +#/** @file +# Sample ACPI Platform Driver. +# +# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001b + BASE_NAME = AcpiPlatform + FILE_GUID = d51068e8-40dc-11eb-9322-1f6d234e9e6e + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = AcpiPlatformEntryPoint + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[Sources] + AcpiPlatform.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec + +[LibraryClasses] + BaseMemoryLib + DebugLib + DxeServicesLib + UefiLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[Guids] + +[Protocols] + gEfiAcpiTableProtocolGuid ## CONSUMES + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile ## CONSUMES + +[FixedPcd] + gArmTokenSpaceGuid.PcdGicRedistributorsBase + +[Depex] + gEfiAcpiTableProtocolGuid diff --git a/Silicon/Phytium/PhytiumCommonPkg/Include/Platform.h b/Silicon/Phytium/PhytiumCommonPkg/Include/Platform.h new file mode 100644 index 000000000000..d5e3907e377a --- /dev/null +++ b/Silicon/Phytium/PhytiumCommonPkg/Include/Platform.h @@ -0,0 +1,80 @@ +/** @file + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef PHYTIUM_H_ +#define PHYTIUM_H_ + +#include <IndustryStandard/Acpi.h> + +#define EFI_ACPI_6_1_GIC_ITS_INIT(GicITSHwId, GicITSBase) \ + { \ + EFI_ACPI_6_1_GIC_ITS, sizeof (EFI_ACPI_6_1_GIC_ITS_STRUCTURE), EFI_ACPI_RESERVED_WORD, \ + GicITSHwId, GicITSBase, EFI_ACPI_RESERVED_DWORD \ + } + +#define EFI_ACPI_5_1_GICR_STRUCTURE_INIT( \ + GicRBase, GicRlength) \ + { \ + EFI_ACPI_5_1_GICR, sizeof (EFI_ACPI_5_1_GICR_STRUCTURE), EFI_ACPI_RESERVED_WORD, \ + GicRBase, GicRlength \ + } + +#define EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT( \ + ProximityDomain, ACPIProcessorUID, Flags, ClockDomain) \ + { \ + 3, sizeof (EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE),ProximityDomain , \ + ACPIProcessorUID, Flags, ClockDomain \ + } + +#define EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT( \ + ProximityDomain, AddressBaseLow, AddressBaseHigh, LengthLow, LengthHigh, Flags) \ + { \ + 1, sizeof (EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE),ProximityDomain , EFI_ACPI_RESERVED_WORD, \ + AddressBaseLow, AddressBaseHigh, LengthLow, LengthHigh, EFI_ACPI_RESERVED_DWORD, Flags, \ + EFI_ACPI_RESERVED_QWORD \ + } + +#define EFI_ACPI_6_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags, PmuIrq, \ + GicBase, GicVBase, GicHBase, GsivId, GicRBase, ProcessorPowerEfficiencyClass) \ + { \ + EFI_ACPI_6_1_GIC, sizeof (EFI_ACPI_6_1_GIC_STRUCTURE), EFI_ACPI_RESERVED_WORD, \ + GicId, AcpiCpuUid, Flags, 0, PmuIrq, 0, GicBase, GicVBase, GicHBase, \ + GsivId, GicRBase, Mpidr, ProcessorPowerEfficiencyClass, {0, 0, 0} \ + } + +#define EFI_ACPI_6_1_GIC_DISTRIBUTOR_INIT(GicDistHwId, GicDistBase, GicDistVector, GicVersion) \ + { \ + EFI_ACPI_6_1_GICD, sizeof (EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE), EFI_ACPI_RESERVED_WORD, \ + GicDistHwId, GicDistBase, GicDistVector, GicVersion, \ + {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE} \ + } + +// +// ACPI table information used to initialize tables. +// +#define EFI_ACPI_PHYTIUM_OEM_ID 'F','T','-','L','T','D' // OEMID 6 bytes long +#define EFI_ACPI_PHYTIUM_OEM_TABLE_ID SIGNATURE_64('P','H','Y','T','I','U','M',' ') // OEM table id 8 bytes long +#define EFI_ACPI_PHYTIUM_OEM_REVISION 0x20201111 +#define EFI_ACPI_PHYTIUM_CREATOR_ID SIGNATURE_32('P','H','Y','T') +#define EFI_ACPI_PHYTIUM_CREATOR_REVISION 0x20201111 + +// A macro to initialise the common header part of EFI ACPI tables as defined by +// EFI_ACPI_DESCRIPTION_HEADER structure. +#define PHYTIUM_ACPI_HEADER(Signature, Type, Revision) { \ + Signature, /* UINT32 Signature */ \ + sizeof (Type), /* UINT32 Length */ \ + Revision, /* UINT8 Revision */ \ + 0, /* UINT8 Checksum */ \ + { EFI_ACPI_PHYTIUM_OEM_ID }, /* UINT8 OemId[6] */ \ + EFI_ACPI_PHYTIUM_OEM_TABLE_ID, /* UINT64 OemTableId */ \ + EFI_ACPI_PHYTIUM_OEM_REVISION, /* UINT32 OemRevision */ \ + EFI_ACPI_PHYTIUM_CREATOR_ID, /* UINT32 CreatorId */ \ + EFI_ACPI_PHYTIUM_CREATOR_REVISION /* UINT32 CreatorRevision */ \ + } + +#endif diff --git a/Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatform.c b/Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatform.c new file mode 100644 index 000000000000..c48ed74f5386 --- /dev/null +++ b/Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatform.c @@ -0,0 +1,250 @@ +/** @file + Sample ACPI Platform Driver. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <IndustryStandard/Acpi.h> +#include <Library/BaseLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/DebugLib.h> +#include <Library/UefiLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <PiDxe.h> +#include <Protocol/AcpiTable.h> +#include <Protocol/FirmwareVolume2.h> + +/** + Locate the first instance of a protocol. If the protocol requested is an + FV protocol, then it will return the first FV that contains the ACPI table + storage file. + + @param[out] Instance Return pointer to the first instance of the protocol. + + @return EFI_SUCCESS The function completed successfully. + + @return EFI_NOT_FOUND The protocol could not be located. + + @return EFI_OUT_OF_RESOURCES There are not enough resources to find the protocol. + +**/ +EFI_STATUS +LocateFvInstanceWithTables ( + OUT EFI_FIRMWARE_VOLUME2_PROTOCOL **Instance + ) +{ + EFI_STATUS Status; + EFI_HANDLE *HandleBuffer; + UINTN NumberOfHandles; + EFI_FV_FILETYPE FileType; + UINT32 FvStatus; + EFI_FV_FILE_ATTRIBUTES Attributes; + UINTN Size; + UINTN Index; + EFI_FIRMWARE_VOLUME2_PROTOCOL *FvInstance; + + FvStatus = 0; + + // + // Locate protocol. + // + Status = gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiFirmwareVolume2ProtocolGuid, + NULL, + &NumberOfHandles, + &HandleBuffer + ); + if (EFI_ERROR (Status)) { + // + // Defined errors at this time are not found and out of resources. + // + return Status; + } + + // + // Looking for FV with ACPI storage file + // + + for (Index = 0; Index < NumberOfHandles; Index++) { + // + // Get the protocol on this handle + // This should not fail because of LocateHandleBuffer + // + Status = gBS->HandleProtocol ( + HandleBuffer[Index], + &gEfiFirmwareVolume2ProtocolGuid, + (VOID **)&FvInstance + ); + ASSERT_EFI_ERROR (Status); + + // + // See if it has the ACPI storage file + // + Status = FvInstance->ReadFile ( + FvInstance, + (EFI_GUID *)PcdGetPtr (PcdAcpiTableStorageFile), + NULL, + &Size, + &FileType, + &Attributes, + &FvStatus + ); + + // + // If we found it, then we are done + // + if (Status == EFI_SUCCESS) { + *Instance = FvInstance; + break; + } + } + + // + // Free any allocated buffers + // + gBS->FreePool (HandleBuffer); + + return Status; +} + + +/** + This function calculates and updates an UINT8 checksum. + + @param[in] Buffer Pointer to buffer to checksum. + + @param[in] Size Number of bytes to checksum. + +**/ +VOID +AcpiPlatformChecksum ( + IN UINT8 *Buffer, + IN UINTN Size + ) +{ + UINTN ChecksumOffset; + + ChecksumOffset = OFFSET_OF (EFI_ACPI_DESCRIPTION_HEADER, Checksum); + + // + // Set checksum to 0 first + // + Buffer[ChecksumOffset] = 0; + + // + // Update checksum value + // + Buffer[ChecksumOffset] = CalculateCheckSum8 (Buffer, Size); +} + + +/** + This function is the entrypoint of the acpi platform. + + @param[in] ImageHandle The firmware allocated handle for the EFI image. + + @param[in] SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + + @retval other Some error occurs when executing this entry point. + +**/ +EFI_STATUS +EFIAPI +AcpiPlatformEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_ACPI_TABLE_PROTOCOL *AcpiTable; + EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol; + INTN Instance; + EFI_ACPI_COMMON_HEADER *CurrentTable; + UINTN TableHandle; + UINT32 FvStatus; + UINTN TableSize; + UINTN Size; + + Instance = 0; + CurrentTable = NULL; + TableHandle = 0; + + // + // Find the AcpiTable protocol + // + Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID **)&AcpiTable); + if (EFI_ERROR (Status)) { + return EFI_ABORTED; + } + + // + // Locate the firmware volume protocol + // + Status = LocateFvInstanceWithTables (&FwVol); + if (EFI_ERROR (Status)) { + return EFI_ABORTED; + } + // + // Read tables from the storage file. + // + while (Status == EFI_SUCCESS) { + + Status = FwVol->ReadSection ( + FwVol, + (EFI_GUID *)PcdGetPtr (PcdAcpiTableStorageFile), + EFI_SECTION_RAW, + Instance, + (VOID **)&CurrentTable, + &Size, + &FvStatus + ); + if ( ! EFI_ERROR (Status)) { + // + // Add the table + // + TableHandle = 0; + + TableSize = ((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable)->Length; + ASSERT (Size >= TableSize); + + // + // Checksum ACPI table + // + AcpiPlatformChecksum ((UINT8 *)CurrentTable, TableSize); + + // + // Install ACPI table + // + Status = AcpiTable->InstallAcpiTable ( + AcpiTable, + CurrentTable, + TableSize, + &TableHandle + ); + + // + // Free memory allocated by ReadSection + // + gBS->FreePool (CurrentTable); + + if (EFI_ERROR (Status)) { + return EFI_ABORTED; + } + + // + // Increment the instance + // + Instance++; + CurrentTable = NULL; + } + } + + return EFI_SUCCESS; +} + diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiSsdtRootPci.asl b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiSsdtRootPci.asl new file mode 100644 index 000000000000..667f8cc8fb65 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiSsdtRootPci.asl @@ -0,0 +1,209 @@ +/** @file + Phytium ACPI ASL Sources. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <Platform.h> + +#define LNK_DEVICE(Unique_Id, Link_Name, irq) \ + Device (Link_Name) { \ + Name (_HID, EISAID ("PNP0C0F")) \ + Name (_UID, Unique_Id) \ + Name (_PRS, ResourceTemplate () { \ + Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive) { irq } \ + }) \ + Method (_CRS, 0) { Return (_PRS) } \ + Method (_SRS, 1) { } \ + Method (_DIS) { } \ + } + +#define PRT_ENTRY(Address, Pin, Link) \ + Package (4) { \ + Address, \ + Pin, \ + Link, \ + Zero \ + } + +#define ROOT_PRT_ENTRY(Dev, Pin, Link) PRT_ENTRY(Dev * 0x10000 + 0xFFFF, Pin, Link) + + +DefinitionBlock ("SsdtPci.aml", "SSDT", 2, "FT-LTD", "PHYTIUM ", EFI_ACPI_PHYTIUM_OEM_REVISION) { + Scope (_SB) { + // + // PCI Root Complex + // + LNK_DEVICE (1, LNKA, 60) + LNK_DEVICE (2, LNKB, 61) + LNK_DEVICE (3, LNKC, 62) + LNK_DEVICE (4, LNKD, 63) + + // reserve ECAM memory range + Device (RES0) + { + Name (_HID, EISAID ("PNP0C02")) + Name (_UID, 0) + Name (_CRS, ResourceTemplate () { + QWordMemory (ResourceConsumer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0, // Granularity + 0x40000000, // Range Minimum + 0x4FFFFFFF, // Range Maximum + 0, // Translation Offset + 0x10000000, // Length + ,,) + }) + } + + Device (PCI0) + { + Name (_HID, EISAID ("PNP0A08")) // PCI Express Root Bridge + Name (_CID, EISAID ("PNP0A03")) // Compatible PCI Root Bridge + Name (_SEG, Zero) // PCI Segment Group number + Name (_BBN, 0) // PCI Base Bus Number + Name (_CCA, 1) + + // Root Complex + Device (RP0) { + Name (_ADR, 0x00000000) // Dev 0, Func 0 + } + // PCI Routing Table + Name (_PRT, Package () { + ROOT_PRT_ENTRY (0, 0, LNKA), // INTA + ROOT_PRT_ENTRY (0, 1, LNKB), // INTB + ROOT_PRT_ENTRY (0, 2, LNKC), // INTC + ROOT_PRT_ENTRY (0, 3, LNKD), // INTD + + ROOT_PRT_ENTRY (1, 0, LNKA), // INTA + ROOT_PRT_ENTRY (1, 1, LNKB), // INTB + ROOT_PRT_ENTRY (1, 2, LNKC), // INTC + ROOT_PRT_ENTRY (1, 3, LNKD), // INTD + + ROOT_PRT_ENTRY (2, 0, LNKA), // INTA + ROOT_PRT_ENTRY (2, 1, LNKB), // INTB + ROOT_PRT_ENTRY (2, 2, LNKC), // INTC + ROOT_PRT_ENTRY (2, 3, LNKD), // INTD + + ROOT_PRT_ENTRY (3, 0, LNKA), // INTA + ROOT_PRT_ENTRY (3, 1, LNKB), // INTB + ROOT_PRT_ENTRY (3, 2, LNKC), // INTC + ROOT_PRT_ENTRY (3, 3, LNKD), // INTD + + ROOT_PRT_ENTRY (4, 0, LNKA), // INTA + ROOT_PRT_ENTRY (4, 1, LNKB), // INTB + ROOT_PRT_ENTRY (4, 2, LNKC), // INTC + ROOT_PRT_ENTRY (4, 3, LNKD), // INTD + + ROOT_PRT_ENTRY (5, 0, LNKA), // INTA + ROOT_PRT_ENTRY (5, 1, LNKB), // INTB + ROOT_PRT_ENTRY (5, 2, LNKC), // INTC + ROOT_PRT_ENTRY (5, 3, LNKD), // INTD + }) + + // Root complex resources + Method (_CRS, 0, Serialized) { + Name (RBUF, ResourceTemplate () { + WordBusNumber ( + ResourceProducer, + MinFixed, MaxFixed, PosDecode, + 0, // AddressGranularity + 0, // AddressMinimum - Minimum Bus Number + 255, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 256 // RangeLength - Number of Busses + ) + + DWordMemory ( // 32-bit BAR Windows + ResourceProducer, PosDecode, + MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x58000000, // Min Base Address + 0x7FFFFFFF, // Max Base Address + 0x00000000, // Translate + 0x28000000 // Length + ) + + QWordMemory ( // 64-bit BAR Windows + ResourceProducer, PosDecode, + MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x1000000000, // Min Base Address + 0x1FFFFFFFFF, // Max Base Address + 0x0000000000, // Translate + 0x1000000000 // Length + ) + + DWordIo ( // IO window + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x00000000, // Granularity + 0x00000000, // Min Base Address + 0x00efffff, // Max Base Address + 0x50000000, // Translate + 0x00f00000, // Length + ,,, TypeTranslation + ) + }) // Name(RBUF) + + Return (RBUF) + } // Method(_CRS) + + // + // OS Control Handoff + // + Name (SUPP, Zero) // PCI _OSC Support Field value + Name (CTRL, Zero) // PCI _OSC Control Field value + + /* + See [1] 6.2.10, [2] 4.5 + */ + Method (_OSC, 4) { + // Check for proper UUID + If (LEqual (Arg0, ToUUID ("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + // Create DWord-adressable fields from the Capabilities Buffer + CreateDWordField (Arg3, 0, CDW1) + CreateDWordField (Arg3, 4, CDW2) + CreateDWordField (Arg3, 8, CDW3) + + // Save Capabilities DWord2 & 3 + Store (CDW2, SUPP) + Store (CDW3, CTRL) + + // Only allow native hot plug control if OS supports: + // * ASPM + // * Clock PM + // * MSI/MSI-X + If (LNotEqual (And (SUPP, 0x16), 0x16)) { + And (CTRL, 0x1E, CTRL) // Mask bit 0 (and undefined bits) + } + + // Do not allow native PME, AER (no dependencies) + // Never allow SHPC (no SHPC controller in this system) + And (CTRL, 0x10, CTRL) + + If (LNotEqual (Arg1, One)) { // Unknown revision + Or (CDW1, 0x08, CDW1) + } + + If (LNotEqual (CDW3, CTRL)) { // Capabilities bits were masked + Or (CDW1, 0x10, CDW1) + } + // Update DWORD3 in the buffer + Store (CTRL, CDW3) + Return (Arg3) + } Else { + Or (CDW1, 4, CDW1) // Unrecognized UUID + Return (Arg3) + } + } + } + } +} diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dbg2.aslc b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dbg2.aslc new file mode 100644 index 000000000000..5349f6364b3d --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dbg2.aslc @@ -0,0 +1,80 @@ +/** @file + Phytium ACPI ASL Sources. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <IndustryStandard/Acpi.h> +#include <IndustryStandard/DebugPort2Table.h> +#include <Library/AcpiLib.h> +#include <Library/ArmLib.h> +#include <Library/PcdLib.h> +#include <Platform.h> + +#define NUMBER_DEBUG_DEVICE_INFO 1 +#define NUMBER_OF_GENERIC_ADDRESS 1 +#define NAMESPACE_STRING_SIZE 8 + +#pragma pack(1) + +typedef struct { + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT DdiHeader; + EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE Address[NUMBER_OF_GENERIC_ADDRESS]; + UINT32 AddressSize[NUMBER_OF_GENERIC_ADDRESS]; + CHAR8 NamespaceString[NAMESPACE_STRING_SIZE]; +} EFI_ACPI_DBG2_DDI_STRUCT; + +typedef struct { + EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Desc; + EFI_ACPI_DBG2_DDI_STRUCT Ddi[NUMBER_DEBUG_DEVICE_INFO]; +} EFI_ACPI_DEBUG_PORT_2_TABLE; + +#pragma pack() + +EFI_ACPI_DEBUG_PORT_2_TABLE Dbg2 = { + { + PHYTIUM_ACPI_HEADER ( + EFI_ACPI_6_1_DEBUG_PORT_2_TABLE_SIGNATURE, + EFI_ACPI_DEBUG_PORT_2_TABLE, + EFI_ACPI_DEBUG_PORT_2_TABLE_REVISION + ), + OFFSET_OF (EFI_ACPI_DEBUG_PORT_2_TABLE, Ddi), + NUMBER_DEBUG_DEVICE_INFO + }, + { + { + { + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION, + sizeof (EFI_ACPI_DBG2_DDI_STRUCT), + NUMBER_OF_GENERIC_ADDRESS, + NAMESPACE_STRING_SIZE, + OFFSET_OF (EFI_ACPI_DBG2_DDI_STRUCT, NamespaceString), + 0, + 0, + EFI_ACPI_DBG2_PORT_TYPE_SERIAL, + EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_PL011_UART, + {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}, + OFFSET_OF (EFI_ACPI_DBG2_DDI_STRUCT, Address), + OFFSET_OF (EFI_ACPI_DBG2_DDI_STRUCT, AddressSize), + }, + { + { + EFI_ACPI_6_1_SYSTEM_MEMORY, + 32, + 0, + EFI_ACPI_6_1_DWORD, + FixedPcdGet64 (PcdSerialRegisterBase) + } + }, + { + 0x1000 + }, + "COM0" + } + } +}; + +VOID * CONST ReferenceAcpiTable = &Dbg2; diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Cpu.asl b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Cpu.asl new file mode 100644 index 000000000000..219a129fa540 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Cpu.asl @@ -0,0 +1,85 @@ +/** @file + Phytium ACPI ASL Sources. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Scope (_SB) +{ + Device (CLU0) { + Name (_HID, "ACPI0010") + Name (_UID, 0) + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + Device (CPU0) { + Name (_HID, "ACPI0007") + Name (_UID, 0) + Name (_DSD, Package () { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"clock-name", "c0"}, + Package () {"clock-domain", 0}, + } + }) + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + } + + Device (CPU1) { + Name (_HID, "ACPI0007") + Name (_UID, 1) + Name (_DSD, Package () { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"clock-name", "c0"}, + Package () {"clock-domain", 0}, + } + }) + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + } + } + + Device (CLU1) { + Name (_HID, "ACPI0010") + Name (_UID, 1) + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + Device (CPU2) { + Name (_HID, "ACPI0007") + Name (_UID, 2) + Name (_DSD, Package () { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"clock-name", "c1"}, + Package () {"clock-domain", 1}, + } + }) + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + } + + Device (CPU3) { + Name (_HID, "ACPI0007") + Name (_UID, 3) + Name (_DSD, Package () { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"clock-name", "c1"}, + Package () {"clock-domain", 1}, + } + }) + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + } + } +} diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Dsdt.asl b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Dsdt.asl new file mode 100644 index 000000000000..b21431ca36dc --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Dsdt.asl @@ -0,0 +1,15 @@ +/** @file + Phytium ACPI ASL Sources. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <Platform.h> + +DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "FT-LTD", "PHYTIUM ", EFI_ACPI_PHYTIUM_OEM_REVISION) { + include ("Cpu.asl") + include ("Uart.asl") +} diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Uart.asl b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Uart.asl new file mode 100644 index 000000000000..25752036b550 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Uart.asl @@ -0,0 +1,65 @@ +/** @file + Phytium ACPI ASL Sources. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +Scope (_SB) +{ + //UART 0 + Device (UAR0) { + Name (_HID, "ARMH0011") + Name (_UID, 0) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0x28000000, 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 38 } + }) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + } + + //UART 1 + Device (UAR1) { + Name (_HID, "ARMH0011") + Name (_UID, 1) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0x28001000, 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {39} + }) + + Method (_STA, 0, NotSerialized) { Return (0x0F) } + } + + //UART 2 + Device (UAR2) { + Name (_HID, "ARMH0011") + Name (_UID, 2) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0x28002000, 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {40} + }) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + } + + //UART 3 + Device (UAR3) { + Name (_HID, "ARMH0011") + Name (_UID, 3) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0x28003000, 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {41} + }) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + } +} diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Fadt.aslc b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Fadt.aslc new file mode 100644 index 000000000000..10612c136876 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Fadt.aslc @@ -0,0 +1,77 @@ +/** @file + Phytium ACPI ASL Sources. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <IndustryStandard/Acpi.h> +#include <Library/AcpiLib.h> +#include <Platform.h> + +EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = { + PHYTIUM_ACPI_HEADER ( + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE, + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION + ), + 0, // UINT32 FirmwareCtrl + 0, // UINT32 Dsdt + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0 + EFI_ACPI_6_1_PM_PROFILE_ENTERPRISE_SERVER, // UINT8 PreferredPmProfile + 0, // UINT16 SciInt + 0, // UINT32 SmiCmd + 0, // UINT8 AcpiEnable + 0, // UINT8 AcpiDisable + 0, // UINT8 S4BiosReq + 0, // UINT8 PstateCnt + 0, // UINT32 Pm1aEvtBlk + 0, // UINT32 Pm1bEvtBlk + 0, // UINT32 Pm1aCntBlk + 0, // UINT32 Pm1bCntBlk + 0, // UINT32 Pm2CntBlk + 0, // UINT32 PmTmrBlk + 0, // UINT32 Gpe0Blk + 0, // UINT32 Gpe1Blk + 0, // UINT8 Pm1EvtLen + 0, // UINT8 Pm1CntLen + 0, // UINT8 Pm2CntLen + 0, // UINT8 PmTmrLen + 0, // UINT8 Gpe0BlkLen + 0, // UINT8 Gpe1BlkLen + 0, // UINT8 Gpe1Base + 0, // UINT8 CstCnt + 0, // UINT16 PLvl2Lat + 0, // UINT16 PLvl3Lat + 0, // UINT16 FlushSize + 0, // UINT16 FlushStride + 0, // UINT8 DutyOffset + 0, // UINT8 DutyWidth + 0, // UINT8 DayAlrm + 0, // UINT8 MonAlrm + 0, // UINT8 Century + 0, // UINT16 IaPcBootArch + 0, // UINT8 Reserved1 + EFI_ACPI_6_1_HW_REDUCED_ACPI | EFI_ACPI_6_1_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE ResetReg + 0, // UINT8 ResetValue + EFI_ACPI_6_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision + 0, // UINT64 XFirmwareCtrl + 0, // UINT64 XDsdt + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPm2CntBlk + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPmTmrBlk + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XGpe0Blk + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XGpe1Blk + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE SleepControlReg + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE SleepStatusReg + 0 // UINT64 Hypervisor Vendor Identify +}; + +VOID * CONST ReferenceAcpiTable = &Fadt; diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Gtdt.aslc b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Gtdt.aslc new file mode 100644 index 000000000000..67468db2d4bd --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Gtdt.aslc @@ -0,0 +1,83 @@ +/** @file + Phytium ACPI ASL Sources. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <IndustryStandard/Acpi.h> +#include <Library/AcpiLib.h> +#include <Library/PcdLib.h> +#include <Platform.h> + +#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_6_1_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT +#define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0 +#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_6_1_GTDT_GLOBAL_FLAG_INTERRUPT_MODE +#define GTDT_GLOBAL_FLAGS_LEVEL 0 + +#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE +#define GTDT_TIMER_LEVEL_TRIGGERED 0 +#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY +#define GTDT_TIMER_ACTIVE_HIGH 0 +#define GTDT_TIMER_ALWAYS_ON_CAPABILITY EFI_ACPI_6_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY + +#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED \ + | EFI_ACPI_6_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY) + +#pragma pack (1) + +typedef struct { + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; + EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[2]; +} EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES; + +#pragma pack () + +EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { + { + PHYTIUM_ACPI_HEADER ( + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES, + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION + ), + 0xFFFFFFFFFFFFFFFF, // UINT64 PhysicalAddress + 0, // UINT32 Reserved + FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags + FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags + FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags + FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags + 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress + 2, + sizeof (EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE) + }, + + { + { + 1, //Type + 28, //Size of this structure + 0, //reserved + 0x2800a000, //RefreshFrame Physical Address + 0x2800b000, //WatchdogControlFrame Physical Address + 48, //Watchdog Timer GSIV + 0, //Watchdog Timer Flags high level + }, + + { + 1, + 28, + 0, + 0x28016000, + 0x28017000, + 49, + 0, + } + } +}; + +VOID * CONST ReferenceAcpiTable = &Gtdt; diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Iort.aslc b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Iort.aslc new file mode 100644 index 000000000000..4239499b68e5 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Iort.aslc @@ -0,0 +1,89 @@ +/** @file + Phytium ACPI ASL Sources. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <IndustryStandard/IoRemappingTable.h> +#include <Platform.h> + +#define FIELD_OFFSET(type, name) __builtin_offsetof(type, name) + +#pragma pack(1) +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE Node; + UINT32 Identifiers[1]; +} PHYTIUM_ITS_NODE; + +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_RC_NODE Node; + EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping; +} PHYTIUM_RC_NODE; + +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort; + PHYTIUM_ITS_NODE ItsNode; + PHYTIUM_RC_NODE RcNode[1]; +} PHYTIUM_IO_REMAPPING_STRUCTURE; + +#define __PHYTIUM_ID_MAPPING(In, Num, Out, Ref, Flags) \ + { \ + In, \ + Num, \ + Out, \ + FIELD_OFFSET (PHYTIUM_IO_REMAPPING_STRUCTURE, Ref), \ + Flags \ + } + +STATIC PHYTIUM_IO_REMAPPING_STRUCTURE Iort = { + { + PHYTIUM_ACPI_HEADER (EFI_ACPI_6_0_IO_REMAPPING_TABLE_SIGNATURE, + PHYTIUM_IO_REMAPPING_STRUCTURE, + EFI_ACPI_IO_REMAPPING_TABLE_REVISION), + 2, // NumNodes + sizeof (EFI_ACPI_6_0_IO_REMAPPING_TABLE), // NodeOffset + 0 // Reserved + }, { + // ItsNode + { + { + EFI_ACPI_IORT_TYPE_ITS_GROUP, // Type + sizeof (PHYTIUM_ITS_NODE), // Length + 0x0, // Revision + 0x0, // Reserved + 0x0, // NumIdMappings + 0x0, // IdReference + }, + 1, + }, { + 0x0 + }, + }, { + { + // PciRcNode + { + { + EFI_ACPI_IORT_TYPE_ROOT_COMPLEX, // Type + sizeof (PHYTIUM_RC_NODE), // Length + 0x0, // Revision + 0x0, // Reserved + 0x1, // NumIdMappings + FIELD_OFFSET (PHYTIUM_RC_NODE, RcIdMapping), // IdReference + }, + EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, // CacheCoherent + 0x0, // AllocationHints + 0x0, // Reserved + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM, // MemoryAccessFlags + EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED, // AtsAttribute + 0x0, // PciSegmentNumber + }, + __PHYTIUM_ID_MAPPING (0x0, 0xffff, 0x0, ItsNode, 0), + } + } +}; +#pragma pack() +# +VOID * CONST ReferenceAcpiTable = &Iort; diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Madt.aslc b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Madt.aslc new file mode 100644 index 000000000000..ef6d94837fa2 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Madt.aslc @@ -0,0 +1,67 @@ +/** @file + Phytium ACPI ASL Sources. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <IndustryStandard/Acpi.h> +#include <Library/AcpiLib.h> +#include <Library/ArmLib.h> +#include <Library/PcdLib.h> +#include <Platform.h> + + +#define PLATFORM_GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId)) + +#define EFI_GICC_STRUCTURE(AcpiCpuUid, Mpidr, GicRBaseOffset) \ + EFI_ACPI_6_1_GICC_STRUCTURE_INIT(0, AcpiCpuUid, Mpidr, EFI_ACPI_6_1_GIC_ENABLED, 23, \ + FixedPcdGet64(PcdGicInterruptInterfaceBase), FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, \ + FixedPcdGet64(PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicRedistributorsBase) + GicRBaseOffset, 0) +#define CORE_NUM 4 +// +// Multiple APIC Description Table +// +#pragma pack (1) + +typedef struct { + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_6_1_GIC_STRUCTURE GicInterfaces[CORE_NUM]; + EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; + EFI_ACPI_6_1_GIC_ITS_STRUCTURE GicITS[1]; +} EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE; + +#pragma pack () + +// +// Multiple APIC Description Table +// +EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { + { + PHYTIUM_ACPI_HEADER ( + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE, + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION + ), + // + // MADT specific fields + // + 0, // LocalApicAddress + 0, // Flags + }, + { + EFI_GICC_STRUCTURE (0x00, PLATFORM_GET_MPID (0x00, 0), 0x000000), + EFI_GICC_STRUCTURE (0x01, PLATFORM_GET_MPID (0x00, 1), 0x020000), + EFI_GICC_STRUCTURE (0x02, PLATFORM_GET_MPID (0x01, 0), 0x040000), + EFI_GICC_STRUCTURE (0x03, PLATFORM_GET_MPID (0x01, 1), 0x060000), + }, + + EFI_ACPI_6_1_GIC_DISTRIBUTOR_INIT (0, FixedPcdGet32 (PcdGicDistributorBase), 0, 0x3), + { + EFI_ACPI_6_1_GIC_ITS_INIT (0, FixedPcdGet64 (PcdGicDistributorBase) + 0x20000), + } +}; + +VOID * CONST ReferenceAcpiTable = &Madt; diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Mcfg.aslc b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Mcfg.aslc new file mode 100644 index 000000000000..34eebd6aeec9 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Mcfg.aslc @@ -0,0 +1,65 @@ +/** @file + Phytium ACPI ASL Sources. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <IndustryStandard/Acpi.h> +#include <Platform.h> + +#define ACPI_6_1_MCFG_VERSION 0x1 + +#pragma pack(1) +typedef struct +{ + UINT64 BaseAddress; + UINT16 SegGroupNum; + UINT8 StartBusNum; + UINT8 EndBusNum; + UINT32 Reserved2; +} EFI_ACPI_6_1_MCFG_CONFIG_STRUCTURE; + +typedef struct +{ + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT64 Reserved1; +} EFI_ACPI_6_1_MCFG_TABLE_CONFIG; + +typedef struct +{ + EFI_ACPI_6_1_MCFG_TABLE_CONFIG Acpi_Table_Mcfg; + EFI_ACPI_6_1_MCFG_CONFIG_STRUCTURE Config_Structure[1]; +} EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE; +#pragma pack() + +EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg= +{ + { + { + EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, + sizeof (EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE), + ACPI_6_1_MCFG_VERSION, + 0x00, // Checksum will be updated at runtime + {EFI_ACPI_PHYTIUM_OEM_ID}, + EFI_ACPI_PHYTIUM_OEM_TABLE_ID, + EFI_ACPI_PHYTIUM_OEM_REVISION, + EFI_ACPI_PHYTIUM_CREATOR_ID, + EFI_ACPI_PHYTIUM_CREATOR_REVISION + }, + 0x0000000000000000, //Reserved + }, + { + { + 0x40000000, //Base Address + 0, //Segment Group Number + 0, //Start Bus Number + 0xff, //End Bus Number + 0x00000000, //Reserved + }, + } +}; + +VOID * CONST ReferenceAcpiTable = &Mcfg; diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Pptt.aslc b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Pptt.aslc new file mode 100644 index 000000000000..ae1a21df23b9 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Pptt.aslc @@ -0,0 +1,219 @@ +/** @file + Phytium ACPI ASL Sources. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <IndustryStandard/Acpi.h> +#include <Platform.h> + +#define FIELD_OFFSET(type, name) __builtin_offsetof(type, name) + +#pragma pack(1) +typedef struct { + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Core; + UINT32 Offset[2]; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE DCache; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE ICache; +} PHYTIUM_PPTT_CORE; + +typedef struct { + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Cluster; + UINT32 Offset[1]; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L2Cache; + PHYTIUM_PPTT_CORE Cores[2]; +} PHYTIUM_PPTT_CLUSTER; + +typedef struct { + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Package; + UINT32 Offset[1]; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L3Cache; + PHYTIUM_PPTT_CLUSTER Clusters[2]; + EFI_ACPI_6_2_PPTT_STRUCTURE_ID ID; +} PHYTIUM_PPTT_PACKAGE; + +typedef struct { + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Pptt; + PHYTIUM_PPTT_PACKAGE Packages[1]; +} PHYTIUM_PPTT_TABLE; +#pragma pack() + +#define PPTT_CORE(pid, cid, id) { \ + { \ + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, \ + FIELD_OFFSET (PHYTIUM_PPTT_CORE, DCache), \ + {}, \ + { \ + 0, /* PhysicalPackage */ \ + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID, /* AcpiProcessorIdValid */ \ + }, \ + FIELD_OFFSET (PHYTIUM_PPTT_TABLE, \ + Packages[pid].Clusters[cid]), /* Parent */ \ + 8 * (pid) + 4 * (cid) + (id), /* AcpiProcessorId */ \ + 2, /* NumberOfPrivateResources */\ + }, { \ + FIELD_OFFSET (PHYTIUM_PPTT_TABLE, \ + Packages[pid].Clusters[cid].Cores[id].DCache), \ + FIELD_OFFSET (PHYTIUM_PPTT_TABLE, \ + Packages[pid].Clusters[cid].Cores[id].ICache), \ + }, { \ + EFI_ACPI_6_2_PPTT_TYPE_CACHE, \ + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \ + {}, \ + { \ + 1, /* SizePropertyValid */ \ + 1, /* NumberOfSetsValid */ \ + 1, /* AssociativityValid */ \ + 1, /* AllocationTypeValid */ \ + 1, /* CacheTypeValid */ \ + 1, /* WritePolicyValid */ \ + 1, /* LineSizeValid */ \ + }, \ + 0, /* NextLevelOfCache */ \ + SIZE_32KB, /* Size */ \ + 256, /* NumberOfSets */ \ + 2, /* Associativity */ \ + { \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \ + }, \ + 64 /* LineSize */ \ + }, { \ + EFI_ACPI_6_2_PPTT_TYPE_CACHE, \ + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \ + {}, \ + { \ + 1, /* SizePropertyValid */ \ + 1, /* NumberOfSetsValid */ \ + 1, /* AssociativityValid */ \ + 1, /* AllocationTypeValid */ \ + 1, /* CacheTypeValid */ \ + 0, /* WritePolicyValid */ \ + 1, /* LineSizeValid */ \ + }, \ + 0, /* NextLevelOfCache */ \ + SIZE_32KB, /* Size */ \ + 256, /* NumberOfSets */ \ + 2, /* Associativity */ \ + { \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ, /* AllocationType */ \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, \ + 0, /* WritePolicy */ \ + }, \ + 64 /* LineSize */ \ + } \ +} + +#define PPTT_CLUSTER(pid, cid) { \ + { \ + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, \ + FIELD_OFFSET (PHYTIUM_PPTT_CLUSTER, L2Cache), \ + {}, \ + { \ + 0, /* PhysicalPackage */ \ + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ \ + }, \ + FIELD_OFFSET (PHYTIUM_PPTT_TABLE, Packages[pid]), /* Parent */ \ + 0, /* AcpiProcessorId */ \ + 1, /* NumberOfPrivateResources */ \ + }, { \ + FIELD_OFFSET (PHYTIUM_PPTT_TABLE, Packages[pid].Clusters[cid].L2Cache), \ + }, { \ + EFI_ACPI_6_2_PPTT_TYPE_CACHE, \ + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \ + {}, \ + { \ + 1, /* SizePropertyValid */ \ + 1, /* NumberOfSetsValid */ \ + 1, /* AssociativityValid */ \ + 1, /* AllocationTypeValid */ \ + 1, /* CacheTypeValid */ \ + 1, /* WritePolicyValid */ \ + 1, /* LineSizeValid */ \ + }, \ + 0, /* NextLevelOfCache */ \ + SIZE_2MB, /* Size */ \ + 2048, /* NumberOfSets */ \ + 16, /* Associativity */ \ + { \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \ + }, \ + 64 /* LineSize */ \ + }, { \ + PPTT_CORE (pid, cid, 0), \ + PPTT_CORE (pid, cid, 1), \ + } \ +} + +#define PPTT_PANEL(pid) { \ + { \ + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, \ + FIELD_OFFSET (PHYTIUM_PPTT_PACKAGE, L3Cache), \ + {}, \ + { \ + 1, /* PhysicalPackage */ \ + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ \ + }, \ + 0, /* Parent */ \ + 0, /* AcpiProcessorId */ \ + 1, /* NumberOfPrivateResources */ \ + }, { \ + FIELD_OFFSET (PHYTIUM_PPTT_TABLE, Packages[pid].L3Cache), \ + }, { \ + EFI_ACPI_6_2_PPTT_TYPE_CACHE, \ + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \ + {}, \ + { \ + 1, /* SizePropertyValid */ \ + 1, /* NumberOfSetsValid */ \ + 1, /* AssociativityValid */ \ + 0, /* AllocationTypeValid */ \ + 1, /* CacheTypeValid */ \ + 1, /* WritePolicyValid */ \ + 1, /* LineSizeValid */ \ + }, \ + 0, /* NextLevelOfCache */ \ + SIZE_4MB, /* Size */ \ + 4096, /* NumberOfSets */ \ + 16, /* Associativity */ \ + { \ + 0, \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \ + }, \ + 64 /* LineSize */ \ + }, { \ + PPTT_CLUSTER (pid, 0), \ + PPTT_CLUSTER (pid, 1), \ + }, { \ + EFI_ACPI_6_2_PPTT_TYPE_ID, \ + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID), \ + {0}, \ + 0x54594850, \ + 0x3, \ + 0x1, \ + 0, \ + 0, \ + 0, \ + } \ +} + + +STATIC PHYTIUM_PPTT_TABLE mPhytiumPpttTable = { + { + PHYTIUM_ACPI_HEADER (EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + PHYTIUM_PPTT_TABLE, + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION), + }, + { + PPTT_PANEL (0) + } +}; + +VOID * CONST ReferenceAcpiTable = &mPhytiumPpttTable; diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Spcr.aslc b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Spcr.aslc new file mode 100644 index 000000000000..00ffb7e7a90d --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Spcr.aslc @@ -0,0 +1,73 @@ +/** @file + Phytium ACPI ASL Sources. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <IndustryStandard/Acpi.h> +#include <IndustryStandard/SerialPortConsoleRedirectionTable.h> +#include <Library/AcpiLib.h> +#include <Library/ArmLib.h> +#include <Library/PcdLib.h> +#include <Platform.h> + +/// +/// SPCR Flow Control +/// +#define SPCR_FLOW_CONTROL_NONE 0 + + +STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = { + PHYTIUM_ACPI_HEADER (EFI_ACPI_5_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION), + // UINT8 InterfaceType; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART, + // UINT8 Reserved1[3]; + { + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE + }, + // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE BaseAddress; + ARM_GAS32 (FixedPcdGet64 (PcdSerialRegisterBase)), + // UINT8 InterruptType; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC, + // UINT8 Irq; + 0, // Not used on ARM + // UINT32 GlobalSystemInterrupt; + FixedPcdGet32 (PL011UartInterrupt), + // UINT8 BaudRate; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200, + // UINT8 Parity; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY, + // UINT8 StopBits; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1, + // UINT8 FlowControl; + SPCR_FLOW_CONTROL_NONE, + // UINT8 TerminalType; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI, + // UINT8 Reserved2; + EFI_ACPI_RESERVED_BYTE, + // UINT16 PciDeviceId; + 0xFFFF, + // UINT16 PciVendorId; + 0xFFFF, + // UINT8 PciBusNumber; + 0x00, + // UINT8 PciDeviceNumber; + 0x00, + // UINT8 PciFunctionNumber; + 0x00, + // UINT32 PciFlags; + 0x00000000, + // UINT8 PciSegment; + 0x00, + // UINT32 Reserved3; + EFI_ACPI_RESERVED_DWORD +}; + +VOID * CONST ReferenceAcpiTable = &Spcr; -- 2.25.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-04-02 8:47 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2021-03-12 10:55 [PATCH v3 00/46] Added support for FT2000/4 chip Ling Jia 2021-03-12 10:55 ` [PATCH v3 01/46] TigerlakeOpenBoardPkg: Fix build errors with GCC5 Ling Jia 2021-04-01 19:19 ` Nate DeSimone 2021-04-02 8:46 ` Ling Jia 2021-03-12 10:55 ` [PATCH v3 14/46] Silicon/Phytium: Added Acpi support to FT2000/4 Ling Jia -- strict thread matches above, loose matches on Subject: below -- 2021-03-12 11:01 [PATCH v3 00/46] Added support for FT2000/4 chip Ling Jia 2021-03-12 11:01 ` [PATCH v3 14/46] Silicon/Phytium: Added Acpi support to FT2000/4 Ling Jia
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