From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from zg8tmty1ljiyny4xntqumjca.icoremail.net (zg8tmty1ljiyny4xntqumjca.icoremail.net [165.227.154.27]) by mx.groups.io with SMTP id smtpd.web11.6619.1615546635009233045 for ; Fri, 12 Mar 2021 02:57:15 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: phytium.com.cn, ip: 165.227.154.27, mailfrom: jialing@phytium.com.cn) Received: from localhost.localdomain (unknown [223.104.131.160]) by c1app11 (Coremail) with SMTP id CwINCgD3GAbgSEtgauKHAw--.20002S3; Fri, 12 Mar 2021 18:57:06 +0800 (CST) From: Ling Jia To: devel@edk2.groups.io Cc: Leif Lindholm , Peng Xie , Yiqi Shu , Takuto Naito , Sai Chaganty , Nate DeSimone , Heng Luo Subject: [PATCH v3 01/46] TigerlakeOpenBoardPkg: Fix build errors with GCC5 Date: Fri, 12 Mar 2021 18:55:33 +0800 Message-Id: <20210312105618.75605-2-jialing@phytium.com.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210312105618.75605-1-jialing@phytium.com.cn> References: <20210312105618.75605-1-jialing@phytium.com.cn> MIME-Version: 1.0 X-CM-TRANSID: CwINCgD3GAbgSEtgauKHAw--.20002S3 X-Coremail-Antispam: 1UD129KBjvJXoWxKF4UtrykJr17ZFW8tF1rtFb_yoWxZF1fpr WDJr47A34rWr4a9r47Xa48CF1qyFWDJw1rJ3yrZw18XwnIyws7AFn0ya4fZ3y3ArnxtFyx uF4j9w47CFsFqr7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBYb7Iv0xC_Kw4lb4IE77IF4wAFF20E14v26r4j6ryUM7CY07I2 0VC2zVCF04k26cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI 8067AKxVWUGwA2048vs2IY020Ec7CjxVAFwI0_Jrv_JF4l8cAvFVAK0II2c7xJM28CjxkF 64kEwVA0rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVWUJVWUCwA2z4x0Y4vE2Ix0cI8IcV CY1x0267AKxVW8JVWxJwA2z4x0Y4vEx4A2jsIE14v26r4UJVWxJr1l84ACjcxK6I8E87Iv 6xkF7I0E14v26rxl6s0DM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c 02F40Ex7xfMcIj6xIIjxv20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE 4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41lc2xSY4AK67AK6r4DMxAIw28IcxkI7V AKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCj r7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6x IIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAI w20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x 0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7IU5DgA7UUUUU== X-Originating-IP: [223.104.131.160] X-CM-SenderInfo: xmldzxdqj61x51wl3zoofrzhdfq/ Content-Transfer-Encoding: quoted-printable From: Takuto Naito REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3224 - Fix the path of TigerLakeFspBinPkg - Fix misuse of RETURN_ERROR - Remove unused function CheckNationalSio. Cc: Sai Chaganty Cc: Nate DeSimone Cc: Heng Luo Signed-off-by: Takuto Naito Reviewed-by: Heng Luo Reviewed-by: Nate DeSimone --- Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLi= b/PeiFspPolicyInitLib.inf | 2 +- Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatf= ormHookLib.c | 188 -------------------- Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdate= Lib/DxeSiliconPolicyUpdateLate.c | 2 +- 3 files changed, 2 insertions(+), 190 deletions(-) diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFsp= PolicyInitLib/PeiFspPolicyInitLib.inf b/Platform/Intel/TigerlakeOpenBoardPk= g/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf index 9d85d855f501..708fbac08fd6 100644 --- a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI= nitLib/PeiFspPolicyInitLib.inf +++ b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI= nitLib/PeiFspPolicyInitLib.inf @@ -52,7 +52,7 @@ [Packages] MdeModulePkg/MdeModulePkg.dec=0D IntelFsp2Pkg/IntelFsp2Pkg.dec=0D TigerlakeSiliconPkg/SiPkg.dec=0D - TigerLakeFspBinPkg/TigerLakeFspBinPkg.dec=0D + TigerLakeFspBinPkg/Client/TigerLakeFspBinPkg.dec=0D TigerlakeOpenBoardPkg/OpenBoardPkg.dec=0D UefiCpuPkg/UefiCpuPkg.dec=0D IntelSiliconPkg/IntelSiliconPkg.dec=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookL= ib/BasePlatformHookLib.c b/Platform/Intel/TigerlakeOpenBoardPkg/Library/Bas= ePlatformHookLib/BasePlatformHookLib.c index 6209e5045061..cc5337698b8a 100644 --- a/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/Base= PlatformHookLib.c +++ b/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/Base= PlatformHookLib.c @@ -94,194 +94,6 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTableWi= nbond_x374[] =3D { {0x30, 0x01} // Enable it with Activation bit=0D };=0D =0D -/**=0D - Detect if a National 393 SIO is docked. If yes, enable the docked SIO=0D - and its serial port, and disable the onboard serial port.=0D -=0D - @retval EFI_SUCCESS Operations performed successfully.=0D -**/=0D -STATIC=0D -VOID=0D -CheckNationalSio (=0D - VOID=0D - )=0D -{=0D - UINT8 Data8;=0D -=0D - //=0D - // Pc87393 access is through either (0x2e, 0x2f) or (0x4e, 0x4f).=0D - // We use (0x2e, 0x2f) which is determined by BADD default strapping=0D - //=0D -=0D - //=0D - // Read the Pc87393 signature=0D - //=0D - IoWrite8 (0x2e, 0x20);=0D - Data8 =3D IoRead8 (0x2f);=0D -=0D - if (Data8 =3D=3D 0xea) {=0D - //=0D - // Signature matches - National PC87393 SIO is docked=0D - //=0D -=0D - //=0D - // Enlarge the LPC decode scope to accommodate the Docking LPC Switch= =0D - // Register (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS is allocated at=0D - // SIO_BASE_ADDRESS + 0x10)=0D - //=0D - PchLpcGenIoRangeSet ((FixedPcdGet16 (PcdSioBaseAddress) & (UINT16)~0x7= F), 0x20);=0D -=0D - //=0D - // Enable port switch=0D - //=0D - IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x06);=0D -=0D - //=0D - // Turn on docking power=0D - //=0D - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x8c);=0D -=0D - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x9c);=0D -=0D - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0xBc);=0D -=0D - //=0D - // Enable port switch=0D - //=0D - IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x7);=0D -=0D - //=0D - // GPIO setting=0D - //=0D - IoWrite8 (0x2e, 0x24);=0D - IoWrite8 (0x2f, 0x29);=0D -=0D - //=0D - // Enable chip clock=0D - //=0D - IoWrite8 (0x2e, 0x29);=0D - IoWrite8 (0x2f, 0x1e);=0D -=0D -=0D - //=0D - // Enable serial port=0D - //=0D -=0D - //=0D - // Select com1=0D - //=0D - IoWrite8 (0x2e, 0x7);=0D - IoWrite8 (0x2f, 0x3);=0D -=0D - //=0D - // Base address: 0x3f8=0D - //=0D - IoWrite8 (0x2e, 0x60);=0D - IoWrite8 (0x2f, 0x03);=0D - IoWrite8 (0x2e, 0x61);=0D - IoWrite8 (0x2f, 0xf8);=0D -=0D - //=0D - // Interrupt: 4=0D - //=0D - IoWrite8 (0x2e, 0x70);=0D - IoWrite8 (0x2f, 0x04);=0D -=0D - //=0D - // Enable bank selection=0D - //=0D - IoWrite8 (0x2e, 0xf0);=0D - IoWrite8 (0x2f, 0x82);=0D -=0D - //=0D - // Activate=0D - //=0D - IoWrite8 (0x2e, 0x30);=0D - IoWrite8 (0x2f, 0x01);=0D -=0D - //=0D - // Disable onboard serial port=0D - //=0D - IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0x55);=0D -=0D - //=0D - // Power Down UARTs=0D - //=0D - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x2);=0D - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x00);=0D -=0D - //=0D - // Dissable COM1 decode=0D - //=0D - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x24);=0D - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0);=0D -=0D - //=0D - // Disable COM2 decode=0D - //=0D - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x25);=0D - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0);=0D -=0D - //=0D - // Disable interrupt=0D - //=0D - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x28);=0D - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x0);=0D -=0D - IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA);=0D -=0D - //=0D - // Enable floppy=0D - //=0D -=0D - //=0D - // Select floppy=0D - //=0D - IoWrite8 (0x2e, 0x7);=0D - IoWrite8 (0x2f, 0x0);=0D -=0D - //=0D - // Base address: 0x3f0=0D - //=0D - IoWrite8 (0x2e, 0x60);=0D - IoWrite8 (0x2f, 0x03);=0D - IoWrite8 (0x2e, 0x61);=0D - IoWrite8 (0x2f, 0xf0);=0D -=0D - //=0D - // Interrupt: 6=0D - //=0D - IoWrite8 (0x2e, 0x70);=0D - IoWrite8 (0x2f, 0x06);=0D -=0D - //=0D - // DMA 2=0D - //=0D - IoWrite8 (0x2e, 0x74);=0D - IoWrite8 (0x2f, 0x02);=0D -=0D - //=0D - // Activate=0D - //=0D - IoWrite8 (0x2e, 0x30);=0D - IoWrite8 (0x2f, 0x01);=0D -=0D - } else {=0D -=0D - //=0D - // No National pc87393 SIO is docked, turn off dock power and=0D - // disable port switch=0D - //=0D - // IoWrite8 (SIO_BASE_ADDRESS + 0x0E, 0xbf);=0D - // IoWrite8 (0x690, 0);=0D -=0D - //=0D - // If no National pc87393, just return=0D - //=0D - return ;=0D - }=0D -}=0D -=0D /**=0D Check whether the IT8628 SIO present on LPC. If yes, enable its serial por= ts=0D =0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSilicon= PolicyUpdateLib/DxeSiliconPolicyUpdateLate.c b/Platform/Intel/TigerlakeOpen= BoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLat= e.c index 2eee9958beea..410a8d1073a9 100644 --- a/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyU= pdateLib/DxeSiliconPolicyUpdateLate.c +++ b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyU= pdateLib/DxeSiliconPolicyUpdateLate.c @@ -88,8 +88,8 @@ SiliconPolicyUpdateLate ( // GOP Dxe Policy Initialization=0D //=0D Status =3D GopPolicyInitDxe (gImageHandle);=0D - RETURN_ERROR (Status);=0D DEBUG ((DEBUG_INFO, "GOP Dxe Policy Initialization done\n"));=0D + ASSERT_EFI_ERROR (Status);=0D }=0D =0D return Policy;=0D --=20 2.25.1