From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from zg8tmja5ljk3lje4mi4ymjia.icoremail.net (zg8tmja5ljk3lje4mi4ymjia.icoremail.net [209.97.182.222]) by mx.groups.io with SMTP id smtpd.web09.6574.1615546935395452910 for ; Fri, 12 Mar 2021 03:02:15 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: phytium.com.cn, ip: 209.97.182.222, mailfrom: jialing@phytium.com.cn) Received: from localhost.localdomain (unknown [223.104.131.160]) by c1app4 (Coremail) with SMTP id BAINCgC3mwEVSktgMY01BQ--.34795S18; Fri, 12 Mar 2021 19:02:10 +0800 (CST) From: Ling Jia To: devel@edk2.groups.io Cc: Leif Lindholm , Peng Xie , Yiqi Shu , Ling Jia Subject: [PATCH v3 41/46] Silicon/Phytium: Added PciHostBridgeLib to FT2000/4 Date: Fri, 12 Mar 2021 19:01:36 +0800 Message-Id: <20210312110141.75749-17-jialing@phytium.com.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210312110141.75749-1-jialing@phytium.com.cn> References: <20210312110141.75749-1-jialing@phytium.com.cn> MIME-Version: 1.0 X-CM-TRANSID: BAINCgC3mwEVSktgMY01BQ--.34795S18 X-Coremail-Antispam: 1UD129KBjvJXoWxtw1rWFWxWr1rGF4UGryUKFg_yoWfZF1rpw 4Utan8X345X3Wjvw48A3s2gF43Aa9Fkw45Jr43Xw17ZFyfXF4kJrsFka43Wa4jq3WDXw4x WF1YqFyfu3ZYgaUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUm014x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F 4UJwA2z4x0Y4vEx4A2jsIE14v26r4UJVWxJr1l84ACjcxK6I8E87Iv6xkF7I0E14v26rxl 6s0DM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6x IIjxv20xvE14v26r106r15McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_ Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7MxkF7I0En4kS14v26r 126r1DMxkIecxEwVAFwVW8KwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8 JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1V AFwI0_JF0_Jw1lIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVW8JVW5JwCI42IY6xII jxv20xvEc7CjxVAFwI0_Gr1j6F4UJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcV C2z280aVAFwI0_Gr0_Cr1lIxAIcVC2z280aVCY1x0267AKxVW8Jr0_Cr1UYxBIdaVFxhVj vjDU0xZFpf9x0JUk8nOUUUUU= X-Originating-IP: [223.104.131.160] X-CM-SenderInfo: xmldzxdqj61x51wl3zoofrzhdfq/ Content-Transfer-Encoding: quoted-printable The Pci host bridge library is mainly to get Pci bridge information. v3: Optimize the codes of PciHostBridgeLib.c to conform to specifications. Signed-off-by: Ling Jia Reviewed-by: Leif Lindholm --- Platform/Phytium/DurianPkg/DurianPkg.dsc = | 9 + Platform/Phytium/DurianPkg/DurianPkg.fdf = | 6 + Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf = | 47 +++++ Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.c = | 181 ++++++++++++++++++++ 4 files changed, 243 insertions(+) diff --git a/Platform/Phytium/DurianPkg/DurianPkg.dsc b/Platform/Phytium/Du= rianPkg/DurianPkg.dsc index 093b2cd9dbd4..3a9bc2289cf3 100644 --- a/Platform/Phytium/DurianPkg/DurianPkg.dsc +++ b/Platform/Phytium/DurianPkg/DurianPkg.dsc @@ -37,6 +37,7 @@ [LibraryClasses.common] [LibraryClasses.common.DXE_DRIVER]=0D # Pci dependencies=0D PciSegmentLib|Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegme= ntLib.inf=0D + PciHostBridgeLib|Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/Pc= iHostBridgeLib.inf=0D =0D ##########################################################################= ######=0D #=0D @@ -263,6 +264,14 @@ [Components.common] MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf=0D MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf=0D =0D + #=0D + # PCI Support=0D + #=0D + ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf=0D + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf=0D + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf=0D + MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDevic= eDxe.inf=0D +=0D #=0D # The following 2 module perform the same work except one operate variab= le.=0D # Only one of both should be put into fdf.=0D diff --git a/Platform/Phytium/DurianPkg/DurianPkg.fdf b/Platform/Phytium/Du= rianPkg/DurianPkg.fdf index 3106a43fb744..a443d0f3a4ac 100644 --- a/Platform/Phytium/DurianPkg/DurianPkg.fdf +++ b/Platform/Phytium/DurianPkg/DurianPkg.fdf @@ -135,6 +135,12 @@ [FV.FvMain] INF FatPkg/EnhancedFatDxe/Fat.inf=0D INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.i= nf=0D =0D + #=0D + # PCI Support=0D + #=0D + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf=0D + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf=0D +=0D #=0D # SATA Controller=0D #=0D diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBr= idgeLib.inf b/Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostB= ridgeLib.inf new file mode 100644 index 000000000000..0e6f0797b0fe --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib= .inf @@ -0,0 +1,47 @@ +#/** @file=0D +# PCI Host Bridge Library instance for Phytium SOC.=0D +#=0D +# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +#**/=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x0001001b=0D + BASE_NAME =3D PciHostBridgeLib=0D + FILE_GUID =3D f965de0e-40fe-11eb-8290-3f9d1f895a80= =0D + MODULE_TYPE =3D DXE_DRIVER=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D PciHostBridgeLib|DXE_DRIVER=0D +=0D +#=0D +# The following information is for reference only and not required by the = build=0D +# tools.=0D +#=0D +# VALID_ARCHITECTURES =3D ARM AARCH64=0D +#=0D +=0D +[Sources]=0D + PciHostBridgeLib.c=0D +=0D +[Packages]=0D + ArmPkg/ArmPkg.dec=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec=0D +=0D +[LibraryClasses]=0D + DebugLib=0D +=0D +[Guids]=0D +=0D +[FixedPcd]=0D + gArmTokenSpaceGuid.PcdPciBusMin=0D + gArmTokenSpaceGuid.PcdPciBusMax=0D + gArmTokenSpaceGuid.PcdPciIoBase=0D + gArmTokenSpaceGuid.PcdPciIoSize=0D + gArmTokenSpaceGuid.PcdPciMmio32Base=0D + gArmTokenSpaceGuid.PcdPciMmio32Size=0D + gArmTokenSpaceGuid.PcdPciMmio64Base=0D + gArmTokenSpaceGuid.PcdPciMmio64Size=0D diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBr= idgeLib.c b/Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBri= dgeLib.c new file mode 100644 index 000000000000..8ed3516749a1 --- /dev/null +++ b/Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib= .c @@ -0,0 +1,181 @@ +/** @file=0D + PCI host bridge library instance for Phytium SOC.=0D +=0D + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
= =0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#pragma pack(1)=0D +=0D +typedef struct {=0D + ACPI_HID_DEVICE_PATH AcpiDevicePath;=0D + EFI_DEVICE_PATH_PROTOCOL EndDevicePath;=0D +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;=0D +=0D +#pragma pack ()=0D +=0D +#define END_DEVICE_PATH_DEF { END_DEVICE_PATH_TYPE, \=0D + END_ENTIRE_DEVICE_PATH_SUBTYPE, \=0D + { END_DEVICE_PATH_LENGTH, 0 } \=0D + }=0D +=0D +#define ACPI_DEVICE_PATH_DEF(UID) {{ ACPI_DEVICE_PATH, ACPI_DP, \=0D + { (UINT8) (sizeof (ACPI_HID_DEVICE_PA= TH)), \=0D + (UINT8) (sizeof (ACPI_HID_DEVICE_PA= TH) >> 8)} \=0D + }, \=0D + EISA_PNP_ID (0x0A03), UID \=0D + }=0D +=0D +STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[]= =3D {=0D + {=0D + ACPI_DEVICE_PATH_DEF (0),=0D + END_DEVICE_PATH_DEF=0D + },=0D +};=0D +=0D +GLOBAL_REMOVE_IF_UNREFERENCED=0D +CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] =3D {=0D + L"Mem", L"I/O", L"Bus"=0D +};=0D +=0D +STATIC PCI_ROOT_BRIDGE mRootBridge =3D {=0D + 0, // Segment=0D + 0, // Supports=0D + 0, // Attributes=0D + TRUE, // DmaAbove4G=0D + FALSE, // NoExtendedConfigSpace= =0D + FALSE, // ResourceAssigned=0D + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes= =0D + EFI_PCI_HOST_BRIDGE_MEM64_DECODE,=0D + {=0D + // Bus=0D + FixedPcdGet32 (PcdPciBusMin),=0D + FixedPcdGet32 (PcdPciBusMax)=0D + }, {=0D + // Io=0D + FixedPcdGet64 (PcdPciIoBase),=0D + FixedPcdGet64 (PcdPciIoBase) + FixedPcdGet64 (PcdPciIoSize) - 1=0D + }, {=0D + // Mem=0D + FixedPcdGet32 (PcdPciMmio32Base),=0D + FixedPcdGet32 (PcdPciMmio32Base) + (FixedPcdGet32 (PcdPciMmio32Size) -= 1)=0D + //0x7FFFFFFF=0D + }, {=0D + // MemAbove4G=0D + FixedPcdGet64 (PcdPciMmio64Base),=0D + FixedPcdGet64 (PcdPciMmio64Base) + FixedPcdGet64 (PcdPciMmio64Size) - = 1=0D + }, {=0D + // PMem=0D + MAX_UINT64,=0D + 0=0D + }, {=0D + // PMemAbove4G=0D + MAX_UINT64,=0D + 0=0D + },=0D + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath=0D +};=0D +=0D +/**=0D + Return all the root bridge instances in an array.=0D +=0D + @param[out] Count Return the count of root bridge instances.=0D +=0D + @return All the root bridge instances in an array.=0D + The array should be passed into PciHostBridgeFreeRootBridges()=0D + when it's not used.=0D +=0D +**/=0D +PCI_ROOT_BRIDGE *=0D +EFIAPI=0D +PciHostBridgeGetRootBridges (=0D + OUT UINTN *Count=0D + )=0D +{=0D + *Count =3D 1;=0D + return &mRootBridge;=0D +}=0D +=0D +=0D +/**=0D + Free the root bridge instances array returned from PciHostBridgeGetRootB= ridges().=0D +=0D + @param[in] Bridges The root bridge instances array.=0D + @param[in] Count The count of the array.=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +PciHostBridgeFreeRootBridges (=0D + IN PCI_ROOT_BRIDGE *Bridges,=0D + IN UINTN Count=0D + )=0D +{=0D +=0D +}=0D +=0D +=0D +/**=0D + Inform the platform that the resource conflict happens.=0D +=0D + @param[in] HostBridgeHandle Handle of the Host Bridge.=0D + @param[in] Configuration Pointer to PCI I/O and PCI memory resource=0D + descriptors. The Configuration contains the reso= urces=0D + for all the root bridges. The resource for each = root=0D + bridge is terminated with END descriptor and an= =0D + additional END is appended indicating the end of= the=0D + entire resources. The resource descriptor field= =0D + values follow the description in=0D + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL= =0D + SubmitResources().=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +PciHostBridgeResourceConflict (=0D + IN EFI_HANDLE HostBridgeHandle,=0D + IN VOID *Configuration=0D + )=0D +{=0D + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;=0D + BOOLEAN IsPrefetchable;=0D +=0D + Descriptor =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;=0D + while (Descriptor->Desc =3D=3D ACPI_ADDRESS_SPACE_DESCRIPTOR) {=0D + for (; Descriptor->Desc =3D=3D ACPI_ADDRESS_SPACE_DESCRIPTOR; Descript= or++) {=0D + ASSERT (Descriptor->ResType <=0D + ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr));=0D + DEBUG ((DEBUG_INFO, " %s: Length/Alignment =3D 0x%lx / 0x%lx\n",=0D + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType= ],=0D + Descriptor->AddrLen,=0D + Descriptor->AddrRangeMax=0D + ));=0D + if (Descriptor->ResType =3D=3D ACPI_ADDRESS_SPACE_TYPE_MEM) {=0D +=0D + IsPrefetchable =3D (Descriptor->SpecificFlag &=0D + EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE) != =3D 0;=0D +=0D + DEBUG ((DEBUG_INFO, " Granularity/SpecificFlag =3D %ld / %02x%= s\n",=0D + Descriptor->AddrSpaceGranularity,=0D + Descriptor->SpecificFlag,=0D + (IsPrefetchable) ? L" (Prefetchable)" : L""=0D + ));=0D + }=0D + }=0D + //=0D + // Skip the end descriptor for root bridge=0D + //=0D + ASSERT (Descriptor->Desc =3D=3D ACPI_END_TAG_DESCRIPTOR);=0D + Descriptor =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) (=0D + (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1=0D + );=0D + }=0D +}=0D --=20 2.25.1