From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web08.8877.1615816142071017221 for ; Mon, 15 Mar 2021 06:49:02 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.65, mailfrom: yun.lou@intel.com) IronPort-SDR: 9FqpxT8O0KBd7ugufr+R8wTEkP/FSpc4M5TyPSS3/er24Oivlzey05n9ubFPu4ZYgmchATejQc 8Sg+re33FBNA== X-IronPort-AV: E=McAfee;i="6000,8403,9923"; a="189136356" X-IronPort-AV: E=Sophos;i="5.81,249,1610438400"; d="scan'208";a="189136356" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Mar 2021 06:49:01 -0700 IronPort-SDR: efpMFfyJqjreFdbv4RBEo9Bbu+APR/Hu2BR5hLkN2Amv6ls5Venz26Zjdvw7ZLY2oX69/Ar4vP s5t5Zw5QCuwQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,249,1610438400"; d="scan'208";a="601435454" Received: from shwdeopenlab102.ccr.corp.intel.com ([10.239.183.74]) by fmsmga006.fm.intel.com with ESMTP; 15 Mar 2021 06:48:58 -0700 From: "Jason Lou" To: devel@edk2.groups.io Cc: Jason , Ray Ni , Eric Dong , Laszlo Ersek , Rahul Kumar Subject: [PATCH v2 1/1] UefiCpuPkg/CpuCacheInfoLib: Collect cache associative type Date: Mon, 15 Mar 2021 21:48:53 +0800 Message-Id: <20210315134854.6363-1-yun.lou@intel.com> X-Mailer: git-send-email 2.28.0.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3265 Support collecting cache associative type in CpuCacheInfoLib. This prevents the user from using additional code to obtain the same information. Signed-off-by: Jason Lou Cc: Ray Ni Cc: Eric Dong Cc: Laszlo Ersek Cc: Rahul Kumar --- UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c | 49 ++++++++= +++--------- UefiCpuPkg/Include/Library/CpuCacheInfoLib.h | 15 +++++- UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h | 15 +++++- 3 files changed, 53 insertions(+), 26 deletions(-) diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c b/UefiCpu= Pkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c index d46fb0425851..126ee0da86fc 100644 --- a/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c +++ b/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c @@ -1,7 +1,7 @@ /** @file=0D Provides cache info for each package, core type, cache level and cache t= ype.=0D =0D - Copyright (c) 2020 Intel Corporation. All rights reserved.
=0D + Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D **/=0D @@ -23,18 +23,18 @@ CpuCacheInfoPrintCpuCacheInfoTable ( {=0D UINTN Index;=0D =0D - DEBUG ((DEBUG_INFO, "+-------+------------------------------------------= -------------------------------------+\n"));=0D - DEBUG ((DEBUG_INFO, "| Index | Packge CoreType CacheLevel CacheType = CacheWays CacheSizeinKB CacheCount |\n"));=0D - DEBUG ((DEBUG_INFO, "+-------+------------------------------------------= -------------------------------------+\n"));=0D + DEBUG ((DEBUG_INFO, "+-------+------------------------------------------= --------------------------------------------+\n"));=0D + DEBUG ((DEBUG_INFO, "| Index | Packge CoreType CacheLevel CacheType = CacheWays (FA|DM) CacheSizeinKB CacheCount |\n"));=0D + DEBUG ((DEBUG_INFO, "+-------+------------------------------------------= --------------------------------------------+\n"));=0D =0D for (Index =3D 0; Index < CpuCacheInfoCount; Index++) {=0D - DEBUG ((DEBUG_INFO, "| %4x | %4x %2x %2x %2x = %4x %8x %4x |\n", Index,=0D - CpuCacheInfo[Index].Package, CpuCacheInfo[Index].CoreType, CpuCach= eInfo[Index].CacheLevel,=0D - CpuCacheInfo[Index].CacheType, CpuCacheInfo[Index].CacheWays, CpuC= acheInfo[Index].CacheSizeinKB,=0D - CpuCacheInfo[Index].CacheCount));=0D + DEBUG ((DEBUG_INFO, "| %4x | %4x %2x %2x %2x = %4x ( %x| %x) %8x %4x |\n",=0D + Index, CpuCacheInfo[Index].Package, CpuCacheInfo[Index].CoreType, = CpuCacheInfo[Index].CacheLevel,=0D + CpuCacheInfo[Index].CacheType, CpuCacheInfo[Index].CacheWays, CpuC= acheInfo[Index].FullyAssociativeCache,=0D + CpuCacheInfo[Index].DirectMappedCache, CpuCacheInfo[Index].CacheSi= zeinKB, CpuCacheInfo[Index].CacheCount));=0D }=0D =0D - DEBUG ((DEBUG_INFO, "+-------+------------------------------------------= -------------------------------------+\n"));=0D + DEBUG ((DEBUG_INFO, "+-------+------------------------------------------= --------------------------------------------+\n"));=0D }=0D =0D /**=0D @@ -160,6 +160,7 @@ CpuCacheInfoCollectCoreAndCacheData ( CPUID_CACHE_PARAMS_EAX CacheParamEax;=0D CPUID_CACHE_PARAMS_EBX CacheParamEbx;=0D UINT32 CacheParamEcx;=0D + CPUID_CACHE_PARAMS_EDX CacheParamEdx;=0D CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX NativeModelIdAndCoreTypeEax;=0D COLLECT_CPUID_CACHE_DATA_CONTEXT *Context;=0D CPUID_CACHE_DATA *CacheData;=0D @@ -185,17 +186,19 @@ CpuCacheInfoCollectCoreAndCacheData ( CacheParamLeafIndex =3D 0;=0D =0D while (CacheParamLeafIndex < MAX_NUM_OF_CACHE_PARAMS_LEAF) {=0D - AsmCpuidEx (CPUID_CACHE_PARAMS, CacheParamLeafIndex, &CacheParamEax.Ui= nt32, &CacheParamEbx.Uint32, &CacheParamEcx, NULL);=0D + AsmCpuidEx (CPUID_CACHE_PARAMS, CacheParamLeafIndex, &CacheParamEax.Ui= nt32, &CacheParamEbx.Uint32, &CacheParamEcx, &CacheParamEdx.Uint32);=0D =0D if (CacheParamEax.Bits.CacheType =3D=3D 0) {=0D break;=0D }=0D =0D - CacheData[CacheParamLeafIndex].CacheLevel =3D (UINT8)CacheParamEax= .Bits.CacheLevel;=0D - CacheData[CacheParamLeafIndex].CacheType =3D (UINT8)CacheParamEax= .Bits.CacheType;=0D - CacheData[CacheParamLeafIndex].CacheWays =3D (UINT16)CacheParamEb= x.Bits.Ways;=0D - CacheData[CacheParamLeafIndex].CacheShareBits =3D (UINT16)CacheParamEa= x.Bits.MaximumAddressableIdsForLogicalProcessors;=0D - CacheData[CacheParamLeafIndex].CacheSizeinKB =3D (CacheParamEbx.Bits.= Ways + 1) *=0D + CacheData[CacheParamLeafIndex].CacheLevel =3D (UINT8)CacheP= aramEax.Bits.CacheLevel;=0D + CacheData[CacheParamLeafIndex].CacheType =3D (UINT8)CacheP= aramEax.Bits.CacheType;=0D + CacheData[CacheParamLeafIndex].CacheWays =3D (UINT16)Cache= ParamEbx.Bits.Ways;=0D + CacheData[CacheParamLeafIndex].FullyAssociativeCache =3D (UINT8)CacheP= aramEax.Bits.FullyAssociativeCache;=0D + CacheData[CacheParamLeafIndex].DirectMappedCache =3D (UINT8)CacheP= aramEdx.Bits.ComplexCacheIndexing;=0D + CacheData[CacheParamLeafIndex].CacheShareBits =3D (UINT16)Cache= ParamEax.Bits.MaximumAddressableIdsForLogicalProcessors;=0D + CacheData[CacheParamLeafIndex].CacheSizeinKB =3D (CacheParamEb= x.Bits.Ways + 1) *=0D (CacheParamEbx.Bits.LinePartitions + 1) * (CacheParamEbx.Bits.Line= Size + 1) * (CacheParamEcx + 1) / SIZE_1KB;=0D =0D CacheParamLeafIndex++;=0D @@ -305,13 +308,15 @@ CpuCacheInfoCollectCpuCacheInfoData ( if (CacheInfoIndex =3D=3D LocalCacheInfoCount) {=0D ASSERT (LocalCacheInfoCount < MaxCacheInfoCount);=0D =0D - LocalCacheInfo[LocalCacheInfoCount].Package =3D ProcessorInfo[= Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package;=0D - LocalCacheInfo[LocalCacheInfoCount].CoreType =3D ProcessorInfo[= Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType;=0D - LocalCacheInfo[LocalCacheInfoCount].CacheLevel =3D CacheData[Inde= x].CacheLevel;=0D - LocalCacheInfo[LocalCacheInfoCount].CacheType =3D CacheData[Inde= x].CacheType;=0D - LocalCacheInfo[LocalCacheInfoCount].CacheWays =3D CacheData[Inde= x].CacheWays;=0D - LocalCacheInfo[LocalCacheInfoCount].CacheSizeinKB =3D CacheData[Inde= x].CacheSizeinKB;=0D - LocalCacheInfo[LocalCacheInfoCount].CacheCount =3D 1;=0D + LocalCacheInfo[LocalCacheInfoCount].Package =3D Proces= sorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package;=0D + LocalCacheInfo[LocalCacheInfoCount].CoreType =3D Proces= sorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType;=0D + LocalCacheInfo[LocalCacheInfoCount].CacheLevel =3D CacheD= ata[Index].CacheLevel;=0D + LocalCacheInfo[LocalCacheInfoCount].CacheType =3D CacheD= ata[Index].CacheType;=0D + LocalCacheInfo[LocalCacheInfoCount].CacheWays =3D CacheD= ata[Index].CacheWays;=0D + LocalCacheInfo[LocalCacheInfoCount].FullyAssociativeCache =3D CacheD= ata[Index].FullyAssociativeCache;=0D + LocalCacheInfo[LocalCacheInfoCount].DirectMappedCache =3D CacheD= ata[Index].DirectMappedCache;=0D + LocalCacheInfo[LocalCacheInfoCount].CacheSizeinKB =3D CacheD= ata[Index].CacheSizeinKB;=0D + LocalCacheInfo[LocalCacheInfoCount].CacheCount =3D 1;=0D =0D LocalCacheInfoCount++;=0D }=0D diff --git a/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h b/UefiCpuPkg/Incl= ude/Library/CpuCacheInfoLib.h index a7f29b188775..a66152bce009 100644 --- a/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h +++ b/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h @@ -1,7 +1,7 @@ /** @file=0D Header file for CPU Cache info Library.=0D =0D - Copyright (c) 2020, Intel Corporation. All rights reserved.
=0D + Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D **/=0D @@ -33,7 +33,18 @@ typedef struct { // Ways of associativity.=0D // Value =3D CPUID.04h:EBX[31:22]=0D //=0D - UINT16 CacheWays;=0D + UINT16 CacheWays : 10;=0D + //=0D + // Fully associative cache.=0D + // Value =3D CPUID.04h:EAX[09]=0D + //=0D + UINT16 FullyAssociativeCache : 1;=0D + //=0D + // Direct mapped cache.=0D + // Value =3D CPUID.04h:EDX[02]=0D + //=0D + UINT16 DirectMappedCache : 1;=0D + UINT16 Reserved : 4;=0D //=0D // Size of single cache that this package's this type of logical process= or corresponds to.=0D // Value =3D (CPUID.04h:EBX[31:22] + 1) * (CPUID.04h:EBX[21:12] + 1) *=0D diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h b= /UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h index de56db9c0cbe..b6e6ae5bc50a 100644 --- a/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h +++ b/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h @@ -1,7 +1,7 @@ /** @file=0D Internal header file for CPU Cache info Library.=0D =0D - Copyright (c) 2020, Intel Corporation. All rights reserved.
=0D + Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D **/=0D @@ -52,7 +52,18 @@ typedef struct { // Ways of associativity.=0D // Value =3D CPUID.04h:EBX[31:22]=0D //=0D - UINT16 CacheWays;=0D + UINT16 CacheWays : 10;=0D + //=0D + // Fully associative cache.=0D + // Value =3D CPUID.04h:EAX[09]=0D + //=0D + UINT16 FullyAssociativeCache : 1;=0D + //=0D + // Direct mapped cache.=0D + // Value =3D CPUID.04h:EDX[02]=0D + //=0D + UINT16 DirectMappedCache : 1;=0D + UINT16 Reserved : 4;=0D //=0D // Cache share bits.=0D // Value =3D CPUID.04h:EAX[25:14]=0D --=20 2.28.0.windows.1