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[193.106.246.138]) by smtp.gmail.com with ESMTPSA id b30sm344622lfj.101.2021.03.18.12.58.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Mar 2021 12:58:22 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ard.biesheuvel@arm.com, mw@semihalf.com, jaz@semihalf.com, kostap@marvell.com, upstream@semihalf.com, jon@solid-run.com Subject: [edk2-non-osi PATCH 2/4] Marvell/Armada7k8k: Move device tree sources from edk2-platforms Date: Thu, 18 Mar 2021 20:57:54 +0100 Message-Id: <20210318195757.2974226-2-mw@semihalf.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210318195757.2974226-1-mw@semihalf.com> References: <20210318195757.2974226-1-mw@semihalf.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable edk2-non-osi project is a more proper place for keeping the device tree sources, so keep it here from now on. Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf | 22 + Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf | 22 + Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf | 22 + Silicon/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi | 16 + Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts | 267 +++++++= +++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi | 16 + Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi | 64 +++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi | 26 + Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts | 336 +++++++= +++++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts | 377 +++++++= ++++++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi | 25 + Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi | 108 ++++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi | 31 ++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi | 43 ++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi | 264 +++++++= ++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi | 10 + Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi | 560 +++++++= +++++++++++++ 17 files changed, 2209 insertions(+) create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.i= nf create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin= .dts create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual= .dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad= .dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf b/Silic= on/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf new file mode 100644 index 0000000..b533578 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/Armada70x0Db.inf @@ -0,0 +1,22 @@ +## @file=0D +#=0D +# Device tree description of the Marvell Armada 7040 DB platform=0D +#=0D +# Copyright (c) 2018, Marvell International Ltd. All rights reserved.=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x0001001A=0D + BASE_NAME =3D Armada70x0DbDeviceTree=0D + FILE_GUID =3D 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDef= aultDtbFileGuid=0D + MODULE_TYPE =3D USER_DEFINED=0D + VERSION_STRING =3D 1.0=0D +=0D +[Sources]=0D + armada-7040-db.dts=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf b/Silic= on/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf new file mode 100644 index 0000000..378fad2 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf @@ -0,0 +1,22 @@ +## @file=0D +#=0D +# Device tree description of the Marvell Armada 8040 DB platform=0D +#=0D +# Copyright (c) 2018, Marvell International Ltd. All rights reserved.=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x0001001A=0D + BASE_NAME =3D Armada80x0DbDeviceTree=0D + FILE_GUID =3D 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDef= aultDtbFileGuid=0D + MODULE_TYPE =3D USER_DEFINED=0D + VERSION_STRING =3D 1.0=0D +=0D +[Sources]=0D + armada-8040-db.dts=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf b/Si= licon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf new file mode 100644 index 0000000..540e1a7 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0McBin.inf @@ -0,0 +1,22 @@ +## @file=0D +#=0D +# Device tree description of the Marvell Armada 8040 MacchiatoBin platfor= m=0D +#=0D +# Copyright (c) 2018, Marvell International Ltd. All rights reserved.=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x0001001A=0D + BASE_NAME =3D Armada80x0McBinDeviceTree=0D + FILE_GUID =3D 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDef= aultDtbFileGuid=0D + MODULE_TYPE =3D USER_DEFINED=0D + VERSION_STRING =3D 1.0=0D +=0D +[Sources]=0D + armada-8040-mcbin.dts=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi b/Silic= on/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi new file mode 100644 index 0000000..e2edc26 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7020.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)=0D +/*=0D + * Copyright (C) 2016 Marvell Technology Group Ltd.=0D + *=0D + * Device Tree file for the Armada 7020 SoC, made of an AP806 Dual and=0D + * one CP110.=0D + */=0D +=0D +#include "armada-ap806-dual.dtsi"=0D +#include "armada-70x0.dtsi"=0D +=0D +/ {=0D + model =3D "Marvell Armada 7020";=0D + compatible =3D "marvell,armada7020", "marvell,armada-ap806-dual",= =0D + "marvell,armada-ap806";=0D +};=0D diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts b/Sil= icon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts new file mode 100644 index 0000000..f5878ef --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts @@ -0,0 +1,267 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)=0D +/*=0D + * Copyright (C) 2016 Marvell Technology Group Ltd.=0D + *=0D + * Device Tree file for Marvell Armada 7040 Development board platform=0D + */=0D +=0D +#include "armada-7040.dtsi"=0D +=0D +#define GPIO_ACTIVE_HIGH 0=0D +#define GPIO_ACTIVE_LOW 1=0D +=0D +/ {=0D + model =3D "Marvell Armada 7040 DB board";=0D + compatible =3D "marvell,armada7040-db", "marvell,armada7040",=0D + "marvell,armada-ap806-quad", "marvell,armada-ap806";= =0D +=0D + chosen {=0D + stdout-path =3D "serial0:115200n8";=0D + };=0D +=0D + memory@0 {=0D + device_type =3D "memory";=0D + reg =3D <0x0 0x0 0x0 0x80000000>;=0D + };=0D +=0D + aliases {=0D + ethernet0 =3D &cp0_eth0;=0D + ethernet1 =3D &cp0_eth1;=0D + ethernet2 =3D &cp0_eth2;=0D + };=0D +=0D + cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {=0D + compatible =3D "regulator-fixed";=0D + regulator-name =3D "usb3h0-vbus";=0D + regulator-min-microvolt =3D <5000000>;=0D + regulator-max-microvolt =3D <5000000>;=0D + enable-active-high;=0D + gpio =3D <&expander0 0 GPIO_ACTIVE_HIGH>;=0D + };=0D +=0D + cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {=0D + compatible =3D "regulator-fixed";=0D + regulator-name =3D "usb3h1-vbus";=0D + regulator-min-microvolt =3D <5000000>;=0D + regulator-max-microvolt =3D <5000000>;=0D + enable-active-high;=0D + gpio =3D <&expander0 1 GPIO_ACTIVE_HIGH>;=0D + };=0D +=0D + cp0_usb3_0_phy: cp0-usb3-0-phy {=0D + compatible =3D "usb-nop-xceiv";=0D + vcc-supply =3D <&cp0_reg_usb3_0_vbus>;=0D + };=0D +=0D + cp0_usb3_1_phy: cp0-usb3-1-phy {=0D + compatible =3D "usb-nop-xceiv";=0D + vcc-supply =3D <&cp0_reg_usb3_1_vbus>;=0D + };=0D +};=0D +=0D +&i2c0 {=0D + status =3D "okay";=0D + clock-frequency =3D <100000>;=0D +};=0D +=0D +&spi0 {=0D + status =3D "okay";=0D +=0D + spi-flash@0 {=0D + #address-cells =3D <1>;=0D + #size-cells =3D <1>;=0D + compatible =3D "jedec,spi-nor";=0D + reg =3D <0>;=0D + spi-max-frequency =3D <10000000>;=0D +=0D + partitions {=0D + compatible =3D "fixed-partitions";=0D + #address-cells =3D <1>;=0D + #size-cells =3D <1>;=0D +=0D + partition@0 {=0D + label =3D "U-Boot";=0D + reg =3D <0 0x200000>;=0D + };=0D + partition@400000 {=0D + label =3D "Filesystem";=0D + reg =3D <0x200000 0xce0000>;=0D + };=0D + };=0D + };=0D +};=0D +=0D +&uart0 {=0D + status =3D "okay";=0D + pinctrl-0 =3D <&uart0_pins>;=0D + pinctrl-names =3D "default";=0D +};=0D +=0D +=0D +&cp0_pcie2 {=0D + status =3D "okay";=0D +};=0D +=0D +&cp0_i2c0 {=0D + status =3D "okay";=0D + clock-frequency =3D <100000>;=0D +=0D + expander0: pca9555@21 {=0D + compatible =3D "nxp,pca9555";=0D + pinctrl-names =3D "default";=0D + gpio-controller;=0D + #gpio-cells =3D <2>;=0D + reg =3D <0x21>;=0D + /*=0D + * IO0_0: USB3_PWR_EN0 IO1_0: USB_3_1_Dev_Detect=0D + * IO0_1: USB3_PWR_EN1 IO1_1: USB2_1_current_limit= =0D + * IO0_2: DDR3_4_Detect IO1_2: Hcon_IO_RstN=0D + * IO0_3: USB2_DEVICE_DETECT=0D + * IO0_4: GPIO_0 IO1_4: SD_Status=0D + * IO0_5: GPIO_1 IO1_5: LDO_5V_Enable=0D + * IO0_6: IHB_5V_Enable IO1_6: PWR_EN_eMMC=0D + * IO0_7: IO1_7: SDIO_Vcntrl=0D + */=0D + };=0D +};=0D +=0D +&cp0_nand_controller {=0D + /*=0D + * SPI on CPM and NAND have common pins on this board. We can=0D + * use only one at a time. To enable the NAND (which will=0D + * disable the SPI), the "status =3D "okay";" line have to be=0D + * added here.=0D + */=0D + pinctrl-0 =3D <&nand_pins>, <&nand_rb>;=0D + pinctrl-names =3D "default";=0D +=0D + nand@0 {=0D + reg =3D <0>;=0D + label =3D "pxa3xx_nand-0";=0D + nand-rb =3D <0>;=0D + nand-on-flash-bbt;=0D + nand-ecc-strength =3D <4>;=0D + nand-ecc-step-size =3D <512>;=0D +=0D + partitions {=0D + compatible =3D "fixed-partitions";=0D + #address-cells =3D <1>;=0D + #size-cells =3D <1>;=0D +=0D + partition@0 {=0D + label =3D "U-Boot";=0D + reg =3D <0 0x200000>;=0D + };=0D +=0D + partition@200000 {=0D + label =3D "Linux";=0D + reg =3D <0x200000 0xe00000>;=0D + };=0D +=0D + partition@1000000 {=0D + label =3D "Filesystem";=0D + reg =3D <0x1000000 0x3f000000>;=0D + };=0D +=0D + };=0D + };=0D +};=0D +=0D +&cp0_spi1 {=0D + status =3D "disabled";=0D +=0D + spi-flash@0 {=0D + #address-cells =3D <0x1>;=0D + #size-cells =3D <0x1>;=0D + compatible =3D "jedec,spi-nor";=0D + reg =3D <0x0>;=0D + spi-max-frequency =3D <20000000>;=0D +=0D + partitions {=0D + compatible =3D "fixed-partitions";=0D + #address-cells =3D <1>;=0D + #size-cells =3D <1>;=0D +=0D + partition@0 {=0D + label =3D "U-Boot";=0D + reg =3D <0x0 0x200000>;=0D + };=0D +=0D + partition@400000 {=0D + label =3D "Filesystem";=0D + reg =3D <0x200000 0xe00000>;=0D + };=0D + };=0D + };=0D +};=0D +=0D +&cp0_sata0 {=0D + status =3D "okay";=0D +};=0D +=0D +&cp0_usb3_0 {=0D + usb-phy =3D <&cp0_usb3_0_phy>;=0D + status =3D "okay";=0D +};=0D +=0D +&cp0_usb3_1 {=0D + usb-phy =3D <&cp0_usb3_1_phy>;=0D + status =3D "okay";=0D +};=0D +=0D +&ap_sdhci0 {=0D + status =3D "okay";=0D + bus-width =3D <4>;=0D + no-1-8-v;=0D + non-removable;=0D +};=0D +=0D +&cp0_sdhci0 {=0D + status =3D "okay";=0D + bus-width =3D <4>;=0D + no-1-8-v;=0D + cd-gpios =3D <&expander0 12 GPIO_ACTIVE_LOW>;=0D +};=0D +=0D +&cp0_mdio {=0D + status =3D "okay";=0D +=0D + phy0: ethernet-phy@0 {=0D + reg =3D <0>;=0D + };=0D + phy1: ethernet-phy@1 {=0D + reg =3D <1>;=0D + };=0D +};=0D +=0D +&cp0_ethernet {=0D + status =3D "okay";=0D +};=0D +=0D +&cp0_eth0 {=0D + status =3D "okay";=0D + /* Network PHY */=0D + phy-mode =3D "10gbase-kr";=0D + /* Generic PHY, providing serdes lanes */=0D + phys =3D <&cp0_comphy2 0>;=0D +=0D + fixed-link {=0D + speed =3D <10000>;=0D + full-duplex;=0D + };=0D +};=0D +=0D +&cp0_eth1 {=0D + status =3D "okay";=0D + /* Network PHY */=0D + phy =3D <&phy0>;=0D + phy-mode =3D "sgmii";=0D + /* Generic PHY, providing serdes lanes */=0D + phys =3D <&cp0_comphy0 1>;=0D +};=0D +=0D +&cp0_eth2 {=0D + status =3D "okay";=0D + phy =3D <&phy1>;=0D + phy-mode =3D "rgmii-id";=0D +};=0D diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi b/Silic= on/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi new file mode 100644 index 0000000..03109b2 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)=0D +/*=0D + * Copyright (C) 2016 Marvell Technology Group Ltd.=0D + *=0D + * Device Tree file for the Armada 7040 SoC, made of an AP806 Quad and=0D + * one CP110.=0D + */=0D +=0D +#include "armada-ap806-quad.dtsi"=0D +#include "armada-70x0.dtsi"=0D +=0D +/ {=0D + model =3D "Marvell Armada 7040";=0D + compatible =3D "marvell,armada7040", "marvell,armada-ap806-quad",= =0D + "marvell,armada-ap806";=0D +};=0D diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi b/Silic= on/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi new file mode 100644 index 0000000..78f9d87 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)=0D +/*=0D + * Copyright (C) 2017 Marvell Technology Group Ltd.=0D + *=0D + * Device Tree file for the Armada 70x0 SoC=0D + */=0D +=0D +/ {=0D + aliases {=0D + gpio1 =3D &cp0_gpio1;=0D + gpio2 =3D &cp0_gpio2;=0D + spi1 =3D &cp0_spi0;=0D + spi2 =3D &cp0_spi1;=0D + };=0D +};=0D +=0D +/*=0D + * Instantiate the CP110=0D + */=0D +#define CP110_NAME cp0=0D +#define CP110_BASE f2000000=0D +#define CP110_PCIE_IO_BASE 0xf9000000=0D +#define CP110_PCIE_MEM_BASE 0xf6000000=0D +#define CP110_PCIE0_BASE f2600000=0D +#define CP110_PCIE1_BASE f2620000=0D +#define CP110_PCIE2_BASE f2640000=0D +=0D +#include "armada-cp110.dtsi"=0D +=0D +#undef CP110_NAME=0D +#undef CP110_BASE=0D +#undef CP110_PCIE_IO_BASE=0D +#undef CP110_PCIE_MEM_BASE=0D +#undef CP110_PCIE0_BASE=0D +#undef CP110_PCIE1_BASE=0D +#undef CP110_PCIE2_BASE=0D +=0D +&cp0_gpio1 {=0D + status =3D "okay";=0D +};=0D +=0D +&cp0_gpio2 {=0D + status =3D "okay";=0D +};=0D +=0D +&cp0_syscon0 {=0D + cp0_pinctrl: pinctrl {=0D + compatible =3D "marvell,armada-7k-pinctrl";=0D +=0D + nand_pins: nand-pins {=0D + marvell,pins =3D=0D + "mpp15", "mpp16", "mpp17", "mpp18",=0D + "mpp19", "mpp20", "mpp21", "mpp22",=0D + "mpp23", "mpp24", "mpp25", "mpp26",=0D + "mpp27";=0D + marvell,function =3D "dev";=0D + };=0D +=0D + nand_rb: nand-rb {=0D + marvell,pins =3D "mpp13";=0D + marvell,function =3D "nf";=0D + };=0D + };=0D +};=0D diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi b/Silic= on/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi new file mode 100644 index 0000000..5d76345 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8020.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)=0D +/*=0D + * Copyright (C) 2016 Marvell Technology Group Ltd.=0D + *=0D + * Device Tree file for the Armada 8020 SoC, made of an AP806 Dual and=0D + * two CP110.=0D + */=0D +=0D +#include "armada-ap806-dual.dtsi"=0D +#include "armada-80x0.dtsi"=0D +=0D +/ {=0D + model =3D "Marvell Armada 8020";=0D + compatible =3D "marvell,armada8020", "marvell,armada-ap806-dual",= =0D + "marvell,armada-ap806";=0D +};=0D +=0D +/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock= =0D + * in CP master is not connected (by package) to the oscillator. So=0D + * disable it. However, the RTC clock in CP slave is connected to the=0D + * oscillator so this one is let enabled.=0D + */=0D +=0D +&cp0_rtc {=0D + status =3D "disabled";=0D +};=0D diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts b/Sil= icon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts new file mode 100644 index 0000000..e813922 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts @@ -0,0 +1,336 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)=0D +/*=0D + * Copyright (C) 2016 Marvell Technology Group Ltd.=0D + *=0D + * Device Tree file for Marvell Armada 8040 Development board platform=0D + */=0D +=0D +#include "armada-8040.dtsi"=0D +=0D +#define GPIO_ACTIVE_HIGH 0=0D +#define GPIO_ACTIVE_LOW 1=0D +=0D +/ {=0D + model =3D "Marvell Armada 8040 DB board";=0D + compatible =3D "marvell,armada8040-db", "marvell,armada8040",=0D + "marvell,armada-ap806-quad", "marvell,armada-ap806";= =0D +=0D + chosen {=0D + stdout-path =3D "serial0:115200n8";=0D + };=0D +=0D + memory@0 {=0D + device_type =3D "memory";=0D + reg =3D <0x0 0x0 0x0 0x80000000>;=0D + };=0D +=0D + aliases {=0D + ethernet0 =3D &cp0_eth0;=0D + ethernet1 =3D &cp0_eth2;=0D + ethernet2 =3D &cp1_eth0;=0D + ethernet3 =3D &cp1_eth1;=0D + };=0D +=0D + cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {=0D + compatible =3D "regulator-fixed";=0D + regulator-name =3D "cp0-usb3h0-vbus";=0D + regulator-min-microvolt =3D <5000000>;=0D + regulator-max-microvolt =3D <5000000>;=0D + enable-active-high;=0D + gpio =3D <&expander0 0 GPIO_ACTIVE_HIGH>;=0D + };=0D +=0D + cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {=0D + compatible =3D "regulator-fixed";=0D + regulator-name =3D "cp0-usb3h1-vbus";=0D + regulator-min-microvolt =3D <5000000>;=0D + regulator-max-microvolt =3D <5000000>;=0D + enable-active-high;=0D + gpio =3D <&expander0 1 GPIO_ACTIVE_HIGH>;=0D + };=0D +=0D + cp0_usb3_0_phy: cp0-usb3-0-phy {=0D + compatible =3D "usb-nop-xceiv";=0D + vcc-supply =3D <&cp0_reg_usb3_0_vbus>;=0D + };=0D +=0D + cp0_usb3_1_phy: cp0-usb3-1-phy {=0D + compatible =3D "usb-nop-xceiv";=0D + vcc-supply =3D <&cp0_reg_usb3_1_vbus>;=0D + };=0D +=0D + cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus {=0D + compatible =3D "regulator-fixed";=0D + regulator-name =3D "cp1-usb3h0-vbus";=0D + regulator-min-microvolt =3D <5000000>;=0D + regulator-max-microvolt =3D <5000000>;=0D + enable-active-high;=0D + gpio =3D <&expander1 0 GPIO_ACTIVE_HIGH>;=0D + };=0D +=0D + cp1_usb3_0_phy: cp1-usb3-0-phy {=0D + compatible =3D "usb-nop-xceiv";=0D + vcc-supply =3D <&cp1_reg_usb3_0_vbus>;=0D + };=0D +};=0D +=0D +&i2c0 {=0D + status =3D "okay";=0D + clock-frequency =3D <100000>;=0D +};=0D +=0D +&spi0 {=0D + status =3D "okay";=0D +=0D + spi-flash@0 {=0D + #address-cells =3D <1>;=0D + #size-cells =3D <1>;=0D + compatible =3D "jedec,spi-nor";=0D + reg =3D <0>;=0D + spi-max-frequency =3D <10000000>;=0D +=0D + partitions {=0D + compatible =3D "fixed-partitions";=0D + #address-cells =3D <1>;=0D + #size-cells =3D <1>;=0D +=0D + partition@0 {=0D + label =3D "U-Boot";=0D + reg =3D <0 0x200000>;=0D + };=0D + partition@400000 {=0D + label =3D "Filesystem";=0D + reg =3D <0x200000 0xce0000>;=0D + };=0D + };=0D + };=0D +};=0D +=0D +/* Accessible over the mini-USB CON9 connector on the main board */=0D +&uart0 {=0D + status =3D "okay";=0D + pinctrl-0 =3D <&uart0_pins>;=0D + pinctrl-names =3D "default";=0D +};=0D +=0D +/* CON6 on CP0 expansion */=0D +&cp0_pcie0 {=0D + status =3D "okay";=0D +};=0D +=0D +/* CON5 on CP0 expansion */=0D +&cp0_pcie2 {=0D + status =3D "okay";=0D +};=0D +=0D +&cp0_i2c0 {=0D + status =3D "okay";=0D + clock-frequency =3D <100000>;=0D +=0D + /* U31 */=0D + expander0: pca9555@21 {=0D + compatible =3D "nxp,pca9555";=0D + pinctrl-names =3D "default";=0D + gpio-controller;=0D + #gpio-cells =3D <2>;=0D + reg =3D <0x21>;=0D + };=0D +=0D + /* U25 */=0D + expander1: pca9555@25 {=0D + compatible =3D "nxp,pca9555";=0D + pinctrl-names =3D "default";=0D + gpio-controller;=0D + #gpio-cells =3D <2>;=0D + reg =3D <0x25>;=0D + };=0D +=0D +};=0D +=0D +/* CON4 on CP0 expansion */=0D +&cp0_sata0 {=0D + status =3D "okay";=0D +};=0D +=0D +/* CON9 on CP0 expansion */=0D +&cp0_usb3_0 {=0D + usb-phy =3D <&cp0_usb3_0_phy>;=0D + status =3D "okay";=0D +};=0D +=0D +/* CON10 on CP0 expansion */=0D +&cp0_usb3_1 {=0D + usb-phy =3D <&cp0_usb3_1_phy>;=0D + status =3D "okay";=0D +};=0D +=0D +&cp0_mdio {=0D + status =3D "okay";=0D +=0D + phy1: ethernet-phy@1 {=0D + reg =3D <1>;=0D + };=0D +};=0D +=0D +&cp0_ethernet {=0D + status =3D "okay";=0D +};=0D +=0D +&cp0_eth0 {=0D + status =3D "okay";=0D + phy-mode =3D "10gbase-kr";=0D +=0D + fixed-link {=0D + speed =3D <10000>;=0D + full-duplex;=0D + };=0D +};=0D +=0D +&cp0_eth2 {=0D + status =3D "okay";=0D + phy =3D <&phy1>;=0D + phy-mode =3D "rgmii-id";=0D +};=0D +=0D +/* CON6 on CP1 expansion */=0D +&cp1_pcie0 {=0D + status =3D "okay";=0D +};=0D +=0D +/* CON7 on CP1 expansion */=0D +&cp1_pcie1 {=0D + status =3D "okay";=0D +};=0D +=0D +/* CON5 on CP1 expansion */=0D +&cp1_pcie2 {=0D + status =3D "okay";=0D +};=0D +=0D +&cp1_i2c0 {=0D + status =3D "okay";=0D + clock-frequency =3D <100000>;=0D +};=0D +=0D +&cp1_spi1 {=0D + status =3D "disabled";=0D +=0D + spi-flash@0 {=0D + #address-cells =3D <0x1>;=0D + #size-cells =3D <0x1>;=0D + compatible =3D "jedec,spi-nor";=0D + reg =3D <0x0>;=0D + spi-max-frequency =3D <20000000>;=0D +=0D + partitions {=0D + compatible =3D "fixed-partitions";=0D + #address-cells =3D <1>;=0D + #size-cells =3D <1>;=0D +=0D + partition@0 {=0D + label =3D "Boot";=0D + reg =3D <0x0 0x200000>;=0D + };=0D + partition@200000 {=0D + label =3D "Filesystem";=0D + reg =3D <0x200000 0xd00000>;=0D + };=0D + partition@f00000 {=0D + label =3D "Boot_2nd";=0D + reg =3D <0xf00000 0x100000>;=0D + };=0D + };=0D + };=0D +};=0D +=0D +/*=0D + * Proper NAND usage will require DPR-76 to be in position 1-2, which disa= bles=0D + * MDIO signal of CP1.=0D + */=0D +&cp1_nand_controller {=0D + pinctrl-0 =3D <&nand_pins>, <&nand_rb>;=0D + pinctrl-names =3D "default";=0D +=0D + nand@0 {=0D + reg =3D <0>;=0D + nand-rb =3D <0>;=0D + nand-on-flash-bbt;=0D + nand-ecc-strength =3D <4>;=0D + nand-ecc-step-size =3D <512>;=0D +=0D + partitions {=0D + compatible =3D "fixed-partitions";=0D + #address-cells =3D <1>;=0D + #size-cells =3D <1>;=0D +=0D + partition@0 {=0D + label =3D "U-Boot";=0D + reg =3D <0 0x200000>;=0D + };=0D + partition@200000 {=0D + label =3D "Linux";=0D + reg =3D <0x200000 0xe00000>;=0D + };=0D + partition@1000000 {=0D + label =3D "Filesystem";=0D + reg =3D <0x1000000 0x3f000000>;=0D + };=0D + };=0D + };=0D +};=0D +=0D +/* CON4 on CP1 expansion */=0D +&cp1_sata0 {=0D + status =3D "okay";=0D +};=0D +=0D +/* CON9 on CP1 expansion */=0D +&cp1_usb3_0 {=0D + usb-phy =3D <&cp1_usb3_0_phy>;=0D + status =3D "okay";=0D +};=0D +=0D +/* CON10 on CP1 expansion */=0D +&cp1_usb3_1 {=0D + status =3D "okay";=0D +};=0D +=0D +&cp1_mdio {=0D + status =3D "okay";=0D +=0D + phy0: ethernet-phy@0 {=0D + reg =3D <0>;=0D + };=0D +};=0D +=0D +&cp1_ethernet {=0D + status =3D "okay";=0D +};=0D +=0D +&cp1_eth0 {=0D + status =3D "okay";=0D + phy-mode =3D "10gbase-kr";=0D +=0D + fixed-link {=0D + speed =3D <10000>;=0D + full-duplex;=0D + };=0D +};=0D +=0D +&cp1_eth1 {=0D + status =3D "okay";=0D + phy =3D <&phy0>;=0D + phy-mode =3D "rgmii-id";=0D +};=0D +=0D +&ap_sdhci0 {=0D + status =3D "okay";=0D + bus-width =3D <4>;=0D + non-removable;=0D +};=0D +=0D +&cp0_sdhci0 {=0D + status =3D "okay";=0D + bus-width =3D <8>;=0D + non-removable;=0D +};=0D diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts b/= Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts new file mode 100644 index 0000000..d9c9348 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts @@ -0,0 +1,377 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)=0D +/*=0D + * Copyright (C) 2016 Marvell Technology Group Ltd.=0D + *=0D + * Device Tree file for MACCHIATOBin Armada 8040 community board platform= =0D + */=0D +=0D +#include "armada-8040.dtsi"=0D +=0D +#define GPIO_ACTIVE_HIGH 0=0D +#define GPIO_ACTIVE_LOW 1=0D +=0D +/ {=0D + model =3D "Marvell 8040 MACCHIATOBin";=0D + compatible =3D "marvell,armada8040-mcbin", "marvell,armada8040",=0D + "marvell,armada-ap806-quad", "marvell,armada-ap806= ";=0D +=0D + chosen {=0D + stdout-path =3D "serial0:115200n8";=0D + };=0D +=0D + memory@0 {=0D + device_type =3D "memory";=0D + reg =3D <0x0 0x0 0x0 0x80000000>;=0D + };=0D +=0D + aliases {=0D + ethernet0 =3D &cp0_eth0;=0D + ethernet1 =3D &cp1_eth0;=0D + ethernet2 =3D &cp1_eth1;=0D + ethernet3 =3D &cp1_eth2;=0D + };=0D +=0D + /* Regulator labels correspond with schematics */=0D + v_3_3: regulator-3-3v {=0D + compatible =3D "regulator-fixed";=0D + regulator-name =3D "v_3_3";=0D + regulator-min-microvolt =3D <3300000>;=0D + regulator-max-microvolt =3D <3300000>;=0D + regulator-always-on;=0D + status =3D "okay";=0D + };=0D +=0D + v_vddo_h: regulator-1-8v {=0D + compatible =3D "regulator-fixed";=0D + regulator-name =3D "v_vddo_h";=0D + regulator-min-microvolt =3D <1800000>;=0D + regulator-max-microvolt =3D <1800000>;=0D + regulator-always-on;=0D + status =3D "okay";=0D + };=0D +=0D + v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {=0D + compatible =3D "regulator-fixed";=0D + enable-active-high;=0D + gpio =3D <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>;=0D + pinctrl-names =3D "default";=0D + pinctrl-0 =3D <&cp0_xhci_vbus_pins>;=0D + regulator-name =3D "v_5v0_usb3_hst_vbus";=0D + regulator-min-microvolt =3D <5000000>;=0D + regulator-max-microvolt =3D <5000000>;=0D + status =3D "okay";=0D + };=0D +=0D + usb3h0_phy: usb3_phy0 {=0D + compatible =3D "usb-nop-xceiv";=0D + vcc-supply =3D <&v_5v0_usb3_hst_vbus>;=0D + };=0D +=0D + sfp_eth0: sfp-eth0 {=0D + /* CON15,16 - CPM lane 4 */=0D + compatible =3D "sff,sfp";=0D + i2c-bus =3D <&sfpp0_i2c>;=0D + los-gpio =3D <&cp1_gpio1 28 GPIO_ACTIVE_HIGH>;=0D + mod-def0-gpio =3D <&cp1_gpio1 27 GPIO_ACTIVE_LOW>;=0D + tx-disable-gpio =3D <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>;=0D + tx-fault-gpio =3D <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>;=0D + pinctrl-names =3D "default";=0D + pinctrl-0 =3D <&cp1_sfpp0_pins>;=0D + };=0D +=0D + sfp_eth1: sfp-eth1 {=0D + /* CON17,18 - CPS lane 4 */=0D + compatible =3D "sff,sfp";=0D + i2c-bus =3D <&sfpp1_i2c>;=0D + los-gpio =3D <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>;=0D + mod-def0-gpio =3D <&cp1_gpio1 11 GPIO_ACTIVE_LOW>;=0D + tx-disable-gpio =3D <&cp1_gpio1 10 GPIO_ACTIVE_HIGH>;=0D + tx-fault-gpio =3D <&cp0_gpio2 30 GPIO_ACTIVE_HIGH>;=0D + pinctrl-names =3D "default";=0D + pinctrl-0 =3D <&cp1_sfpp1_pins &cp0_sfpp1_pins>;=0D + };=0D +=0D + sfp_eth3: sfp-eth3 {=0D + /* CON3,4 - CPS lane 5 */=0D + compatible =3D "sff,sfp";=0D + i2c-bus =3D <&sfp_1g_i2c>;=0D + los-gpio =3D <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>;=0D + mod-def0-gpio =3D <&cp0_gpio2 21 GPIO_ACTIVE_LOW>;=0D + tx-disable-gpio =3D <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>;=0D + tx-fault-gpio =3D <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>;=0D + pinctrl-names =3D "default";=0D + pinctrl-0 =3D <&cp0_sfp_1g_pins &cp1_sfp_1g_pins>;=0D + };=0D +};=0D +=0D +&uart0 {=0D + status =3D "okay";=0D + pinctrl-0 =3D <&uart0_pins>;=0D + pinctrl-names =3D "default";=0D +};=0D +=0D +&ap_sdhci0 {=0D + bus-width =3D <8>;=0D + /*=0D + * Not stable in HS modes - phy needs "more calibration", so add=0D + * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes.=0D + */=0D + marvell,xenon-phy-slow-mode;=0D + no-1-8-v;=0D + no-sd;=0D + no-sdio;=0D + non-removable;=0D + status =3D "okay";=0D + vqmmc-supply =3D <&v_vddo_h>;=0D +};=0D +=0D +&cp0_i2c0 {=0D + clock-frequency =3D <100000>;=0D + pinctrl-names =3D "default";=0D + pinctrl-0 =3D <&cp0_i2c0_pins>;=0D + status =3D "okay";=0D +};=0D +=0D +&cp0_i2c1 {=0D + clock-frequency =3D <100000>;=0D + pinctrl-names =3D "default";=0D + pinctrl-0 =3D <&cp0_i2c1_pins>;=0D + status =3D "okay";=0D +=0D + i2c-switch@70 {=0D + compatible =3D "nxp,pca9548";=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + reg =3D <0x70>;=0D +=0D + sfpp0_i2c: i2c@0 {=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + reg =3D <0>;=0D + };=0D + sfpp1_i2c: i2c@1 {=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + reg =3D <1>;=0D + };=0D + sfp_1g_i2c: i2c@2 {=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + reg =3D <2>;=0D + };=0D + };=0D +};=0D +=0D +/* J25 UART header */=0D +&cp0_uart1 {=0D + pinctrl-names =3D "default";=0D + pinctrl-0 =3D <&cp0_uart1_pins>;=0D + status =3D "okay";=0D +};=0D +=0D +&cp0_mdio {=0D + pinctrl-names =3D "default";=0D + pinctrl-0 =3D <&cp0_ge_mdio_pins>;=0D + status =3D "okay";=0D +=0D + ge_phy: ethernet-phy@0 {=0D + reg =3D <0>;=0D + };=0D +};=0D +=0D +&cp0_pcie0 {=0D + compatible =3D "marvell,armada8k-pcie-ecam", "snps,dw-pcie-ecam";= =0D + reg =3D <0 0xe0000000 0 0xff00000>;=0D + bus-range =3D <0 0xfe>;=0D + pinctrl-names =3D "default";=0D + pinctrl-0 =3D <&cp0_pcie_pins>;=0D + num-lanes =3D <4>;=0D + num-viewport =3D <8>;=0D + reset-gpio =3D <&cp0_gpio1 20 GPIO_ACTIVE_LOW>;=0D + ranges =3D <0x1000000 0x0 0x00000000 0x0 0xeff00000 0x0 0x00010000= >,=0D + <0x2000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>,= =0D + <0x3000000 0x8 0x00000000 0x8 0x00000000 0x1 0x00000000>;= =0D + status =3D "okay";=0D +};=0D +=0D +&cp0_pinctrl {=0D + cp0_ge_mdio_pins: ge-mdio-pins {=0D + marvell,pins =3D "mpp32", "mpp34";=0D + marvell,function =3D "ge";=0D + };=0D + cp0_i2c1_pins: i2c1-pins {=0D + marvell,pins =3D "mpp35", "mpp36";=0D + marvell,function =3D "i2c1";=0D + };=0D + cp0_i2c0_pins: i2c0-pins {=0D + marvell,pins =3D "mpp37", "mpp38";=0D + marvell,function =3D "i2c0";=0D + };=0D + cp0_uart1_pins: uart1-pins {=0D + marvell,pins =3D "mpp40", "mpp41";=0D + marvell,function =3D "uart1";=0D + };=0D + cp0_xhci_vbus_pins: xhci0-vbus-pins {=0D + marvell,pins =3D "mpp47";=0D + marvell,function =3D "gpio";=0D + };=0D + cp0_sfp_1g_pins: sfp-1g-pins {=0D + marvell,pins =3D "mpp51", "mpp53", "mpp54";=0D + marvell,function =3D "gpio";=0D + };=0D + cp0_pcie_pins: pcie-pins {=0D + marvell,pins =3D "mpp52";=0D + marvell,function =3D "gpio";=0D + };=0D + cp0_sdhci_pins: sdhci-pins {=0D + marvell,pins =3D "mpp55", "mpp56", "mpp57", "mpp58", "mpp5= 9",=0D + "mpp60", "mpp61";=0D + marvell,function =3D "sdio";=0D + };=0D + cp0_sfpp1_pins: sfpp1-pins {=0D + marvell,pins =3D "mpp62";=0D + marvell,function =3D "gpio";=0D + };=0D +};=0D +=0D +&cp0_xmdio {=0D + status =3D "okay";=0D +=0D + phy0: ethernet-phy@0 {=0D + compatible =3D "ethernet-phy-ieee802.3-c45";=0D + reg =3D <0>;=0D + sfp =3D <&sfp_eth0>;=0D + };=0D +=0D + phy8: ethernet-phy@8 {=0D + compatible =3D "ethernet-phy-ieee802.3-c45";=0D + reg =3D <8>;=0D + sfp =3D <&sfp_eth1>;=0D + };=0D +};=0D +=0D +&cp0_ethernet {=0D + status =3D "okay";=0D +};=0D +=0D +&cp0_eth0 {=0D + status =3D "okay";=0D + /* Network PHY */=0D + phy =3D <&phy0>;=0D + phy-mode =3D "10gbase-kr";=0D + /* Generic PHY, providing serdes lanes */=0D + phys =3D <&cp0_comphy4 0>;=0D +};=0D +=0D +&cp0_sata0 {=0D + /* CPM Lane 0 - U29 */=0D + status =3D "okay";=0D +};=0D +=0D +&cp0_sdhci0 {=0D + /* U6 */=0D + broken-cd;=0D + bus-width =3D <4>;=0D + pinctrl-names =3D "default";=0D + pinctrl-0 =3D <&cp0_sdhci_pins>;=0D + status =3D "okay";=0D + vqmmc-supply =3D <&v_3_3>;=0D +};=0D +=0D +&cp0_usb3_0 {=0D + /* J38? - USB2.0 only */=0D + status =3D "okay";=0D +};=0D +=0D +&cp0_usb3_1 {=0D + /* J38? - USB2.0 only */=0D + status =3D "okay";=0D +};=0D +=0D +&cp1_ethernet {=0D + status =3D "okay";=0D +};=0D +=0D +&cp1_eth0 {=0D + status =3D "okay";=0D + /* Network PHY */=0D + phy =3D <&phy8>;=0D + phy-mode =3D "10gbase-kr";=0D + /* Generic PHY, providing serdes lanes */=0D + phys =3D <&cp1_comphy4 0>;=0D +};=0D +=0D +&cp1_eth1 {=0D + /* CPS Lane 0 - J5 (Gigabit RJ45) */=0D + status =3D "okay";=0D + /* Network PHY */=0D + phy =3D <&ge_phy>;=0D + phy-mode =3D "sgmii";=0D + /* Generic PHY, providing serdes lanes */=0D + phys =3D <&cp1_comphy0 1>;=0D +};=0D +=0D +&cp1_eth2 {=0D + /* CPS Lane 5 */=0D + status =3D "okay";=0D + /* Network PHY */=0D + phy-mode =3D "2500base-x";=0D + managed =3D "in-band-status";=0D + /* Generic PHY, providing serdes lanes */=0D + phys =3D <&cp1_comphy5 2>;=0D + sfp =3D <&sfp_eth3>;=0D +};=0D +=0D +&cp1_pinctrl {=0D + cp1_sfpp1_pins: sfpp1-pins {=0D + marvell,pins =3D "mpp8", "mpp10", "mpp11";=0D + marvell,function =3D "gpio";=0D + };=0D + cp1_spi1_pins: spi1-pins {=0D + marvell,pins =3D "mpp12", "mpp13", "mpp14", "mpp15", "mpp1= 6";=0D + marvell,function =3D "spi1";=0D + };=0D + cp1_uart0_pins: uart0-pins {=0D + marvell,pins =3D "mpp6", "mpp7";=0D + marvell,function =3D "uart0";=0D + };=0D + cp1_sfp_1g_pins: sfp-1g-pins {=0D + marvell,pins =3D "mpp24";=0D + marvell,function =3D "gpio";=0D + };=0D + cp1_sfpp0_pins: sfpp0-pins {=0D + marvell,pins =3D "mpp26", "mpp27", "mpp28", "mpp29";=0D + marvell,function =3D "gpio";=0D + };=0D +};=0D +=0D +/* J27 UART header */=0D +&cp1_uart0 {=0D + pinctrl-names =3D "default";=0D + pinctrl-0 =3D <&cp1_uart0_pins>;=0D + status =3D "okay";=0D +};=0D +=0D +&cp1_sata0 {=0D + /* CPS Lane 1 - U32 */=0D + /* CPS Lane 3 - U31 */=0D + status =3D "okay";=0D +};=0D +=0D +&cp1_spi1 {=0D + pinctrl-names =3D "default";=0D + pinctrl-0 =3D <&cp1_spi1_pins>;=0D + status =3D "disabled";=0D +=0D + spi-flash@0 {=0D + compatible =3D "st,w25q32";=0D + spi-max-frequency =3D <50000000>;=0D + reg =3D <0>;=0D + };=0D +};=0D +=0D +&cp1_usb3_0 {=0D + /* CPS Lane 2 - CON7 */=0D + usb-phy =3D <&usb3h0_phy>;=0D + status =3D "okay";=0D +};=0D diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi b/Silic= on/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi new file mode 100644 index 0000000..784ef3f --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)=0D +/*=0D + * Copyright (C) 2016 Marvell Technology Group Ltd.=0D + *=0D + * Device Tree file for the Armada 8040 SoC, made of an AP806 Quad and=0D + * two CP110.=0D + */=0D +=0D +#include "armada-ap806-quad.dtsi"=0D +#include "armada-80x0.dtsi"=0D +=0D +/ {=0D + model =3D "Marvell Armada 8040";=0D + compatible =3D "marvell,armada8040", "marvell,armada-ap806-quad",= =0D + "marvell,armada-ap806";=0D +};=0D +=0D +/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock= =0D + * in CP master is not connected (by package) to the oscillator. So=0D + * disable it. However, the RTC clock in CP slave is connected to the=0D + * oscillator so this one is let enabled.=0D + */=0D +&cp0_rtc {=0D + status =3D "disabled";=0D +};=0D diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi b/Silic= on/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi new file mode 100644 index 0000000..81967e2 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)=0D +/*=0D + * Copyright (C) 2017 Marvell Technology Group Ltd.=0D + *=0D + * Device Tree file for the Armada 80x0 SoC family=0D + */=0D +=0D +/ {=0D + aliases {=0D + gpio1 =3D &cp1_gpio1;=0D + gpio2 =3D &cp0_gpio2;=0D + spi1 =3D &cp0_spi0;=0D + spi2 =3D &cp0_spi1;=0D + spi3 =3D &cp1_spi0;=0D + spi4 =3D &cp1_spi1;=0D + };=0D +};=0D +=0D +/*=0D + * Instantiate the master CP110=0D + */=0D +#define CP110_NAME cp0=0D +#define CP110_BASE f2000000=0D +#define CP110_PCIE_IO_BASE 0xf9000000=0D +#define CP110_PCIE_MEM_BASE 0xf6000000=0D +#define CP110_PCIE0_BASE f2600000=0D +#define CP110_PCIE1_BASE f2620000=0D +#define CP110_PCIE2_BASE f2640000=0D +=0D +#include "armada-cp110.dtsi"=0D +=0D +#undef CP110_NAME=0D +#undef CP110_BASE=0D +#undef CP110_PCIE_IO_BASE=0D +#undef CP110_PCIE_MEM_BASE=0D +#undef CP110_PCIE0_BASE=0D +#undef CP110_PCIE1_BASE=0D +#undef CP110_PCIE2_BASE=0D +=0D +/*=0D + * Instantiate the slave CP110=0D + */=0D +#define CP110_NAME cp1=0D +#define CP110_BASE f4000000=0D +#define CP110_PCIE_IO_BASE 0xfd000000=0D +#define CP110_PCIE_MEM_BASE 0xfa000000=0D +#define CP110_PCIE0_BASE f4600000=0D +#define CP110_PCIE1_BASE f4620000=0D +#define CP110_PCIE2_BASE f4640000=0D +=0D +#include "armada-cp110.dtsi"=0D +=0D +#undef CP110_NAME=0D +#undef CP110_BASE=0D +#undef CP110_PCIE_IO_BASE=0D +#undef CP110_PCIE_MEM_BASE=0D +#undef CP110_PCIE0_BASE=0D +#undef CP110_PCIE1_BASE=0D +#undef CP110_PCIE2_BASE=0D +=0D +/* The 80x0 has two CP blocks, but uses only one block from each. */=0D +&cp1_gpio1 {=0D + status =3D "okay";=0D +};=0D +=0D +&cp0_gpio2 {=0D + status =3D "okay";=0D +};=0D +=0D +&cp0_syscon0 {=0D + cp0_pinctrl: pinctrl {=0D + compatible =3D "marvell,armada-8k-cpm-pinctrl";=0D + };=0D +};=0D +=0D +&cp1_syscon0 {=0D + cp1_pinctrl: pinctrl {=0D + compatible =3D "marvell,armada-8k-cps-pinctrl";=0D +=0D + nand_pins: nand-pins {=0D + marvell,pins =3D=0D + "mpp0", "mpp1", "mpp2", "mpp3",=0D + "mpp4", "mpp5", "mpp6", "mpp7",=0D + "mpp8", "mpp9", "mpp10", "mpp11",=0D + "mpp15", "mpp16", "mpp17", "mpp18",=0D + "mpp19", "mpp20", "mpp21", "mpp22",=0D + "mpp23", "mpp24", "mpp25", "mpp26",=0D + "mpp27";=0D + marvell,function =3D "dev";=0D + };=0D +=0D + nand_rb: nand-rb {=0D + marvell,pins =3D "mpp13", "mpp12";=0D + marvell,function =3D "nf";=0D + };=0D + };=0D +};=0D +=0D +&cp1_crypto {=0D + /*=0D + * The cryptographic engine found on the cp110=0D + * master is enabled by default at the SoC=0D + * level. Because it is not possible as of now=0D + * to enable two cryptographic engines in=0D + * parallel, disable this one by default.=0D + */=0D + status =3D "disabled";=0D +};=0D diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi b= /Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi new file mode 100644 index 0000000..5985843 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)=0D +/*=0D + * Copyright (C) 2016 Marvell Technology Group Ltd.=0D + *=0D + * Device Tree file for Marvell Armada AP806.=0D + */=0D +=0D +#include "armada-ap806.dtsi"=0D +=0D +/ {=0D + model =3D "Marvell Armada AP806 Dual";=0D + compatible =3D "marvell,armada-ap806-dual", "marvell,armada-ap806"= ;=0D +=0D + cpus {=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D +=0D + cpu@0 {=0D + device_type =3D "cpu";=0D + compatible =3D "arm,cortex-a72", "arm,armv8";=0D + reg =3D <0x000>;=0D + enable-method =3D "psci";=0D + };=0D + cpu@1 {=0D + device_type =3D "cpu";=0D + compatible =3D "arm,cortex-a72", "arm,armv8";=0D + reg =3D <0x001>;=0D + enable-method =3D "psci";=0D + };=0D + };=0D +};=0D diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi b= /Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi new file mode 100644 index 0000000..bae0ed9 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)=0D +/*=0D + * Copyright (C) 2016 Marvell Technology Group Ltd.=0D + *=0D + * Device Tree file for Marvell Armada AP806.=0D + */=0D +=0D +#include "armada-ap806.dtsi"=0D +=0D +/ {=0D + model =3D "Marvell Armada AP806 Quad";=0D + compatible =3D "marvell,armada-ap806-quad", "marvell,armada-ap806"= ;=0D +=0D + cpus {=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D +=0D + cpu@0 {=0D + device_type =3D "cpu";=0D + compatible =3D "arm,cortex-a72", "arm,armv8";=0D + reg =3D <0x000>;=0D + enable-method =3D "psci";=0D + };=0D + cpu@1 {=0D + device_type =3D "cpu";=0D + compatible =3D "arm,cortex-a72", "arm,armv8";=0D + reg =3D <0x001>;=0D + enable-method =3D "psci";=0D + };=0D + cpu@100 {=0D + device_type =3D "cpu";=0D + compatible =3D "arm,cortex-a72", "arm,armv8";=0D + reg =3D <0x100>;=0D + enable-method =3D "psci";=0D + };=0D + cpu@101 {=0D + device_type =3D "cpu";=0D + compatible =3D "arm,cortex-a72", "arm,armv8";=0D + reg =3D <0x101>;=0D + enable-method =3D "psci";=0D + };=0D + };=0D +};=0D diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi b/Sili= con/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi new file mode 100644 index 0000000..66124bf --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi @@ -0,0 +1,264 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)=0D +/*=0D + * Copyright (C) 2016 Marvell Technology Group Ltd.=0D + *=0D + * Device Tree file for Marvell Armada AP806.=0D + */=0D +=0D +#define IRQ_TYPE_LEVEL_HIGH (1 << 2)=0D +#define IRQ_TYPE_LEVEL_LOW (1 << 3)=0D +=0D +#define GIC_SPI 0=0D +#define GIC_PPI 1=0D +=0D +#define GIC_CPU_MASK_RAW(x) ((x) << 8)=0D +#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1)=0D +=0D +/dts-v1/;=0D +=0D +/ {=0D + model =3D "Marvell Armada AP806";=0D + compatible =3D "marvell,armada-ap806";=0D + #address-cells =3D <2>;=0D + #size-cells =3D <2>;=0D +=0D + aliases {=0D + serial0 =3D &uart0;=0D + serial1 =3D &uart1;=0D + gpio0 =3D &ap_gpio;=0D + spi0 =3D &spi0;=0D + };=0D +=0D + psci {=0D + compatible =3D "arm,psci-0.2";=0D + method =3D "smc";=0D + };=0D +=0D + ap806 {=0D + #address-cells =3D <2>;=0D + #size-cells =3D <2>;=0D + compatible =3D "simple-bus";=0D + interrupt-parent =3D <&gic>;=0D + ranges;=0D +=0D + config-space@f0000000 {=0D + #address-cells =3D <1>;=0D + #size-cells =3D <1>;=0D + compatible =3D "simple-bus";=0D + ranges =3D <0x0 0x0 0xf0000000 0x1000000>;=0D +=0D + gic: interrupt-controller@210000 {=0D + compatible =3D "arm,gic-400";=0D + #interrupt-cells =3D <3>;=0D + #address-cells =3D <1>;=0D + #size-cells =3D <1>;=0D + ranges;=0D + interrupt-controller;=0D + interrupts =3D ;=0D + reg =3D <0x210000 0x10000>,=0D + <0x220000 0x20000>,=0D + <0x240000 0x20000>,=0D + <0x260000 0x20000>;=0D +=0D + gic_v2m0: v2m@280000 {=0D + compatible =3D "arm,gic-v2m-frame"= ;=0D + msi-controller;=0D + reg =3D <0x280000 0x1000>;=0D + arm,msi-base-spi =3D <160>;=0D + arm,msi-num-spis =3D <32>;=0D + };=0D + gic_v2m1: v2m@290000 {=0D + compatible =3D "arm,gic-v2m-frame"= ;=0D + msi-controller;=0D + reg =3D <0x290000 0x1000>;=0D + arm,msi-base-spi =3D <192>;=0D + arm,msi-num-spis =3D <32>;=0D + };=0D + gic_v2m2: v2m@2a0000 {=0D + compatible =3D "arm,gic-v2m-frame"= ;=0D + msi-controller;=0D + reg =3D <0x2a0000 0x1000>;=0D + arm,msi-base-spi =3D <224>;=0D + arm,msi-num-spis =3D <32>;=0D + };=0D + gic_v2m3: v2m@2b0000 {=0D + compatible =3D "arm,gic-v2m-frame"= ;=0D + msi-controller;=0D + reg =3D <0x2b0000 0x1000>;=0D + arm,msi-base-spi =3D <256>;=0D + arm,msi-num-spis =3D <32>;=0D + };=0D + };=0D +=0D + timer {=0D + compatible =3D "arm,armv8-timer";=0D + interrupts =3D ,=0D + ,=0D + ,=0D + ;=0D + };=0D +=0D + pmu {=0D + compatible =3D "arm,cortex-a72-pmu";=0D + interrupt-parent =3D <&pic>;=0D + interrupts =3D <17>;=0D + };=0D +=0D + odmi: odmi@300000 {=0D + compatible =3D "marvell,odmi-controller";= =0D + interrupt-controller;=0D + msi-controller;=0D + marvell,odmi-frames =3D <4>;=0D + reg =3D <0x300000 0x4000>,=0D + <0x304000 0x4000>,=0D + <0x308000 0x4000>,=0D + <0x30C000 0x4000>;=0D + marvell,spi-base =3D <128>, <136>, <144>, = <152>;=0D + };=0D +=0D + gicp: gicp@3f0040 {=0D + compatible =3D "marvell,ap806-gicp";=0D + reg =3D <0x3f0040 0x10>;=0D + marvell,spi-ranges =3D <64 64>, <288 64>;= =0D + msi-controller;=0D + };=0D +=0D + pic: interrupt-controller@3f0100 {=0D + compatible =3D "marvell,armada-8k-pic";=0D + reg =3D <0x3f0100 0x10>;=0D + #interrupt-cells =3D <1>;=0D + interrupt-controller;=0D + interrupts =3D ;=0D + };=0D +=0D + xor@400000 {=0D + compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2";=0D + reg =3D <0x400000 0x1000>,=0D + <0x410000 0x1000>;=0D + msi-parent =3D <&gic_v2m0>;=0D + clocks =3D <&ap_clk 3>;=0D + dma-coherent;=0D + };=0D +=0D + xor@420000 {=0D + compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2";=0D + reg =3D <0x420000 0x1000>,=0D + <0x430000 0x1000>;=0D + msi-parent =3D <&gic_v2m0>;=0D + clocks =3D <&ap_clk 3>;=0D + dma-coherent;=0D + };=0D +=0D + xor@440000 {=0D + compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2";=0D + reg =3D <0x440000 0x1000>,=0D + <0x450000 0x1000>;=0D + msi-parent =3D <&gic_v2m0>;=0D + clocks =3D <&ap_clk 3>;=0D + dma-coherent;=0D + };=0D +=0D + xor@460000 {=0D + compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2";=0D + reg =3D <0x460000 0x1000>,=0D + <0x470000 0x1000>;=0D + msi-parent =3D <&gic_v2m0>;=0D + clocks =3D <&ap_clk 3>;=0D + dma-coherent;=0D + };=0D +=0D + spi0: spi@510600 {=0D + compatible =3D "marvell,armada-380-spi";=0D + reg =3D <0x510600 0x50>;=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + interrupts =3D ;=0D + clocks =3D <&ap_clk 3>;=0D + status =3D "disabled";=0D + };=0D +=0D + i2c0: i2c@511000 {=0D + compatible =3D "marvell,mv78230-i2c";=0D + reg =3D <0x511000 0x20>;=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + interrupts =3D ;=0D + timeout-ms =3D <1000>;=0D + clocks =3D <&ap_clk 3>;=0D + status =3D "disabled";=0D + };=0D +=0D + uart0: serial@512000 {=0D + compatible =3D "snps,dw-apb-uart";=0D + reg =3D <0x512000 0x100>;=0D + reg-shift =3D <2>;=0D + interrupts =3D ;=0D + reg-io-width =3D <1>;=0D + clocks =3D <&ap_clk 3>;=0D + status =3D "disabled";=0D + };=0D +=0D + uart1: serial@512100 {=0D + compatible =3D "snps,dw-apb-uart";=0D + reg =3D <0x512100 0x100>;=0D + reg-shift =3D <2>;=0D + interrupts =3D ;=0D + reg-io-width =3D <1>;=0D + clocks =3D <&ap_clk 3>;=0D + status =3D "disabled";=0D +=0D + };=0D +=0D + watchdog: watchdog@610000 {=0D + compatible =3D "arm,sbsa-gwdt";=0D + reg =3D <0x610000 0x1000>, <0x600000 0x100= 0>;=0D + interrupts =3D ;=0D + };=0D +=0D + ap_sdhci0: sdhci@6e0000 {=0D + compatible =3D "marvell,armada-ap806-sdhci= ";=0D + reg =3D <0x6e0000 0x300>;=0D + interrupts =3D ;=0D + clock-names =3D "core";=0D + clocks =3D <&ap_clk 4>;=0D + dma-coherent;=0D + marvell,xenon-phy-slow-mode;=0D + status =3D "disabled";=0D + };=0D +=0D + ap_syscon: system-controller@6f4000 {=0D + compatible =3D "syscon", "simple-mfd";=0D + reg =3D <0x6f4000 0x2000>;=0D +=0D + ap_clk: clock {=0D + compatible =3D "marvell,ap806-cloc= k";=0D + #clock-cells =3D <1>;=0D + };=0D +=0D + ap_pinctrl: pinctrl {=0D + compatible =3D "marvell,ap806-pinc= trl";=0D +=0D + uart0_pins: uart0-pins {=0D + marvell,pins =3D "mpp11", = "mpp19";=0D + marvell,function =3D "uart= 0";=0D + };=0D + };=0D +=0D + ap_gpio: gpio@1040 {=0D + compatible =3D "marvell,armada-8k-= gpio";=0D + offset =3D <0x1040>;=0D + ngpios =3D <20>;=0D + gpio-controller;=0D + #gpio-cells =3D <2>;=0D + gpio-ranges =3D <&ap_pinctrl 0 0 2= 0>;=0D + };=0D + };=0D +=0D + ap_thermal: thermal@6f808c {=0D + compatible =3D "marvell,armada-ap806-therm= al";=0D + reg =3D <0x6f808c 0x4>,=0D + <0x6f8084 0x8>;=0D + };=0D + };=0D + };=0D +};=0D diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi b/Sil= icon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi new file mode 100644 index 0000000..8b610fd --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)=0D +/*=0D + * Copyright (C) 2016 Marvell Technology Group Ltd.=0D + */=0D +=0D +/* Common definitions used by Armada 7K/8K DTs */=0D +#define PASTER(x, y) x ## y=0D +#define EVALUATOR(x, y) PASTER(x, y)=0D +#define CP110_LABEL(name) EVALUATOR(CP110_NAME, EVALUATOR(_, name))=0D +#define ADDRESSIFY(addr) EVALUATOR(0x, addr)=0D diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi b/Sili= con/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi new file mode 100644 index 0000000..5e8e524 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi @@ -0,0 +1,560 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)=0D +/*=0D + * Copyright (C) 2016 Marvell Technology Group Ltd.=0D + *=0D + * Device Tree file for Marvell Armada CP110.=0D + */=0D +=0D +#include "armada-common.dtsi"=0D +=0D +#define ICU_GRP_NSR 0x0=0D +#define ICU_GRP_SR 0x1=0D +#define ICU_GRP_SEI 0x4=0D +#define ICU_GRP_REI 0x5=0D +=0D +#define CP110_PCIEx_IO_BASE(iface) (CP110_PCIE_IO_BASE + (iface * = 0x10000))=0D +#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIE_MEM_BASE + (iface *= 0x1000000))=0D +#define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) += 0xf00000)=0D +=0D +/ {=0D + /*=0D + * The contents of the node are defined below, in order to=0D + * save one indentation level=0D + */=0D + CP110_NAME: CP110_NAME { };=0D +};=0D +=0D +&CP110_NAME {=0D + #address-cells =3D <2>;=0D + #size-cells =3D <2>;=0D + compatible =3D "simple-bus";=0D + interrupt-parent =3D <&CP110_LABEL(icu)>;=0D + ranges;=0D +=0D + config-space@CP110_BASE {=0D + #address-cells =3D <1>;=0D + #size-cells =3D <1>;=0D + compatible =3D "simple-bus";=0D + ranges =3D <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>;=0D +=0D + CP110_LABEL(ethernet): ethernet@0 {=0D + compatible =3D "marvell,armada-7k-pp22";=0D + reg =3D <0x0 0x100000>, <0x129000 0xb000>;=0D + clocks =3D <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL= (ppv2_clk)>,=0D + <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL(c= ore_clk)>,=0D + <&CP110_LABEL(core_clk)>;=0D + clock-names =3D "pp_clk", "gop_clk",=0D + "mg_clk", "mg_core_clk", "axi_clk";= =0D + marvell,system-controller =3D <&CP110_LABEL(syscon= 0)>;=0D + status =3D "disabled";=0D + dma-coherent;=0D +=0D + CP110_LABEL(eth0): eth0 {=0D + interrupts =3D ,=0D + ,=0D + ,=0D + ,=0D + ,=0D + ;=0D + interrupt-names =3D "tx-cpu0", "tx-cpu1", = "tx-cpu2",=0D + "tx-cpu3", "rx-shared", "link";=0D + port-id =3D <0>;=0D + gop-port-id =3D <0>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP110_LABEL(eth1): eth1 {=0D + interrupts =3D ,=0D + ,=0D + ,=0D + ,=0D + ,=0D + ;=0D + interrupt-names =3D "tx-cpu0", "tx-cpu1", = "tx-cpu2",=0D + "tx-cpu3", "rx-shared", "link";=0D + port-id =3D <1>;=0D + gop-port-id =3D <2>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP110_LABEL(eth2): eth2 {=0D + interrupts =3D ,=0D + ,=0D + ,=0D + ,=0D + ,=0D + ;=0D + interrupt-names =3D "tx-cpu0", "tx-cpu1", = "tx-cpu2",=0D + "tx-cpu3", "rx-shared", "link";=0D + port-id =3D <2>;=0D + gop-port-id =3D <3>;=0D + status =3D "disabled";=0D + };=0D + };=0D +=0D + CP110_LABEL(comphy): phy@120000 {=0D + compatible =3D "marvell,comphy-cp110";=0D + reg =3D <0x120000 0x6000>;=0D + marvell,system-controller =3D <&CP110_LABEL(syscon= 0)>;=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D +=0D + CP110_LABEL(comphy0): phy@0 {=0D + reg =3D <0>;=0D + #phy-cells =3D <1>;=0D + };=0D +=0D + CP110_LABEL(comphy1): phy@1 {=0D + reg =3D <1>;=0D + #phy-cells =3D <1>;=0D + };=0D +=0D + CP110_LABEL(comphy2): phy@2 {=0D + reg =3D <2>;=0D + #phy-cells =3D <1>;=0D + };=0D +=0D + CP110_LABEL(comphy3): phy@3 {=0D + reg =3D <3>;=0D + #phy-cells =3D <1>;=0D + };=0D +=0D + CP110_LABEL(comphy4): phy@4 {=0D + reg =3D <4>;=0D + #phy-cells =3D <1>;=0D + };=0D +=0D + CP110_LABEL(comphy5): phy@5 {=0D + reg =3D <5>;=0D + #phy-cells =3D <1>;=0D + };=0D + };=0D +=0D + CP110_LABEL(mdio): mdio@12a200 {=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + compatible =3D "marvell,orion-mdio";=0D + reg =3D <0x12a200 0x10>;=0D + clocks =3D <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL= (ppv2_clk)>,=0D + <&CP110_LABEL(core_clk)>, <&CP110_LABEL(c= ore_clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP110_LABEL(xmdio): mdio@12a600 {=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + compatible =3D "marvell,xmdio";=0D + reg =3D <0x12a600 0x10>;=0D + clocks =3D <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL= (ppv2_clk)>,=0D + <&CP110_LABEL(core_clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP110_LABEL(icu): interrupt-controller@1e0000 {=0D + compatible =3D "marvell,cp110-icu";=0D + reg =3D <0x1e0000 0x440>;=0D + #interrupt-cells =3D <3>;=0D + interrupt-controller;=0D + msi-parent =3D <&gicp>;=0D + };=0D +=0D + CP110_LABEL(rtc): rtc@284000 {=0D + compatible =3D "marvell,armada-8k-rtc";=0D + reg =3D <0x284000 0x20>, <0x284080 0x24>;=0D + reg-names =3D "rtc", "rtc-soc";=0D + interrupts =3D ;=0D + status =3D "disabled";=0D + };=0D +=0D + CP110_LABEL(thermal): thermal@400078 {=0D + compatible =3D "marvell,armada-cp110-thermal";=0D + reg =3D <0x400078 0x4>,=0D + <0x400070 0x8>;=0D + };=0D +=0D + CP110_LABEL(syscon0): system-controller@440000 {=0D + compatible =3D "syscon", "simple-mfd";=0D + reg =3D <0x440000 0x2000>;=0D +=0D + CP110_LABEL(clk): clock {=0D + compatible =3D "marvell,cp110-clock";=0D + status =3D "disabled";=0D + #clock-cells =3D <2>;=0D + };=0D +=0D + CP110_LABEL(gpio1): gpio@100 {=0D + compatible =3D "marvell,armada-8k-gpio";=0D + offset =3D <0x100>;=0D + ngpios =3D <32>;=0D + gpio-controller;=0D + #gpio-cells =3D <2>;=0D + gpio-ranges =3D <&CP110_LABEL(pinctrl) 0 0= 32>;=0D + interrupt-controller;=0D + interrupts =3D ,=0D + ,=0D + ,=0D + ;=0D + status =3D "disabled";=0D + };=0D +=0D + CP110_LABEL(gpio2): gpio@140 {=0D + compatible =3D "marvell,armada-8k-gpio";=0D + offset =3D <0x140>;=0D + ngpios =3D <31>;=0D + gpio-controller;=0D + #gpio-cells =3D <2>;=0D + gpio-ranges =3D <&CP110_LABEL(pinctrl) 0 3= 2 31>;=0D + interrupt-controller;=0D + interrupts =3D ,=0D + ,=0D + ,=0D + ;=0D + status =3D "disabled";=0D + };=0D + };=0D +=0D + CP110_LABEL(usb3_0): usb3@500000 {=0D + compatible =3D "marvell,armada-8k-xhci",=0D + "generic-xhci";=0D + reg =3D <0x500000 0x4000>;=0D + dma-coherent;=0D + interrupts =3D ;=0D + clock-names =3D "core", "reg";=0D + clocks =3D <&CP110_LABEL(core_clk)>,=0D + <&CP110_LABEL(core_clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP110_LABEL(usb3_1): usb3@510000 {=0D + compatible =3D "marvell,armada-8k-xhci",=0D + "generic-xhci";=0D + reg =3D <0x510000 0x4000>;=0D + dma-coherent;=0D + interrupts =3D ;=0D + clock-names =3D "core", "reg";=0D + clocks =3D <&CP110_LABEL(core_clk)>,=0D + <&CP110_LABEL(core_clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP110_LABEL(sata0): sata@540000 {=0D + compatible =3D "marvell,armada-8k-ahci",=0D + "generic-ahci";=0D + reg =3D <0x540000 0x30000>;=0D + dma-coherent;=0D + interrupts =3D ;=0D + clocks =3D <&CP110_LABEL(core_clk)>,=0D + <&CP110_LABEL(core_clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP110_LABEL(xor0): xor@6a0000 {=0D + compatible =3D "marvell,armada-7k-xor", "marvell,x= or-v2";=0D + reg =3D <0x6a0000 0x1000>, <0x6b0000 0x1000>;=0D + dma-coherent;=0D + msi-parent =3D <&gic_v2m0>;=0D + clock-names =3D "core", "reg";=0D + clocks =3D <&CP110_LABEL(core_clk)>,=0D + <&CP110_LABEL(x2core_clk)>;=0D + };=0D +=0D + CP110_LABEL(xor1): xor@6c0000 {=0D + compatible =3D "marvell,armada-7k-xor", "marvell,x= or-v2";=0D + reg =3D <0x6c0000 0x1000>, <0x6d0000 0x1000>;=0D + dma-coherent;=0D + msi-parent =3D <&gic_v2m0>;=0D + clock-names =3D "core", "reg";=0D + clocks =3D <&CP110_LABEL(core_clk)>,=0D + <&CP110_LABEL(x2core_clk)>;=0D + };=0D +=0D + CP110_LABEL(spi0): spi@700600 {=0D + compatible =3D "marvell,armada-380-spi";=0D + reg =3D <0x700600 0x50>;=0D + #address-cells =3D <0x1>;=0D + #size-cells =3D <0x0>;=0D + clock-names =3D "core", "axi";=0D + clocks =3D <&CP110_LABEL(slow_io_clk)>,=0D + <&CP110_LABEL(x2core_clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP110_LABEL(spi1): spi@700680 {=0D + compatible =3D "marvell,armada-380-spi";=0D + reg =3D <0x700680 0x50>;=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + clock-names =3D "core", "axi";=0D + clocks =3D <&CP110_LABEL(slow_io_clk)>,=0D + <&CP110_LABEL(x2core_clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP110_LABEL(i2c0): i2c@701000 {=0D + compatible =3D "marvell,mv78230-i2c";=0D + reg =3D <0x701000 0x20>;=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + interrupts =3D ;=0D + clock-names =3D "core", "reg";=0D + clocks =3D <&CP110_LABEL(slow_io_clk)>,=0D + <&CP110_LABEL(x2core_clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP110_LABEL(i2c1): i2c@701100 {=0D + compatible =3D "marvell,mv78230-i2c";=0D + reg =3D <0x701100 0x20>;=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + interrupts =3D ;=0D + clock-names =3D "core", "reg";=0D + clocks =3D <&CP110_LABEL(slow_io_clk)>,=0D + <&CP110_LABEL(x2core_clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP110_LABEL(uart0): serial@702000 {=0D + compatible =3D "snps,dw-apb-uart";=0D + reg =3D <0x702000 0x100>;=0D + reg-shift =3D <2>;=0D + interrupts =3D ;=0D + reg-io-width =3D <1>;=0D + clock-names =3D "baudclk", "apb_pclk";=0D + clocks =3D <&CP110_LABEL(slow_io_clk)>,=0D + <&CP110_LABEL(x2core_clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP110_LABEL(uart1): serial@702100 {=0D + compatible =3D "snps,dw-apb-uart";=0D + reg =3D <0x702100 0x100>;=0D + reg-shift =3D <2>;=0D + interrupts =3D ;=0D + reg-io-width =3D <1>;=0D + clock-names =3D "baudclk", "apb_pclk";=0D + clocks =3D <&CP110_LABEL(slow_io_clk)>,=0D + <&CP110_LABEL(x2core_clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP110_LABEL(uart2): serial@702200 {=0D + compatible =3D "snps,dw-apb-uart";=0D + reg =3D <0x702200 0x100>;=0D + reg-shift =3D <2>;=0D + interrupts =3D ;=0D + reg-io-width =3D <1>;=0D + clock-names =3D "baudclk", "apb_pclk";=0D + clocks =3D <&CP110_LABEL(slow_io_clk)>,=0D + <&CP110_LABEL(x2core_clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP110_LABEL(uart3): serial@702300 {=0D + compatible =3D "snps,dw-apb-uart";=0D + reg =3D <0x702300 0x100>;=0D + reg-shift =3D <2>;=0D + interrupts =3D ;=0D + reg-io-width =3D <1>;=0D + clock-names =3D "baudclk", "apb_pclk";=0D + clocks =3D <&CP110_LABEL(slow_io_clk)>,=0D + <&CP110_LABEL(x2core_clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP110_LABEL(nand_controller): nand@720000 {=0D + /*=0D + * Due to the limitation of the pins available=0D + * this controller is only usable on the CPM=0D + * for A7K and on the CPS for A8K.=0D + */=0D + compatible =3D "marvell,armada-8k-nand-controller"= ,=0D + "marvell,armada370-nand-controller";=0D + reg =3D <0x720000 0x54>;=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + interrupts =3D ;=0D + clock-names =3D "core", "reg";=0D + clocks =3D <&CP110_LABEL(nand_clk)>,=0D + <&CP110_LABEL(x2core_clk)>;=0D + marvell,system-controller =3D <&CP110_LABEL(syscon= 0)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP110_LABEL(trng): trng@760000 {=0D + compatible =3D "marvell,armada-8k-rng",=0D + "inside-secure,safexcel-eip76";=0D + reg =3D <0x760000 0x7d>;=0D + interrupts =3D ;=0D + clock-names =3D "core", "reg";=0D + clocks =3D <&CP110_LABEL(x2core_clk)>,=0D + <&CP110_LABEL(x2core_clk)>;=0D + status =3D "okay";=0D + };=0D +=0D + CP110_LABEL(sdhci0): sdhci@780000 {=0D + compatible =3D "marvell,armada-cp110-sdhci";=0D + reg =3D <0x780000 0x300>;=0D + interrupts =3D ;=0D + clock-names =3D "core", "axi";=0D + clocks =3D <&CP110_LABEL(sdio_clk)>, <&CP110_LABEL= (core_clk)>;=0D + dma-coherent;=0D + status =3D "disabled";=0D + };=0D +=0D + CP110_LABEL(crypto): crypto@800000 {=0D + compatible =3D "inside-secure,safexcel-eip197";=0D + reg =3D <0x800000 0x200000>;=0D + interrupts =3D ,=0D + ,=0D + ,=0D + ,=0D + ,=0D + ;=0D + interrupt-names =3D "mem", "ring0", "ring1",=0D + "ring2", "ring3", "eip";=0D + clock-names =3D "core", "reg";=0D + clocks =3D <&CP110_LABEL(x2core_clk)>,=0D + <&CP110_LABEL(x2core_clk)>;=0D + dma-coherent;=0D + };=0D + };=0D +=0D + CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE {=0D + compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie";=0D + reg =3D <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>,=0D + <0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>;=0D + reg-names =3D "ctrl", "config";=0D + #address-cells =3D <3>;=0D + #size-cells =3D <2>;=0D + #interrupt-cells =3D <1>;=0D + device_type =3D "pci";=0D + dma-coherent;=0D + msi-parent =3D <&gic_v2m0>;=0D +=0D + bus-range =3D <0 0xff>;=0D + ranges =3D=0D + /* downstream I/O */=0D + <0x81000000 0 CP110_PCIEx_IO_BASE(0) 0 CP110_PCIEx_IO_BAS= E(0) 0 0x10000=0D + /* non-prefetchable memory */=0D + 0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BA= SE(0) 0 0xf00000>;=0D + interrupt-map-mask =3D <0 0 0 0>;=0D + interrupt-map =3D <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 2= 2 IRQ_TYPE_LEVEL_HIGH>;=0D + interrupts =3D ;=0D + num-lanes =3D <1>;=0D + clock-names =3D "core", "reg";=0D + clocks =3D <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_= clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE {=0D + compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie";=0D + reg =3D <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>,=0D + <0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>;=0D + reg-names =3D "ctrl", "config";=0D + #address-cells =3D <3>;=0D + #size-cells =3D <2>;=0D + #interrupt-cells =3D <1>;=0D + device_type =3D "pci";=0D + dma-coherent;=0D + msi-parent =3D <&gic_v2m0>;=0D +=0D + bus-range =3D <0 0xff>;=0D + ranges =3D=0D + /* downstream I/O */=0D + <0x81000000 0 CP110_PCIEx_IO_BASE(1) 0 CP110_PCIEx_IO_BAS= E(1) 0 0x10000=0D + /* non-prefetchable memory */=0D + 0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BA= SE(1) 0 0xf00000>;=0D + interrupt-map-mask =3D <0 0 0 0>;=0D + interrupt-map =3D <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 2= 4 IRQ_TYPE_LEVEL_HIGH>;=0D + interrupts =3D ;=0D +=0D + num-lanes =3D <1>;=0D + clock-names =3D "core", "reg";=0D + clocks =3D <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_= clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE {=0D + compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie";=0D + reg =3D <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>,=0D + <0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>;=0D + reg-names =3D "ctrl", "config";=0D + #address-cells =3D <3>;=0D + #size-cells =3D <2>;=0D + #interrupt-cells =3D <1>;=0D + device_type =3D "pci";=0D + dma-coherent;=0D + msi-parent =3D <&gic_v2m0>;=0D +=0D + bus-range =3D <0 0xff>;=0D + ranges =3D=0D + /* downstream I/O */=0D + <0x81000000 0 CP110_PCIEx_IO_BASE(2) 0 CP110_PCIEx_IO_BAS= E(2) 0 0x10000=0D + /* non-prefetchable memory */=0D + 0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BA= SE(2) 0 0xf00000>;=0D + interrupt-map-mask =3D <0 0 0 0>;=0D + interrupt-map =3D <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 2= 3 IRQ_TYPE_LEVEL_HIGH>;=0D + interrupts =3D ;=0D +=0D + num-lanes =3D <1>;=0D + clock-names =3D "core", "reg";=0D + clocks =3D <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_= clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + /* 1 GHz fixed main PLL */=0D + CP110_LABEL(mainpll): CP110_LABEL(mainpll) {=0D + compatible =3D "fixed-clock";=0D + #clock-cells =3D <0>;=0D + clock-frequency =3D <1000000000>;=0D + };=0D +=0D + CP110_LABEL(x2core_clk): CP110_LABEL(x2core_clk) {=0D + compatible =3D "fixed-factor-clock";=0D + clocks =3D <&CP110_LABEL(mainpll)>;=0D + #clock-cells =3D <0>;=0D + clock-mult =3D <1>;=0D + clock-div =3D <2>;=0D + };=0D +=0D + CP110_LABEL(core_clk): CP110_LABEL(core_clk) {=0D + compatible =3D "fixed-factor-clock";=0D + clocks =3D <&CP110_LABEL(mainpll)>;=0D + #clock-cells =3D <0>;=0D + clock-mult =3D <1>;=0D + clock-div =3D <2>;=0D + };=0D +=0D + CP110_LABEL(sdio_clk): CP110_LABEL(sdio_clk) {=0D + compatible =3D "fixed-factor-clock";=0D + clocks =3D <&CP110_LABEL(mainpll)>;=0D + #clock-cells =3D <0>;=0D + clock-mult =3D <2>;=0D + clock-div =3D <5>;=0D + };=0D +=0D + CP110_LABEL(nand_clk): CP110_LABEL(nand_clk) {=0D + compatible =3D "fixed-factor-clock";=0D + clocks =3D <&CP110_LABEL(mainpll)>;=0D + #clock-cells =3D <0>;=0D + clock-mult =3D <2>;=0D + clock-div =3D <5>;=0D + };=0D +=0D + CP110_LABEL(ppv2_clk): CP110_LABEL(ppv2_clk) {=0D + compatible =3D "fixed-factor-clock";=0D + clocks =3D <&CP110_LABEL(mainpll)>;=0D + #clock-cells =3D <0>;=0D + clock-mult =3D <1>;=0D + clock-div =3D <3>;=0D + };=0D +=0D + CP110_LABEL(slow_io_clk): CP110_LABEL(slow_io_clk) {=0D + compatible =3D "fixed-factor-clock";=0D + clocks =3D <&CP110_LABEL(mainpll)>;=0D + #clock-cells =3D <0>;=0D + clock-mult =3D <1>;=0D + clock-div =3D <4>;=0D + };=0D +};=0D --=20 2.29.0