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[193.106.246.138]) by smtp.gmail.com with ESMTPSA id b30sm344622lfj.101.2021.03.18.12.58.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Mar 2021 12:58:24 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ard.biesheuvel@arm.com, mw@semihalf.com, jaz@semihalf.com, kostap@marvell.com, upstream@semihalf.com, jon@solid-run.com Subject: [edk2-non-osi PATCH 3/4] Marvell/Armada7k8k: Update device trees Date: Thu, 18 Mar 2021 20:57:56 +0100 Message-Id: <20210318195757.2974226-4-mw@semihalf.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210318195757.2974226-1-mw@semihalf.com> References: <20210318195757.2974226-1-mw@semihalf.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable This patch updates the Armada7k8k device trees to the version found in Linux v5.11. All previous modifications, compared to vanilla files, are kept, i.e. disabled SPI flashes & RTC, fixed clock tree and generic PCIE for MacchiatoBin board. Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts | 72 ++- Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi | 24 + Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi | 28 +- Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts | 57 +- Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts | 344 +------= ---- Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dtsi | 374 +++++++= +++++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi | 36 ++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi | 56 +- Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi | 38 +- Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi | 66 ++- Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi | 262 +------- Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807-quad.dtsi | 93 +++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807.dtsi | 33 ++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap80x.dtsi | 470 +++++++= ++++++++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi | 3 +- Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi | 556 +------= ---------- Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp115.dtsi | 12 + Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp11x.dtsi | 627 +++++++= +++++++++++++ 18 files changed, 1921 insertions(+), 1230 deletions(-) create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin= .dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807-quad= .dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807.dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap80x.dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp115.dtsi create mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp11x.dtsi diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts b/Sil= icon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts index f5878ef..a578b5a 100644 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040-db.dts @@ -7,9 +7,6 @@ =0D #include "armada-7040.dtsi"=0D =0D -#define GPIO_ACTIVE_HIGH 0=0D -#define GPIO_ACTIVE_LOW 1=0D -=0D / {=0D model =3D "Marvell Armada 7040 DB board";=0D compatible =3D "marvell,armada7040-db", "marvell,armada7040",=0D @@ -30,6 +27,32 @@ ethernet2 =3D &cp0_eth2;=0D };=0D =0D + cp0_exp_usb3_0_current_regulator: gpio-regulator {=0D + compatible =3D "regulator-gpio";=0D + regulator-name =3D "cp0-usb3-0-current-regulator";=0D + regulator-type =3D "current";=0D + regulator-min-microamp =3D <500000>;=0D + regulator-max-microamp =3D <900000>;=0D + gpios =3D <&expander0 4 GPIO_ACTIVE_HIGH>;=0D + states =3D <500000 0x0=0D + 900000 0x1>;=0D + enable-active-high;=0D + gpios-states =3D <0>;=0D + };=0D +=0D + cp0_exp_usb3_1_current_regulator: gpio-regulator {=0D + compatible =3D "regulator-gpio";=0D + regulator-name =3D "cp0-usb3-1-current-regulator";=0D + regulator-type =3D "current";=0D + regulator-min-microamp =3D <500000>;=0D + regulator-max-microamp =3D <900000>;=0D + gpios =3D <&expander0 5 GPIO_ACTIVE_HIGH>;=0D + states =3D <500000 0x0=0D + 900000 0x1>;=0D + enable-active-high;=0D + gpios-states =3D <0>;=0D + };=0D +=0D cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {=0D compatible =3D "regulator-fixed";=0D regulator-name =3D "usb3h0-vbus";=0D @@ -37,6 +60,7 @@ regulator-max-microvolt =3D <5000000>;=0D enable-active-high;=0D gpio =3D <&expander0 0 GPIO_ACTIVE_HIGH>;=0D + vin-supply =3D <&cp0_exp_usb3_0_current_regulator>;=0D };=0D =0D cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {=0D @@ -46,16 +70,7 @@ regulator-max-microvolt =3D <5000000>;=0D enable-active-high;=0D gpio =3D <&expander0 1 GPIO_ACTIVE_HIGH>;=0D - };=0D -=0D - cp0_usb3_0_phy: cp0-usb3-0-phy {=0D - compatible =3D "usb-nop-xceiv";=0D - vcc-supply =3D <&cp0_reg_usb3_0_vbus>;=0D - };=0D -=0D - cp0_usb3_1_phy: cp0-usb3-1-phy {=0D - compatible =3D "usb-nop-xceiv";=0D - vcc-supply =3D <&cp0_reg_usb3_1_vbus>;=0D + vin-supply =3D <&cp0_exp_usb3_1_current_regulator>;=0D };=0D };=0D =0D @@ -68,8 +83,6 @@ status =3D "okay";=0D =0D spi-flash@0 {=0D - #address-cells =3D <1>;=0D - #size-cells =3D <1>;=0D compatible =3D "jedec,spi-nor";=0D reg =3D <0>;=0D spi-max-frequency =3D <10000000>;=0D @@ -100,6 +113,8 @@ =0D &cp0_pcie2 {=0D status =3D "okay";=0D + phys =3D <&cp0_comphy5 2>;=0D + phy-names =3D "cp0-pcie2-x1-phy";=0D };=0D =0D &cp0_i2c0 {=0D @@ -171,8 +186,6 @@ status =3D "disabled";=0D =0D spi-flash@0 {=0D - #address-cells =3D <0x1>;=0D - #size-cells =3D <0x1>;=0D compatible =3D "jedec,spi-nor";=0D reg =3D <0x0>;=0D spi-max-frequency =3D <20000000>;=0D @@ -197,15 +210,36 @@ =0D &cp0_sata0 {=0D status =3D "okay";=0D +=0D + sata-port@1 {=0D + phys =3D <&cp0_comphy3 1>;=0D + phy-names =3D "cp0-sata0-1-phy";=0D + };=0D +};=0D +=0D +&cp0_comphy1 {=0D + cp0_usbh0_con: connector {=0D + compatible =3D "usb-a-connector";=0D + phy-supply =3D <&cp0_reg_usb3_0_vbus>;=0D + };=0D };=0D =0D &cp0_usb3_0 {=0D - usb-phy =3D <&cp0_usb3_0_phy>;=0D + phys =3D <&cp0_comphy1 0>;=0D + phy-names =3D "cp0-usb3h0-comphy";=0D status =3D "okay";=0D };=0D =0D +&cp0_comphy4 {=0D + cp0_usbh1_con: connector {=0D + compatible =3D "usb-a-connector";=0D + phy-supply =3D <&cp0_reg_usb3_1_vbus>;=0D + };=0D +};=0D +=0D &cp0_usb3_1 {=0D - usb-phy =3D <&cp0_usb3_1_phy>;=0D + phys =3D <&cp0_comphy4 1>;=0D + phy-names =3D "cp0-usb3h1-comphy";=0D status =3D "okay";=0D };=0D =0D diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi b/Silic= on/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi index 03109b2..30c2e4e 100644 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-7040.dtsi @@ -14,3 +14,27 @@ compatible =3D "marvell,armada7040", "marvell,armada-ap806-quad",= =0D "marvell,armada-ap806";=0D };=0D +=0D +&cp0_pcie0 {=0D + iommu-map =3D=0D + <0x0 &smmu 0x480 0x20>,=0D + <0x100 &smmu 0x4a0 0x20>,=0D + <0x200 &smmu 0x4c0 0x20>;=0D + iommu-map-mask =3D <0x031f>;=0D +};=0D +=0D +&cp0_sata0 {=0D + iommus =3D <&smmu 0x444>;=0D +};=0D +=0D +&cp0_sdhci0 {=0D + iommus =3D <&smmu 0x445>;=0D +};=0D +=0D +&cp0_usb3_0 {=0D + iommus =3D <&smmu 0x440>;=0D +};=0D +=0D +&cp0_usb3_1 {=0D + iommus =3D <&smmu 0x441>;=0D +};=0D diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi b/Silic= on/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi index 78f9d87..0fdcb35 100644 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-70x0.dtsi @@ -17,23 +17,23 @@ /*=0D * Instantiate the CP110=0D */=0D -#define CP110_NAME cp0=0D -#define CP110_BASE f2000000=0D -#define CP110_PCIE_IO_BASE 0xf9000000=0D -#define CP110_PCIE_MEM_BASE 0xf6000000=0D -#define CP110_PCIE0_BASE f2600000=0D -#define CP110_PCIE1_BASE f2620000=0D -#define CP110_PCIE2_BASE f2640000=0D +#define CP11X_NAME cp0=0D +#define CP11X_BASE f2000000=0D +#define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000))=0D +#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000=0D +#define CP11X_PCIE0_BASE f2600000=0D +#define CP11X_PCIE1_BASE f2620000=0D +#define CP11X_PCIE2_BASE f2640000=0D =0D #include "armada-cp110.dtsi"=0D =0D -#undef CP110_NAME=0D -#undef CP110_BASE=0D -#undef CP110_PCIE_IO_BASE=0D -#undef CP110_PCIE_MEM_BASE=0D -#undef CP110_PCIE0_BASE=0D -#undef CP110_PCIE1_BASE=0D -#undef CP110_PCIE2_BASE=0D +#undef CP11X_NAME=0D +#undef CP11X_BASE=0D +#undef CP11X_PCIEx_MEM_BASE=0D +#undef CP11X_PCIEx_MEM_SIZE=0D +#undef CP11X_PCIE0_BASE=0D +#undef CP11X_PCIE1_BASE=0D +#undef CP11X_PCIE2_BASE=0D =0D &cp0_gpio1 {=0D status =3D "okay";=0D diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts b/Sil= icon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts index e813922..9fea84f 100644 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-db.dts @@ -7,9 +7,6 @@ =0D #include "armada-8040.dtsi"=0D =0D -#define GPIO_ACTIVE_HIGH 0=0D -#define GPIO_ACTIVE_LOW 1=0D -=0D / {=0D model =3D "Marvell Armada 8040 DB board";=0D compatible =3D "marvell,armada8040-db", "marvell,armada8040",=0D @@ -29,6 +26,8 @@ ethernet1 =3D &cp0_eth2;=0D ethernet2 =3D &cp1_eth0;=0D ethernet3 =3D &cp1_eth1;=0D + i2c1 =3D &cp0_i2c0;=0D + i2c2 =3D &cp1_i2c0;=0D };=0D =0D cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {=0D @@ -54,11 +53,6 @@ vcc-supply =3D <&cp0_reg_usb3_0_vbus>;=0D };=0D =0D - cp0_usb3_1_phy: cp0-usb3-1-phy {=0D - compatible =3D "usb-nop-xceiv";=0D - vcc-supply =3D <&cp0_reg_usb3_1_vbus>;=0D - };=0D -=0D cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus {=0D compatible =3D "regulator-fixed";=0D regulator-name =3D "cp1-usb3h0-vbus";=0D @@ -74,17 +68,10 @@ };=0D };=0D =0D -&i2c0 {=0D - status =3D "okay";=0D - clock-frequency =3D <100000>;=0D -};=0D -=0D &spi0 {=0D status =3D "okay";=0D =0D spi-flash@0 {=0D - #address-cells =3D <1>;=0D - #size-cells =3D <1>;=0D compatible =3D "jedec,spi-nor";=0D reg =3D <0>;=0D spi-max-frequency =3D <10000000>;=0D @@ -115,11 +102,15 @@ =0D /* CON6 on CP0 expansion */=0D &cp0_pcie0 {=0D + phys =3D <&cp0_comphy0 0>;=0D + phy-names =3D "cp0-pcie0-x1-phy";=0D status =3D "okay";=0D };=0D =0D /* CON5 on CP0 expansion */=0D &cp0_pcie2 {=0D + phys =3D <&cp0_comphy5 2>;=0D + phy-names =3D "cp0-pcie2-x1-phy";=0D status =3D "okay";=0D };=0D =0D @@ -150,6 +141,15 @@ /* CON4 on CP0 expansion */=0D &cp0_sata0 {=0D status =3D "okay";=0D +=0D + sata-port@0 {=0D + phys =3D <&cp0_comphy1 0>;=0D + phy-names =3D "cp0-sata0-0-phy";=0D + };=0D + sata-port@1 {=0D + phys =3D <&cp0_comphy3 1>;=0D + phy-names =3D "cp0-sata0-1-phy";=0D + };=0D };=0D =0D /* CON9 on CP0 expansion */=0D @@ -158,9 +158,17 @@ status =3D "okay";=0D };=0D =0D +&cp0_comphy4 {=0D + cp0_usbh1_con: connector {=0D + compatible =3D "usb-a-connector";=0D + phy-supply =3D <&cp0_reg_usb3_1_vbus>;=0D + };=0D +};=0D +=0D /* CON10 on CP0 expansion */=0D &cp0_usb3_1 {=0D - usb-phy =3D <&cp0_usb3_1_phy>;=0D + phys =3D <&cp0_comphy4 1>;=0D + phy-names =3D "cp0-usb3h1-comphy";=0D status =3D "okay";=0D };=0D =0D @@ -194,16 +202,22 @@ =0D /* CON6 on CP1 expansion */=0D &cp1_pcie0 {=0D + phys =3D <&cp1_comphy0 0>;=0D + phy-names =3D "cp1-pcie0-x1-phy";=0D status =3D "okay";=0D };=0D =0D /* CON7 on CP1 expansion */=0D &cp1_pcie1 {=0D + phys =3D <&cp1_comphy4 1>;=0D + phy-names =3D "cp1-pcie1-x1-phy";=0D status =3D "okay";=0D };=0D =0D /* CON5 on CP1 expansion */=0D &cp1_pcie2 {=0D + phys =3D <&cp1_comphy5 2>;=0D + phy-names =3D "cp1-pcie2-x1-phy";=0D status =3D "okay";=0D };=0D =0D @@ -216,8 +230,6 @@ status =3D "disabled";=0D =0D spi-flash@0 {=0D - #address-cells =3D <0x1>;=0D - #size-cells =3D <0x1>;=0D compatible =3D "jedec,spi-nor";=0D reg =3D <0x0>;=0D spi-max-frequency =3D <20000000>;=0D @@ -282,6 +294,15 @@ /* CON4 on CP1 expansion */=0D &cp1_sata0 {=0D status =3D "okay";=0D +=0D + sata-port@0 {=0D + phys =3D <&cp1_comphy1 0>;=0D + phy-names =3D "cp1-sata0-0-phy";=0D + };=0D + sata-port@1 {=0D + phys =3D <&cp1_comphy3 1>;=0D + phy-names =3D "cp1-sata0-1-phy";=0D + };=0D };=0D =0D /* CON9 on CP1 expansion */=0D diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts b/= Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts index d9c9348..740bdaf 100644 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts @@ -5,233 +5,13 @@ * Device Tree file for MACCHIATOBin Armada 8040 community board platform= =0D */=0D =0D -#include "armada-8040.dtsi"=0D -=0D -#define GPIO_ACTIVE_HIGH 0=0D -#define GPIO_ACTIVE_LOW 1=0D +#include "armada-8040-mcbin.dtsi"=0D =0D / {=0D - model =3D "Marvell 8040 MACCHIATOBin";=0D - compatible =3D "marvell,armada8040-mcbin", "marvell,armada8040",=0D + model =3D "Marvell 8040 MACCHIATOBin Double-shot";=0D + compatible =3D "marvell,armada8040-mcbin-doubleshot",=0D + "marvell,armada8040-mcbin", "marvell,armada8040",= =0D "marvell,armada-ap806-quad", "marvell,armada-ap806= ";=0D -=0D - chosen {=0D - stdout-path =3D "serial0:115200n8";=0D - };=0D -=0D - memory@0 {=0D - device_type =3D "memory";=0D - reg =3D <0x0 0x0 0x0 0x80000000>;=0D - };=0D -=0D - aliases {=0D - ethernet0 =3D &cp0_eth0;=0D - ethernet1 =3D &cp1_eth0;=0D - ethernet2 =3D &cp1_eth1;=0D - ethernet3 =3D &cp1_eth2;=0D - };=0D -=0D - /* Regulator labels correspond with schematics */=0D - v_3_3: regulator-3-3v {=0D - compatible =3D "regulator-fixed";=0D - regulator-name =3D "v_3_3";=0D - regulator-min-microvolt =3D <3300000>;=0D - regulator-max-microvolt =3D <3300000>;=0D - regulator-always-on;=0D - status =3D "okay";=0D - };=0D -=0D - v_vddo_h: regulator-1-8v {=0D - compatible =3D "regulator-fixed";=0D - regulator-name =3D "v_vddo_h";=0D - regulator-min-microvolt =3D <1800000>;=0D - regulator-max-microvolt =3D <1800000>;=0D - regulator-always-on;=0D - status =3D "okay";=0D - };=0D -=0D - v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {=0D - compatible =3D "regulator-fixed";=0D - enable-active-high;=0D - gpio =3D <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>;=0D - pinctrl-names =3D "default";=0D - pinctrl-0 =3D <&cp0_xhci_vbus_pins>;=0D - regulator-name =3D "v_5v0_usb3_hst_vbus";=0D - regulator-min-microvolt =3D <5000000>;=0D - regulator-max-microvolt =3D <5000000>;=0D - status =3D "okay";=0D - };=0D -=0D - usb3h0_phy: usb3_phy0 {=0D - compatible =3D "usb-nop-xceiv";=0D - vcc-supply =3D <&v_5v0_usb3_hst_vbus>;=0D - };=0D -=0D - sfp_eth0: sfp-eth0 {=0D - /* CON15,16 - CPM lane 4 */=0D - compatible =3D "sff,sfp";=0D - i2c-bus =3D <&sfpp0_i2c>;=0D - los-gpio =3D <&cp1_gpio1 28 GPIO_ACTIVE_HIGH>;=0D - mod-def0-gpio =3D <&cp1_gpio1 27 GPIO_ACTIVE_LOW>;=0D - tx-disable-gpio =3D <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>;=0D - tx-fault-gpio =3D <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>;=0D - pinctrl-names =3D "default";=0D - pinctrl-0 =3D <&cp1_sfpp0_pins>;=0D - };=0D -=0D - sfp_eth1: sfp-eth1 {=0D - /* CON17,18 - CPS lane 4 */=0D - compatible =3D "sff,sfp";=0D - i2c-bus =3D <&sfpp1_i2c>;=0D - los-gpio =3D <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>;=0D - mod-def0-gpio =3D <&cp1_gpio1 11 GPIO_ACTIVE_LOW>;=0D - tx-disable-gpio =3D <&cp1_gpio1 10 GPIO_ACTIVE_HIGH>;=0D - tx-fault-gpio =3D <&cp0_gpio2 30 GPIO_ACTIVE_HIGH>;=0D - pinctrl-names =3D "default";=0D - pinctrl-0 =3D <&cp1_sfpp1_pins &cp0_sfpp1_pins>;=0D - };=0D -=0D - sfp_eth3: sfp-eth3 {=0D - /* CON3,4 - CPS lane 5 */=0D - compatible =3D "sff,sfp";=0D - i2c-bus =3D <&sfp_1g_i2c>;=0D - los-gpio =3D <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>;=0D - mod-def0-gpio =3D <&cp0_gpio2 21 GPIO_ACTIVE_LOW>;=0D - tx-disable-gpio =3D <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>;=0D - tx-fault-gpio =3D <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>;=0D - pinctrl-names =3D "default";=0D - pinctrl-0 =3D <&cp0_sfp_1g_pins &cp1_sfp_1g_pins>;=0D - };=0D -};=0D -=0D -&uart0 {=0D - status =3D "okay";=0D - pinctrl-0 =3D <&uart0_pins>;=0D - pinctrl-names =3D "default";=0D -};=0D -=0D -&ap_sdhci0 {=0D - bus-width =3D <8>;=0D - /*=0D - * Not stable in HS modes - phy needs "more calibration", so add=0D - * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes.=0D - */=0D - marvell,xenon-phy-slow-mode;=0D - no-1-8-v;=0D - no-sd;=0D - no-sdio;=0D - non-removable;=0D - status =3D "okay";=0D - vqmmc-supply =3D <&v_vddo_h>;=0D -};=0D -=0D -&cp0_i2c0 {=0D - clock-frequency =3D <100000>;=0D - pinctrl-names =3D "default";=0D - pinctrl-0 =3D <&cp0_i2c0_pins>;=0D - status =3D "okay";=0D -};=0D -=0D -&cp0_i2c1 {=0D - clock-frequency =3D <100000>;=0D - pinctrl-names =3D "default";=0D - pinctrl-0 =3D <&cp0_i2c1_pins>;=0D - status =3D "okay";=0D -=0D - i2c-switch@70 {=0D - compatible =3D "nxp,pca9548";=0D - #address-cells =3D <1>;=0D - #size-cells =3D <0>;=0D - reg =3D <0x70>;=0D -=0D - sfpp0_i2c: i2c@0 {=0D - #address-cells =3D <1>;=0D - #size-cells =3D <0>;=0D - reg =3D <0>;=0D - };=0D - sfpp1_i2c: i2c@1 {=0D - #address-cells =3D <1>;=0D - #size-cells =3D <0>;=0D - reg =3D <1>;=0D - };=0D - sfp_1g_i2c: i2c@2 {=0D - #address-cells =3D <1>;=0D - #size-cells =3D <0>;=0D - reg =3D <2>;=0D - };=0D - };=0D -};=0D -=0D -/* J25 UART header */=0D -&cp0_uart1 {=0D - pinctrl-names =3D "default";=0D - pinctrl-0 =3D <&cp0_uart1_pins>;=0D - status =3D "okay";=0D -};=0D -=0D -&cp0_mdio {=0D - pinctrl-names =3D "default";=0D - pinctrl-0 =3D <&cp0_ge_mdio_pins>;=0D - status =3D "okay";=0D -=0D - ge_phy: ethernet-phy@0 {=0D - reg =3D <0>;=0D - };=0D -};=0D -=0D -&cp0_pcie0 {=0D - compatible =3D "marvell,armada8k-pcie-ecam", "snps,dw-pcie-ecam";= =0D - reg =3D <0 0xe0000000 0 0xff00000>;=0D - bus-range =3D <0 0xfe>;=0D - pinctrl-names =3D "default";=0D - pinctrl-0 =3D <&cp0_pcie_pins>;=0D - num-lanes =3D <4>;=0D - num-viewport =3D <8>;=0D - reset-gpio =3D <&cp0_gpio1 20 GPIO_ACTIVE_LOW>;=0D - ranges =3D <0x1000000 0x0 0x00000000 0x0 0xeff00000 0x0 0x00010000= >,=0D - <0x2000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>,= =0D - <0x3000000 0x8 0x00000000 0x8 0x00000000 0x1 0x00000000>;= =0D - status =3D "okay";=0D -};=0D -=0D -&cp0_pinctrl {=0D - cp0_ge_mdio_pins: ge-mdio-pins {=0D - marvell,pins =3D "mpp32", "mpp34";=0D - marvell,function =3D "ge";=0D - };=0D - cp0_i2c1_pins: i2c1-pins {=0D - marvell,pins =3D "mpp35", "mpp36";=0D - marvell,function =3D "i2c1";=0D - };=0D - cp0_i2c0_pins: i2c0-pins {=0D - marvell,pins =3D "mpp37", "mpp38";=0D - marvell,function =3D "i2c0";=0D - };=0D - cp0_uart1_pins: uart1-pins {=0D - marvell,pins =3D "mpp40", "mpp41";=0D - marvell,function =3D "uart1";=0D - };=0D - cp0_xhci_vbus_pins: xhci0-vbus-pins {=0D - marvell,pins =3D "mpp47";=0D - marvell,function =3D "gpio";=0D - };=0D - cp0_sfp_1g_pins: sfp-1g-pins {=0D - marvell,pins =3D "mpp51", "mpp53", "mpp54";=0D - marvell,function =3D "gpio";=0D - };=0D - cp0_pcie_pins: pcie-pins {=0D - marvell,pins =3D "mpp52";=0D - marvell,function =3D "gpio";=0D - };=0D - cp0_sdhci_pins: sdhci-pins {=0D - marvell,pins =3D "mpp55", "mpp56", "mpp57", "mpp58", "mpp5= 9",=0D - "mpp60", "mpp61";=0D - marvell,function =3D "sdio";=0D - };=0D - cp0_sfpp1_pins: sfpp1-pins {=0D - marvell,pins =3D "mpp62";=0D - marvell,function =3D "gpio";=0D - };=0D };=0D =0D &cp0_xmdio {=0D @@ -250,128 +30,16 @@ };=0D };=0D =0D -&cp0_ethernet {=0D - status =3D "okay";=0D -};=0D -=0D &cp0_eth0 {=0D status =3D "okay";=0D /* Network PHY */=0D phy =3D <&phy0>;=0D - phy-mode =3D "10gbase-kr";=0D - /* Generic PHY, providing serdes lanes */=0D - phys =3D <&cp0_comphy4 0>;=0D -};=0D -=0D -&cp0_sata0 {=0D - /* CPM Lane 0 - U29 */=0D - status =3D "okay";=0D -};=0D -=0D -&cp0_sdhci0 {=0D - /* U6 */=0D - broken-cd;=0D - bus-width =3D <4>;=0D - pinctrl-names =3D "default";=0D - pinctrl-0 =3D <&cp0_sdhci_pins>;=0D - status =3D "okay";=0D - vqmmc-supply =3D <&v_3_3>;=0D -};=0D -=0D -&cp0_usb3_0 {=0D - /* J38? - USB2.0 only */=0D - status =3D "okay";=0D -};=0D -=0D -&cp0_usb3_1 {=0D - /* J38? - USB2.0 only */=0D - status =3D "okay";=0D -};=0D -=0D -&cp1_ethernet {=0D - status =3D "okay";=0D + phy-mode =3D "10gbase-r";=0D };=0D =0D &cp1_eth0 {=0D status =3D "okay";=0D /* Network PHY */=0D phy =3D <&phy8>;=0D - phy-mode =3D "10gbase-kr";=0D - /* Generic PHY, providing serdes lanes */=0D - phys =3D <&cp1_comphy4 0>;=0D -};=0D -=0D -&cp1_eth1 {=0D - /* CPS Lane 0 - J5 (Gigabit RJ45) */=0D - status =3D "okay";=0D - /* Network PHY */=0D - phy =3D <&ge_phy>;=0D - phy-mode =3D "sgmii";=0D - /* Generic PHY, providing serdes lanes */=0D - phys =3D <&cp1_comphy0 1>;=0D -};=0D -=0D -&cp1_eth2 {=0D - /* CPS Lane 5 */=0D - status =3D "okay";=0D - /* Network PHY */=0D - phy-mode =3D "2500base-x";=0D - managed =3D "in-band-status";=0D - /* Generic PHY, providing serdes lanes */=0D - phys =3D <&cp1_comphy5 2>;=0D - sfp =3D <&sfp_eth3>;=0D -};=0D -=0D -&cp1_pinctrl {=0D - cp1_sfpp1_pins: sfpp1-pins {=0D - marvell,pins =3D "mpp8", "mpp10", "mpp11";=0D - marvell,function =3D "gpio";=0D - };=0D - cp1_spi1_pins: spi1-pins {=0D - marvell,pins =3D "mpp12", "mpp13", "mpp14", "mpp15", "mpp1= 6";=0D - marvell,function =3D "spi1";=0D - };=0D - cp1_uart0_pins: uart0-pins {=0D - marvell,pins =3D "mpp6", "mpp7";=0D - marvell,function =3D "uart0";=0D - };=0D - cp1_sfp_1g_pins: sfp-1g-pins {=0D - marvell,pins =3D "mpp24";=0D - marvell,function =3D "gpio";=0D - };=0D - cp1_sfpp0_pins: sfpp0-pins {=0D - marvell,pins =3D "mpp26", "mpp27", "mpp28", "mpp29";=0D - marvell,function =3D "gpio";=0D - };=0D -};=0D -=0D -/* J27 UART header */=0D -&cp1_uart0 {=0D - pinctrl-names =3D "default";=0D - pinctrl-0 =3D <&cp1_uart0_pins>;=0D - status =3D "okay";=0D -};=0D -=0D -&cp1_sata0 {=0D - /* CPS Lane 1 - U32 */=0D - /* CPS Lane 3 - U31 */=0D - status =3D "okay";=0D -};=0D -=0D -&cp1_spi1 {=0D - pinctrl-names =3D "default";=0D - pinctrl-0 =3D <&cp1_spi1_pins>;=0D - status =3D "disabled";=0D -=0D - spi-flash@0 {=0D - compatible =3D "st,w25q32";=0D - spi-max-frequency =3D <50000000>;=0D - reg =3D <0>;=0D - };=0D -};=0D -=0D -&cp1_usb3_0 {=0D - /* CPS Lane 2 - CON7 */=0D - usb-phy =3D <&usb3h0_phy>;=0D - status =3D "okay";=0D + phy-mode =3D "10gbase-r";=0D };=0D diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dtsi b= /Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dtsi new file mode 100644 index 0000000..970e875 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dtsi @@ -0,0 +1,374 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)=0D +/*=0D + * Copyright (C) 2016 Marvell Technology Group Ltd.=0D + *=0D + * Device Tree file for MACCHIATOBin Armada 8040 community board platform= =0D + */=0D +=0D +#include "armada-8040.dtsi"=0D +=0D +/ {=0D + model =3D "Marvell 8040 MACCHIATOBin";=0D + compatible =3D "marvell,armada8040-mcbin", "marvell,armada8040",=0D + "marvell,armada-ap806-quad", "marvell,armada-ap806= ";=0D +=0D + chosen {=0D + stdout-path =3D "serial0:115200n8";=0D + };=0D +=0D + memory@0 {=0D + device_type =3D "memory";=0D + reg =3D <0x0 0x0 0x0 0x80000000>;=0D + };=0D +=0D + aliases {=0D + ethernet0 =3D &cp0_eth0;=0D + ethernet1 =3D &cp1_eth0;=0D + ethernet2 =3D &cp1_eth1;=0D + ethernet3 =3D &cp1_eth2;=0D + };=0D +=0D + /* Regulator labels correspond with schematics */=0D + v_3_3: regulator-3-3v {=0D + compatible =3D "regulator-fixed";=0D + regulator-name =3D "v_3_3";=0D + regulator-min-microvolt =3D <3300000>;=0D + regulator-max-microvolt =3D <3300000>;=0D + regulator-always-on;=0D + status =3D "okay";=0D + };=0D +=0D + v_vddo_h: regulator-1-8v {=0D + compatible =3D "regulator-fixed";=0D + regulator-name =3D "v_vddo_h";=0D + regulator-min-microvolt =3D <1800000>;=0D + regulator-max-microvolt =3D <1800000>;=0D + regulator-always-on;=0D + status =3D "okay";=0D + };=0D +=0D + v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {=0D + compatible =3D "regulator-fixed";=0D + enable-active-high;=0D + gpio =3D <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>;=0D + pinctrl-names =3D "default";=0D + pinctrl-0 =3D <&cp0_xhci_vbus_pins>;=0D + regulator-name =3D "v_5v0_usb3_hst_vbus";=0D + regulator-min-microvolt =3D <5000000>;=0D + regulator-max-microvolt =3D <5000000>;=0D + status =3D "okay";=0D + };=0D +=0D + sfp_eth0: sfp-eth0 {=0D + /* CON15,16 - CPM lane 4 */=0D + compatible =3D "sff,sfp";=0D + i2c-bus =3D <&sfpp0_i2c>;=0D + los-gpio =3D <&cp1_gpio1 28 GPIO_ACTIVE_HIGH>;=0D + mod-def0-gpio =3D <&cp1_gpio1 27 GPIO_ACTIVE_LOW>;=0D + tx-disable-gpio =3D <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>;=0D + tx-fault-gpio =3D <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>;=0D + pinctrl-names =3D "default";=0D + pinctrl-0 =3D <&cp1_sfpp0_pins>;=0D + maximum-power-milliwatt =3D <2000>;=0D + };=0D +=0D + sfp_eth1: sfp-eth1 {=0D + /* CON17,18 - CPS lane 4 */=0D + compatible =3D "sff,sfp";=0D + i2c-bus =3D <&sfpp1_i2c>;=0D + los-gpio =3D <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>;=0D + mod-def0-gpio =3D <&cp1_gpio1 11 GPIO_ACTIVE_LOW>;=0D + tx-disable-gpio =3D <&cp1_gpio1 10 GPIO_ACTIVE_HIGH>;=0D + tx-fault-gpio =3D <&cp0_gpio2 30 GPIO_ACTIVE_HIGH>;=0D + pinctrl-names =3D "default";=0D + pinctrl-0 =3D <&cp1_sfpp1_pins &cp0_sfpp1_pins>;=0D + maximum-power-milliwatt =3D <2000>;=0D + };=0D +=0D + sfp_eth3: sfp-eth3 {=0D + /* CON13,14 - CPS lane 5 */=0D + compatible =3D "sff,sfp";=0D + i2c-bus =3D <&sfp_1g_i2c>;=0D + los-gpio =3D <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>;=0D + mod-def0-gpio =3D <&cp0_gpio2 21 GPIO_ACTIVE_LOW>;=0D + tx-disable-gpio =3D <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>;=0D + tx-fault-gpio =3D <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>;=0D + pinctrl-names =3D "default";=0D + pinctrl-0 =3D <&cp0_sfp_1g_pins &cp1_sfp_1g_pins>;=0D + maximum-power-milliwatt =3D <2000>;=0D + };=0D +};=0D +=0D +&uart0 {=0D + status =3D "okay";=0D + pinctrl-0 =3D <&uart0_pins>;=0D + pinctrl-names =3D "default";=0D +};=0D +=0D +&ap_sdhci0 {=0D + bus-width =3D <8>;=0D + /*=0D + * Not stable in HS modes - phy needs "more calibration", so add=0D + * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes.=0D + */=0D + marvell,xenon-phy-slow-mode;=0D + no-1-8-v;=0D + no-sd;=0D + no-sdio;=0D + non-removable;=0D + status =3D "okay";=0D + vqmmc-supply =3D <&v_vddo_h>;=0D +};=0D +=0D +&cp0_i2c0 {=0D + clock-frequency =3D <100000>;=0D + pinctrl-names =3D "default";=0D + pinctrl-0 =3D <&cp0_i2c0_pins>;=0D + status =3D "okay";=0D +};=0D +=0D +&cp0_i2c1 {=0D + clock-frequency =3D <100000>;=0D + pinctrl-names =3D "default";=0D + pinctrl-0 =3D <&cp0_i2c1_pins>;=0D + status =3D "okay";=0D +=0D + i2c-switch@70 {=0D + compatible =3D "nxp,pca9548";=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + reg =3D <0x70>;=0D +=0D + sfpp0_i2c: i2c@0 {=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + reg =3D <0>;=0D + };=0D + sfpp1_i2c: i2c@1 {=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + reg =3D <1>;=0D + };=0D + sfp_1g_i2c: i2c@2 {=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + reg =3D <2>;=0D + };=0D + };=0D +};=0D +=0D +/* J25 UART header */=0D +&cp0_uart1 {=0D + pinctrl-names =3D "default";=0D + pinctrl-0 =3D <&cp0_uart1_pins>;=0D + status =3D "okay";=0D +};=0D +=0D +&cp0_mdio {=0D + pinctrl-names =3D "default";=0D + pinctrl-0 =3D <&cp0_ge_mdio_pins>;=0D + status =3D "okay";=0D +=0D + ge_phy: ethernet-phy@0 {=0D + reg =3D <0>;=0D + };=0D +};=0D +=0D +&cp0_pcie0 {=0D + compatible =3D "marvell,armada8k-pcie-ecam", "pci-host-ecam-generi= c";=0D + reg =3D <0 0xe0000000 0 0xff00000>;=0D + bus-range =3D <0 0xfe>;=0D + pinctrl-names =3D "default";=0D + pinctrl-0 =3D <&cp0_pcie_pins>;=0D + num-lanes =3D <4>;=0D + num-viewport =3D <8>;=0D + reset-gpios =3D <&cp0_gpio2 20 GPIO_ACTIVE_LOW>;=0D + ranges =3D <0x1000000 0x0 0x00000000 0x0 0xeff00000 0x0 0x00010000= >,=0D + <0x2000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>,= =0D + <0x3000000 0x8 0x00000000 0x8 0x00000000 0x1 0x00000000>;= =0D + phys =3D <&cp0_comphy0 0>, <&cp0_comphy1 0>,=0D + <&cp0_comphy2 0>, <&cp0_comphy3 0>;=0D + phy-names =3D "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy",= =0D + "cp0-pcie0-x4-lane2-phy", "cp0-pcie0-x4-lane3-phy";=0D + status =3D "okay";=0D +};=0D +=0D +&cp0_pinctrl {=0D + cp0_ge_mdio_pins: ge-mdio-pins {=0D + marvell,pins =3D "mpp32", "mpp34";=0D + marvell,function =3D "ge";=0D + };=0D + cp0_i2c1_pins: i2c1-pins {=0D + marvell,pins =3D "mpp35", "mpp36";=0D + marvell,function =3D "i2c1";=0D + };=0D + cp0_i2c0_pins: i2c0-pins {=0D + marvell,pins =3D "mpp37", "mpp38";=0D + marvell,function =3D "i2c0";=0D + };=0D + cp0_uart1_pins: uart1-pins {=0D + marvell,pins =3D "mpp40", "mpp41";=0D + marvell,function =3D "uart1";=0D + };=0D + cp0_xhci_vbus_pins: xhci0-vbus-pins {=0D + marvell,pins =3D "mpp47";=0D + marvell,function =3D "gpio";=0D + };=0D + cp0_sfp_1g_pins: sfp-1g-pins {=0D + marvell,pins =3D "mpp51", "mpp53", "mpp54";=0D + marvell,function =3D "gpio";=0D + };=0D + cp0_pcie_pins: pcie-pins {=0D + marvell,pins =3D "mpp52";=0D + marvell,function =3D "gpio";=0D + };=0D + cp0_sdhci_pins: sdhci-pins {=0D + marvell,pins =3D "mpp55", "mpp56", "mpp57", "mpp58", "mpp5= 9",=0D + "mpp60", "mpp61";=0D + marvell,function =3D "sdio";=0D + };=0D + cp0_sfpp1_pins: sfpp1-pins {=0D + marvell,pins =3D "mpp62";=0D + marvell,function =3D "gpio";=0D + };=0D +};=0D +=0D +&cp0_ethernet {=0D + status =3D "okay";=0D +};=0D +=0D +&cp0_eth0 {=0D + /* Generic PHY, providing serdes lanes */=0D + phys =3D <&cp0_comphy4 0>;=0D +};=0D +=0D +&cp0_sata0 {=0D + status =3D "okay";=0D +=0D + /* CPM Lane 5 - U29 */=0D + sata-port@1 {=0D + phys =3D <&cp0_comphy5 1>;=0D + phy-names =3D "cp0-sata0-1-phy";=0D + };=0D +};=0D +=0D +&cp0_sdhci0 {=0D + /* U6 */=0D + broken-cd;=0D + bus-width =3D <4>;=0D + pinctrl-names =3D "default";=0D + pinctrl-0 =3D <&cp0_sdhci_pins>;=0D + status =3D "okay";=0D + vqmmc-supply =3D <&v_3_3>;=0D +};=0D +=0D +&cp0_usb3_0 {=0D + /* J38? - USB2.0 only */=0D + status =3D "okay";=0D +};=0D +=0D +&cp0_usb3_1 {=0D + /* J38? - USB2.0 only */=0D + status =3D "okay";=0D +};=0D +=0D +&cp1_ethernet {=0D + status =3D "okay";=0D +};=0D +=0D +&cp1_eth0 {=0D + /* Generic PHY, providing serdes lanes */=0D + phys =3D <&cp1_comphy4 0>;=0D +};=0D +=0D +&cp1_eth1 {=0D + /* CPS Lane 0 - J5 (Gigabit RJ45) */=0D + status =3D "okay";=0D + /* Network PHY */=0D + phy =3D <&ge_phy>;=0D + phy-mode =3D "sgmii";=0D + /* Generic PHY, providing serdes lanes */=0D + phys =3D <&cp1_comphy0 1>;=0D +};=0D +=0D +&cp1_eth2 {=0D + /* CPS Lane 5 */=0D + status =3D "okay";=0D + /* Network PHY */=0D + phy-mode =3D "2500base-x";=0D + managed =3D "in-band-status";=0D + /* Generic PHY, providing serdes lanes */=0D + phys =3D <&cp1_comphy5 2>;=0D + sfp =3D <&sfp_eth3>;=0D +};=0D +=0D +&cp1_pinctrl {=0D + cp1_sfpp1_pins: sfpp1-pins {=0D + marvell,pins =3D "mpp8", "mpp10", "mpp11";=0D + marvell,function =3D "gpio";=0D + };=0D + cp1_spi1_pins: spi1-pins {=0D + marvell,pins =3D "mpp12", "mpp13", "mpp14", "mpp15", "mpp1= 6";=0D + marvell,function =3D "spi1";=0D + };=0D + cp1_uart0_pins: uart0-pins {=0D + marvell,pins =3D "mpp6", "mpp7";=0D + marvell,function =3D "uart0";=0D + };=0D + cp1_sfp_1g_pins: sfp-1g-pins {=0D + marvell,pins =3D "mpp24";=0D + marvell,function =3D "gpio";=0D + };=0D + cp1_sfpp0_pins: sfpp0-pins {=0D + marvell,pins =3D "mpp26", "mpp27", "mpp28", "mpp29";=0D + marvell,function =3D "gpio";=0D + };=0D +};=0D +=0D +/* J27 UART header */=0D +&cp1_uart0 {=0D + pinctrl-names =3D "default";=0D + pinctrl-0 =3D <&cp1_uart0_pins>;=0D + status =3D "okay";=0D +};=0D +=0D +&cp1_sata0 {=0D + status =3D "okay";=0D +=0D + /* CPS Lane 1 - U32 */=0D + sata-port@0 {=0D + phys =3D <&cp1_comphy1 0>;=0D + phy-names =3D "cp1-sata0-0-phy";=0D + };=0D +=0D + /* CPS Lane 3 - U31 */=0D + sata-port@1 {=0D + phys =3D <&cp1_comphy3 1>;=0D + phy-names =3D "cp1-sata0-1-phy";=0D + };=0D +};=0D +=0D +&cp1_spi1 {=0D + pinctrl-names =3D "default";=0D + pinctrl-0 =3D <&cp1_spi1_pins>;=0D +=0D + spi-flash@0 {=0D + compatible =3D "st,w25q32";=0D + spi-max-frequency =3D <50000000>;=0D + reg =3D <0>;=0D + };=0D +};=0D +=0D +&cp1_comphy2 {=0D + cp1_usbh0_con: connector {=0D + compatible =3D "usb-a-connector";=0D + phy-supply =3D <&v_5v0_usb3_hst_vbus>;=0D + };=0D +};=0D +=0D +&cp1_usb3_0 {=0D + /* CPS Lane 2 - CON7 */=0D + phys =3D <&cp1_comphy2 0>;=0D + phy-names =3D "cp1-usb3h0-comphy";=0D + status =3D "okay";=0D +};=0D diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi b/Silic= on/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi index 784ef3f..0a676df 100644 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040.dtsi @@ -15,6 +15,14 @@ "marvell,armada-ap806";=0D };=0D =0D +&cp0_pcie0 {=0D + iommu-map =3D=0D + <0x0 &smmu 0x480 0x20>,=0D + <0x100 &smmu 0x4a0 0x20>,=0D + <0x200 &smmu 0x4c0 0x20>;=0D + iommu-map-mask =3D <0x031f>;=0D +};=0D +=0D /* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock= =0D * in CP master is not connected (by package) to the oscillator. So=0D * disable it. However, the RTC clock in CP slave is connected to the=0D @@ -23,3 +31,31 @@ &cp0_rtc {=0D status =3D "disabled";=0D };=0D +=0D +&cp0_sata0 {=0D + iommus =3D <&smmu 0x444>;=0D +};=0D +=0D +&cp0_sdhci0 {=0D + iommus =3D <&smmu 0x445>;=0D +};=0D +=0D +&cp0_usb3_0 {=0D + iommus =3D <&smmu 0x440>;=0D +};=0D +=0D +&cp0_usb3_1 {=0D + iommus =3D <&smmu 0x441>;=0D +};=0D +=0D +&cp1_sata0 {=0D + iommus =3D <&smmu 0x454>;=0D +};=0D +=0D +&cp1_usb3_0 {=0D + iommus =3D <&smmu 0x450>;=0D +};=0D +=0D +&cp1_usb3_1 {=0D + iommus =3D <&smmu 0x451>;=0D +};=0D diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi b/Silic= on/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi index 81967e2..2ee35fa 100644 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-80x0.dtsi @@ -19,44 +19,44 @@ /*=0D * Instantiate the master CP110=0D */=0D -#define CP110_NAME cp0=0D -#define CP110_BASE f2000000=0D -#define CP110_PCIE_IO_BASE 0xf9000000=0D -#define CP110_PCIE_MEM_BASE 0xf6000000=0D -#define CP110_PCIE0_BASE f2600000=0D -#define CP110_PCIE1_BASE f2620000=0D -#define CP110_PCIE2_BASE f2640000=0D +#define CP11X_NAME cp0=0D +#define CP11X_BASE f2000000=0D +#define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000))=0D +#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000=0D +#define CP11X_PCIE0_BASE f2600000=0D +#define CP11X_PCIE1_BASE f2620000=0D +#define CP11X_PCIE2_BASE f2640000=0D =0D #include "armada-cp110.dtsi"=0D =0D -#undef CP110_NAME=0D -#undef CP110_BASE=0D -#undef CP110_PCIE_IO_BASE=0D -#undef CP110_PCIE_MEM_BASE=0D -#undef CP110_PCIE0_BASE=0D -#undef CP110_PCIE1_BASE=0D -#undef CP110_PCIE2_BASE=0D +#undef CP11X_NAME=0D +#undef CP11X_BASE=0D +#undef CP11X_PCIEx_MEM_BASE=0D +#undef CP11X_PCIEx_MEM_SIZE=0D +#undef CP11X_PCIE0_BASE=0D +#undef CP11X_PCIE1_BASE=0D +#undef CP11X_PCIE2_BASE=0D =0D /*=0D * Instantiate the slave CP110=0D */=0D -#define CP110_NAME cp1=0D -#define CP110_BASE f4000000=0D -#define CP110_PCIE_IO_BASE 0xfd000000=0D -#define CP110_PCIE_MEM_BASE 0xfa000000=0D -#define CP110_PCIE0_BASE f4600000=0D -#define CP110_PCIE1_BASE f4620000=0D -#define CP110_PCIE2_BASE f4640000=0D +#define CP11X_NAME cp1=0D +#define CP11X_BASE f4000000=0D +#define CP11X_PCIEx_MEM_BASE(iface) (0xfa000000 + (iface * 0x1000000))=0D +#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000=0D +#define CP11X_PCIE0_BASE f4600000=0D +#define CP11X_PCIE1_BASE f4620000=0D +#define CP11X_PCIE2_BASE f4640000=0D =0D #include "armada-cp110.dtsi"=0D =0D -#undef CP110_NAME=0D -#undef CP110_BASE=0D -#undef CP110_PCIE_IO_BASE=0D -#undef CP110_PCIE_MEM_BASE=0D -#undef CP110_PCIE0_BASE=0D -#undef CP110_PCIE1_BASE=0D -#undef CP110_PCIE2_BASE=0D +#undef CP11X_NAME=0D +#undef CP11X_BASE=0D +#undef CP11X_PCIEx_MEM_BASE=0D +#undef CP11X_PCIEx_MEM_SIZE=0D +#undef CP11X_PCIE0_BASE=0D +#undef CP11X_PCIE1_BASE=0D +#undef CP11X_PCIE2_BASE=0D =0D /* The 80x0 has two CP blocks, but uses only one block from each. */=0D &cp1_gpio1 {=0D diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi b= /Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi index 5985843..0cd8e7e 100644 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-dual.dtsi @@ -15,17 +15,47 @@ #address-cells =3D <1>;=0D #size-cells =3D <0>;=0D =0D - cpu@0 {=0D + cpu0: cpu@0 {=0D device_type =3D "cpu";=0D - compatible =3D "arm,cortex-a72", "arm,armv8";=0D + compatible =3D "arm,cortex-a72";=0D reg =3D <0x000>;=0D enable-method =3D "psci";=0D + #cooling-cells =3D <2>;=0D + clocks =3D <&cpu_clk 0>;=0D + i-cache-size =3D <0xc000>;=0D + i-cache-line-size =3D <64>;=0D + i-cache-sets =3D <256>;=0D + d-cache-size =3D <0x8000>;=0D + d-cache-line-size =3D <64>;=0D + d-cache-sets =3D <256>;=0D + next-level-cache =3D <&l2>;=0D };=0D - cpu@1 {=0D + cpu1: cpu@1 {=0D device_type =3D "cpu";=0D - compatible =3D "arm,cortex-a72", "arm,armv8";=0D + compatible =3D "arm,cortex-a72";=0D reg =3D <0x001>;=0D enable-method =3D "psci";=0D + #cooling-cells =3D <2>;=0D + clocks =3D <&cpu_clk 0>;=0D + i-cache-size =3D <0xc000>;=0D + i-cache-line-size =3D <64>;=0D + i-cache-sets =3D <256>;=0D + d-cache-size =3D <0x8000>;=0D + d-cache-line-size =3D <64>;=0D + d-cache-sets =3D <256>;=0D + next-level-cache =3D <&l2>;=0D };=0D +=0D + l2: l2-cache {=0D + compatible =3D "cache";=0D + cache-size =3D <0x80000>;=0D + cache-line-size =3D <64>;=0D + cache-sets =3D <512>;=0D + };=0D + };=0D +=0D + thermal-zones {=0D + /delete-node/ ap-thermal-cpu2;=0D + /delete-node/ ap-thermal-cpu3;=0D };=0D };=0D diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi b= /Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi index bae0ed9..3b48a13 100644 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806-quad.dtsi @@ -15,29 +15,79 @@ #address-cells =3D <1>;=0D #size-cells =3D <0>;=0D =0D - cpu@0 {=0D + cpu0: cpu@0 {=0D device_type =3D "cpu";=0D - compatible =3D "arm,cortex-a72", "arm,armv8";=0D + compatible =3D "arm,cortex-a72";=0D reg =3D <0x000>;=0D enable-method =3D "psci";=0D + #cooling-cells =3D <2>;=0D + clocks =3D <&cpu_clk 0>;=0D + i-cache-size =3D <0xc000>;=0D + i-cache-line-size =3D <64>;=0D + i-cache-sets =3D <256>;=0D + d-cache-size =3D <0x8000>;=0D + d-cache-line-size =3D <64>;=0D + d-cache-sets =3D <256>;=0D + next-level-cache =3D <&l2_0>;=0D };=0D - cpu@1 {=0D + cpu1: cpu@1 {=0D device_type =3D "cpu";=0D - compatible =3D "arm,cortex-a72", "arm,armv8";=0D + compatible =3D "arm,cortex-a72";=0D reg =3D <0x001>;=0D enable-method =3D "psci";=0D + #cooling-cells =3D <2>;=0D + clocks =3D <&cpu_clk 0>;=0D + i-cache-size =3D <0xc000>;=0D + i-cache-line-size =3D <64>;=0D + i-cache-sets =3D <256>;=0D + d-cache-size =3D <0x8000>;=0D + d-cache-line-size =3D <64>;=0D + d-cache-sets =3D <256>;=0D + next-level-cache =3D <&l2_0>;=0D };=0D - cpu@100 {=0D + cpu2: cpu@100 {=0D device_type =3D "cpu";=0D - compatible =3D "arm,cortex-a72", "arm,armv8";=0D + compatible =3D "arm,cortex-a72";=0D reg =3D <0x100>;=0D enable-method =3D "psci";=0D + #cooling-cells =3D <2>;=0D + clocks =3D <&cpu_clk 1>;=0D + i-cache-size =3D <0xc000>;=0D + i-cache-line-size =3D <64>;=0D + i-cache-sets =3D <256>;=0D + d-cache-size =3D <0x8000>;=0D + d-cache-line-size =3D <64>;=0D + d-cache-sets =3D <256>;=0D + next-level-cache =3D <&l2_1>;=0D };=0D - cpu@101 {=0D + cpu3: cpu@101 {=0D device_type =3D "cpu";=0D - compatible =3D "arm,cortex-a72", "arm,armv8";=0D + compatible =3D "arm,cortex-a72";=0D reg =3D <0x101>;=0D enable-method =3D "psci";=0D + #cooling-cells =3D <2>;=0D + clocks =3D <&cpu_clk 1>;=0D + i-cache-size =3D <0xc000>;=0D + i-cache-line-size =3D <64>;=0D + i-cache-sets =3D <256>;=0D + d-cache-size =3D <0x8000>;=0D + d-cache-line-size =3D <64>;=0D + d-cache-sets =3D <256>;=0D + next-level-cache =3D <&l2_1>;=0D + };=0D +=0D + l2_0: l2-cache0 {=0D + compatible =3D "cache";=0D + cache-size =3D <0x80000>;=0D + cache-line-size =3D <64>;=0D + cache-sets =3D <512>;=0D + };=0D +=0D + l2_1: l2-cache1 {=0D + compatible =3D "cache";=0D + cache-size =3D <0x80000>;=0D + cache-line-size =3D <64>;=0D + cache-sets =3D <512>;=0D };=0D };=0D };=0D diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi b/Sili= con/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi index 66124bf..59641de 100644 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap806.dtsi @@ -5,260 +5,26 @@ * Device Tree file for Marvell Armada AP806.=0D */=0D =0D -#define IRQ_TYPE_LEVEL_HIGH (1 << 2)=0D -#define IRQ_TYPE_LEVEL_LOW (1 << 3)=0D -=0D -#define GIC_SPI 0=0D -#define GIC_PPI 1=0D -=0D -#define GIC_CPU_MASK_RAW(x) ((x) << 8)=0D -#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1)=0D -=0D -/dts-v1/;=0D +#define AP_NAME ap806=0D +#include "armada-ap80x.dtsi"=0D =0D / {=0D model =3D "Marvell Armada AP806";=0D compatible =3D "marvell,armada-ap806";=0D - #address-cells =3D <2>;=0D - #size-cells =3D <2>;=0D -=0D - aliases {=0D - serial0 =3D &uart0;=0D - serial1 =3D &uart1;=0D - gpio0 =3D &ap_gpio;=0D - spi0 =3D &spi0;=0D - };=0D +};=0D =0D - psci {=0D - compatible =3D "arm,psci-0.2";=0D - method =3D "smc";=0D +&ap_syscon0 {=0D + ap_clk: clock {=0D + compatible =3D "marvell,ap806-clock";=0D + #clock-cells =3D <1>;=0D };=0D +};=0D =0D - ap806 {=0D - #address-cells =3D <2>;=0D - #size-cells =3D <2>;=0D - compatible =3D "simple-bus";=0D - interrupt-parent =3D <&gic>;=0D - ranges;=0D -=0D - config-space@f0000000 {=0D - #address-cells =3D <1>;=0D - #size-cells =3D <1>;=0D - compatible =3D "simple-bus";=0D - ranges =3D <0x0 0x0 0xf0000000 0x1000000>;=0D -=0D - gic: interrupt-controller@210000 {=0D - compatible =3D "arm,gic-400";=0D - #interrupt-cells =3D <3>;=0D - #address-cells =3D <1>;=0D - #size-cells =3D <1>;=0D - ranges;=0D - interrupt-controller;=0D - interrupts =3D ;=0D - reg =3D <0x210000 0x10000>,=0D - <0x220000 0x20000>,=0D - <0x240000 0x20000>,=0D - <0x260000 0x20000>;=0D -=0D - gic_v2m0: v2m@280000 {=0D - compatible =3D "arm,gic-v2m-frame"= ;=0D - msi-controller;=0D - reg =3D <0x280000 0x1000>;=0D - arm,msi-base-spi =3D <160>;=0D - arm,msi-num-spis =3D <32>;=0D - };=0D - gic_v2m1: v2m@290000 {=0D - compatible =3D "arm,gic-v2m-frame"= ;=0D - msi-controller;=0D - reg =3D <0x290000 0x1000>;=0D - arm,msi-base-spi =3D <192>;=0D - arm,msi-num-spis =3D <32>;=0D - };=0D - gic_v2m2: v2m@2a0000 {=0D - compatible =3D "arm,gic-v2m-frame"= ;=0D - msi-controller;=0D - reg =3D <0x2a0000 0x1000>;=0D - arm,msi-base-spi =3D <224>;=0D - arm,msi-num-spis =3D <32>;=0D - };=0D - gic_v2m3: v2m@2b0000 {=0D - compatible =3D "arm,gic-v2m-frame"= ;=0D - msi-controller;=0D - reg =3D <0x2b0000 0x1000>;=0D - arm,msi-base-spi =3D <256>;=0D - arm,msi-num-spis =3D <32>;=0D - };=0D - };=0D -=0D - timer {=0D - compatible =3D "arm,armv8-timer";=0D - interrupts =3D ,=0D - ,=0D - ,=0D - ;=0D - };=0D -=0D - pmu {=0D - compatible =3D "arm,cortex-a72-pmu";=0D - interrupt-parent =3D <&pic>;=0D - interrupts =3D <17>;=0D - };=0D -=0D - odmi: odmi@300000 {=0D - compatible =3D "marvell,odmi-controller";= =0D - interrupt-controller;=0D - msi-controller;=0D - marvell,odmi-frames =3D <4>;=0D - reg =3D <0x300000 0x4000>,=0D - <0x304000 0x4000>,=0D - <0x308000 0x4000>,=0D - <0x30C000 0x4000>;=0D - marvell,spi-base =3D <128>, <136>, <144>, = <152>;=0D - };=0D -=0D - gicp: gicp@3f0040 {=0D - compatible =3D "marvell,ap806-gicp";=0D - reg =3D <0x3f0040 0x10>;=0D - marvell,spi-ranges =3D <64 64>, <288 64>;= =0D - msi-controller;=0D - };=0D -=0D - pic: interrupt-controller@3f0100 {=0D - compatible =3D "marvell,armada-8k-pic";=0D - reg =3D <0x3f0100 0x10>;=0D - #interrupt-cells =3D <1>;=0D - interrupt-controller;=0D - interrupts =3D ;=0D - };=0D -=0D - xor@400000 {=0D - compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2";=0D - reg =3D <0x400000 0x1000>,=0D - <0x410000 0x1000>;=0D - msi-parent =3D <&gic_v2m0>;=0D - clocks =3D <&ap_clk 3>;=0D - dma-coherent;=0D - };=0D -=0D - xor@420000 {=0D - compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2";=0D - reg =3D <0x420000 0x1000>,=0D - <0x430000 0x1000>;=0D - msi-parent =3D <&gic_v2m0>;=0D - clocks =3D <&ap_clk 3>;=0D - dma-coherent;=0D - };=0D -=0D - xor@440000 {=0D - compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2";=0D - reg =3D <0x440000 0x1000>,=0D - <0x450000 0x1000>;=0D - msi-parent =3D <&gic_v2m0>;=0D - clocks =3D <&ap_clk 3>;=0D - dma-coherent;=0D - };=0D -=0D - xor@460000 {=0D - compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2";=0D - reg =3D <0x460000 0x1000>,=0D - <0x470000 0x1000>;=0D - msi-parent =3D <&gic_v2m0>;=0D - clocks =3D <&ap_clk 3>;=0D - dma-coherent;=0D - };=0D -=0D - spi0: spi@510600 {=0D - compatible =3D "marvell,armada-380-spi";=0D - reg =3D <0x510600 0x50>;=0D - #address-cells =3D <1>;=0D - #size-cells =3D <0>;=0D - interrupts =3D ;=0D - clocks =3D <&ap_clk 3>;=0D - status =3D "disabled";=0D - };=0D -=0D - i2c0: i2c@511000 {=0D - compatible =3D "marvell,mv78230-i2c";=0D - reg =3D <0x511000 0x20>;=0D - #address-cells =3D <1>;=0D - #size-cells =3D <0>;=0D - interrupts =3D ;=0D - timeout-ms =3D <1000>;=0D - clocks =3D <&ap_clk 3>;=0D - status =3D "disabled";=0D - };=0D -=0D - uart0: serial@512000 {=0D - compatible =3D "snps,dw-apb-uart";=0D - reg =3D <0x512000 0x100>;=0D - reg-shift =3D <2>;=0D - interrupts =3D ;=0D - reg-io-width =3D <1>;=0D - clocks =3D <&ap_clk 3>;=0D - status =3D "disabled";=0D - };=0D -=0D - uart1: serial@512100 {=0D - compatible =3D "snps,dw-apb-uart";=0D - reg =3D <0x512100 0x100>;=0D - reg-shift =3D <2>;=0D - interrupts =3D ;=0D - reg-io-width =3D <1>;=0D - clocks =3D <&ap_clk 3>;=0D - status =3D "disabled";=0D -=0D - };=0D -=0D - watchdog: watchdog@610000 {=0D - compatible =3D "arm,sbsa-gwdt";=0D - reg =3D <0x610000 0x1000>, <0x600000 0x100= 0>;=0D - interrupts =3D ;=0D - };=0D -=0D - ap_sdhci0: sdhci@6e0000 {=0D - compatible =3D "marvell,armada-ap806-sdhci= ";=0D - reg =3D <0x6e0000 0x300>;=0D - interrupts =3D ;=0D - clock-names =3D "core";=0D - clocks =3D <&ap_clk 4>;=0D - dma-coherent;=0D - marvell,xenon-phy-slow-mode;=0D - status =3D "disabled";=0D - };=0D -=0D - ap_syscon: system-controller@6f4000 {=0D - compatible =3D "syscon", "simple-mfd";=0D - reg =3D <0x6f4000 0x2000>;=0D -=0D - ap_clk: clock {=0D - compatible =3D "marvell,ap806-cloc= k";=0D - #clock-cells =3D <1>;=0D - };=0D -=0D - ap_pinctrl: pinctrl {=0D - compatible =3D "marvell,ap806-pinc= trl";=0D -=0D - uart0_pins: uart0-pins {=0D - marvell,pins =3D "mpp11", = "mpp19";=0D - marvell,function =3D "uart= 0";=0D - };=0D - };=0D -=0D - ap_gpio: gpio@1040 {=0D - compatible =3D "marvell,armada-8k-= gpio";=0D - offset =3D <0x1040>;=0D - ngpios =3D <20>;=0D - gpio-controller;=0D - #gpio-cells =3D <2>;=0D - gpio-ranges =3D <&ap_pinctrl 0 0 2= 0>;=0D - };=0D - };=0D -=0D - ap_thermal: thermal@6f808c {=0D - compatible =3D "marvell,armada-ap806-therm= al";=0D - reg =3D <0x6f808c 0x4>,=0D - <0x6f8084 0x8>;=0D - };=0D - };=0D +&ap_syscon1 {=0D + cpu_clk: clock-cpu@278 {=0D + compatible =3D "marvell,ap806-cpu-clock";=0D + clocks =3D <&ap_clk 0>, <&ap_clk 1>;=0D + #clock-cells =3D <1>;=0D + reg =3D <0x278 0xa30>;=0D };=0D };=0D diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807-quad.dtsi b= /Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807-quad.dtsi new file mode 100644 index 0000000..6222569 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807-quad.dtsi @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)=0D +/*=0D + * Device Tree file for Marvell Armada AP807 Quad=0D + *=0D + * Copyright (C) 2019 Marvell Technology Group Ltd.=0D + */=0D +=0D +#include "armada-ap807.dtsi"=0D +=0D +/ {=0D + model =3D "Marvell Armada AP807 Quad";=0D + compatible =3D "marvell,armada-ap807-quad", "marvell,armada-ap807"= ;=0D +=0D + cpus {=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D +=0D + cpu0: cpu@0 {=0D + device_type =3D "cpu";=0D + compatible =3D "arm,cortex-a72";=0D + reg =3D <0x000>;=0D + enable-method =3D "psci";=0D + #cooling-cells =3D <2>;=0D + clocks =3D <&cpu_clk 0>;=0D + i-cache-size =3D <0xc000>;=0D + i-cache-line-size =3D <64>;=0D + i-cache-sets =3D <256>;=0D + d-cache-size =3D <0x8000>;=0D + d-cache-line-size =3D <64>;=0D + d-cache-sets =3D <256>;=0D + next-level-cache =3D <&l2_0>;=0D + };=0D + cpu1: cpu@1 {=0D + device_type =3D "cpu";=0D + compatible =3D "arm,cortex-a72";=0D + reg =3D <0x001>;=0D + enable-method =3D "psci";=0D + #cooling-cells =3D <2>;=0D + clocks =3D <&cpu_clk 0>;=0D + i-cache-size =3D <0xc000>;=0D + i-cache-line-size =3D <64>;=0D + i-cache-sets =3D <256>;=0D + d-cache-size =3D <0x8000>;=0D + d-cache-line-size =3D <64>;=0D + d-cache-sets =3D <256>;=0D + next-level-cache =3D <&l2_0>;=0D + };=0D + cpu2: cpu@100 {=0D + device_type =3D "cpu";=0D + compatible =3D "arm,cortex-a72";=0D + reg =3D <0x100>;=0D + enable-method =3D "psci";=0D + #cooling-cells =3D <2>;=0D + clocks =3D <&cpu_clk 1>;=0D + i-cache-size =3D <0xc000>;=0D + i-cache-line-size =3D <64>;=0D + i-cache-sets =3D <256>;=0D + d-cache-size =3D <0x8000>;=0D + d-cache-line-size =3D <64>;=0D + d-cache-sets =3D <256>;=0D + next-level-cache =3D <&l2_1>;=0D + };=0D + cpu3: cpu@101 {=0D + device_type =3D "cpu";=0D + compatible =3D "arm,cortex-a72";=0D + reg =3D <0x101>;=0D + enable-method =3D "psci";=0D + #cooling-cells =3D <2>;=0D + clocks =3D <&cpu_clk 1>;=0D + i-cache-size =3D <0xc000>;=0D + i-cache-line-size =3D <64>;=0D + i-cache-sets =3D <256>;=0D + d-cache-size =3D <0x8000>;=0D + d-cache-line-size =3D <64>;=0D + d-cache-sets =3D <256>;=0D + next-level-cache =3D <&l2_1>;=0D + };=0D +=0D + l2_0: l2-cache0 {=0D + compatible =3D "cache";=0D + cache-size =3D <0x80000>;=0D + cache-line-size =3D <64>;=0D + cache-sets =3D <512>;=0D + };=0D +=0D + l2_1: l2-cache1 {=0D + compatible =3D "cache";=0D + cache-size =3D <0x80000>;=0D + cache-line-size =3D <64>;=0D + cache-sets =3D <512>;=0D + };=0D + };=0D +};=0D diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807.dtsi b/Sili= con/Marvell/Armada7k8k/DeviceTree/armada-ap807.dtsi new file mode 100644 index 0000000..b42dc3a --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)=0D +/*=0D + * Device Tree file for Marvell Armada AP807=0D + *=0D + * Copyright (C) 2019 Marvell Technology Group Ltd.=0D + */=0D +=0D +#define AP_NAME ap807=0D +#include "armada-ap80x.dtsi"=0D +=0D +/ {=0D + model =3D "Marvell Armada AP807";=0D + compatible =3D "marvell,armada-ap807";=0D +};=0D +=0D +&ap_syscon0 {=0D + ap_clk: clock {=0D + compatible =3D "marvell,ap807-clock";=0D + #clock-cells =3D <1>;=0D + };=0D +};=0D +=0D +&ap_syscon1 {=0D + cpu_clk: clock-cpu {=0D + compatible =3D "marvell,ap807-cpu-clock";=0D + clocks =3D <&ap_clk 0>, <&ap_clk 1>;=0D + #clock-cells =3D <1>;=0D + };=0D +};=0D +=0D +&ap_sdhci0 {=0D + compatible =3D "marvell,armada-ap807-sdhci";=0D +};=0D diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap80x.dtsi b/Sili= con/Marvell/Armada7k8k/DeviceTree/armada-ap80x.dtsi new file mode 100644 index 0000000..c2a7cef --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap80x.dtsi @@ -0,0 +1,470 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)=0D +/*=0D + * Copyright (C) 2019 Marvell Technology Group Ltd.=0D + *=0D + * Device Tree file for Marvell Armada AP80x.=0D + */=0D +=0D +#define IRQ_TYPE_LEVEL_HIGH (1 << 2)=0D +#define IRQ_TYPE_LEVEL_LOW (1 << 3)=0D +=0D +#define GIC_SPI 0=0D +#define GIC_PPI 1=0D +=0D +#define GIC_CPU_MASK_RAW(x) ((x) << 8)=0D +#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1)=0D +=0D +#define GPIO_ACTIVE_HIGH 0=0D +#define GPIO_ACTIVE_LOW 1=0D +=0D +/dts-v1/;=0D +=0D +/ {=0D + #address-cells =3D <2>;=0D + #size-cells =3D <2>;=0D +=0D + aliases {=0D + serial0 =3D &uart0;=0D + serial1 =3D &uart1;=0D + gpio0 =3D &ap_gpio;=0D + spi0 =3D &spi0;=0D + };=0D +=0D + psci {=0D + compatible =3D "arm,psci-0.2";=0D + method =3D "smc";=0D + };=0D +=0D + reserved-memory {=0D + #address-cells =3D <2>;=0D + #size-cells =3D <2>;=0D + ranges;=0D +=0D + /*=0D + * This area matches the mapping done with a=0D + * mainline U-Boot, and should be updated by the=0D + * bootloader.=0D + */=0D +=0D + psci-area@4000000 {=0D + reg =3D <0x0 0x4000000 0x0 0x200000>;=0D + no-map;=0D + };=0D + };=0D +=0D + AP_NAME {=0D + #address-cells =3D <2>;=0D + #size-cells =3D <2>;=0D + compatible =3D "simple-bus";=0D + interrupt-parent =3D <&gic>;=0D + ranges;=0D +=0D + config-space@f0000000 {=0D + #address-cells =3D <1>;=0D + #size-cells =3D <1>;=0D + compatible =3D "simple-bus";=0D + ranges =3D <0x0 0x0 0xf0000000 0x1000000>;=0D +=0D + smmu: iommu@5000000 {=0D + compatible =3D "marvell,ap806-smmu-500", "= arm,mmu-500";=0D + reg =3D <0x100000 0x100000>;=0D + dma-coherent;=0D + #iommu-cells =3D <1>;=0D + #global-interrupts =3D <1>;=0D + interrupts =3D ,=0D + ,=0D + ,=0D + ,=0D + ,=0D + ,=0D + ,=0D + ,=0D + ;=0D + status =3D "disabled";=0D + };=0D +=0D + gic: interrupt-controller@210000 {=0D + compatible =3D "arm,gic-400";=0D + #interrupt-cells =3D <3>;=0D + #address-cells =3D <1>;=0D + #size-cells =3D <1>;=0D + ranges;=0D + interrupt-controller;=0D + interrupts =3D ;=0D + reg =3D <0x210000 0x10000>,=0D + <0x220000 0x20000>,=0D + <0x240000 0x20000>,=0D + <0x260000 0x20000>;=0D +=0D + gic_v2m0: v2m@280000 {=0D + compatible =3D "arm,gic-v2m-frame"= ;=0D + msi-controller;=0D + reg =3D <0x280000 0x1000>;=0D + arm,msi-base-spi =3D <160>;=0D + arm,msi-num-spis =3D <32>;=0D + };=0D + gic_v2m1: v2m@290000 {=0D + compatible =3D "arm,gic-v2m-frame"= ;=0D + msi-controller;=0D + reg =3D <0x290000 0x1000>;=0D + arm,msi-base-spi =3D <192>;=0D + arm,msi-num-spis =3D <32>;=0D + };=0D + gic_v2m2: v2m@2a0000 {=0D + compatible =3D "arm,gic-v2m-frame"= ;=0D + msi-controller;=0D + reg =3D <0x2a0000 0x1000>;=0D + arm,msi-base-spi =3D <224>;=0D + arm,msi-num-spis =3D <32>;=0D + };=0D + gic_v2m3: v2m@2b0000 {=0D + compatible =3D "arm,gic-v2m-frame"= ;=0D + msi-controller;=0D + reg =3D <0x2b0000 0x1000>;=0D + arm,msi-base-spi =3D <256>;=0D + arm,msi-num-spis =3D <32>;=0D + };=0D + };=0D +=0D + timer {=0D + compatible =3D "arm,armv8-timer";=0D + interrupts =3D ,=0D + ,=0D + ,=0D + ;=0D + };=0D +=0D + pmu {=0D + compatible =3D "arm,cortex-a72-pmu";=0D + interrupt-parent =3D <&pic>;=0D + interrupts =3D <17>;=0D + };=0D +=0D + odmi: odmi@300000 {=0D + compatible =3D "marvell,odmi-controller";= =0D + interrupt-controller;=0D + msi-controller;=0D + marvell,odmi-frames =3D <4>;=0D + reg =3D <0x300000 0x4000>,=0D + <0x304000 0x4000>,=0D + <0x308000 0x4000>,=0D + <0x30C000 0x4000>;=0D + marvell,spi-base =3D <128>, <136>, <144>, = <152>;=0D + };=0D +=0D + gicp: gicp@3f0040 {=0D + compatible =3D "marvell,ap806-gicp";=0D + reg =3D <0x3f0040 0x10>;=0D + marvell,spi-ranges =3D <64 64>, <288 64>;= =0D + msi-controller;=0D + };=0D +=0D + pic: interrupt-controller@3f0100 {=0D + compatible =3D "marvell,armada-8k-pic";=0D + reg =3D <0x3f0100 0x10>;=0D + #interrupt-cells =3D <1>;=0D + interrupt-controller;=0D + interrupts =3D ;=0D + };=0D +=0D + sei: interrupt-controller@3f0200 {=0D + compatible =3D "marvell,ap806-sei";=0D + reg =3D <0x3f0200 0x40>;=0D + interrupts =3D ;=0D + #interrupt-cells =3D <1>;=0D + interrupt-controller;=0D + msi-controller;=0D + };=0D +=0D + xor@400000 {=0D + compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2";=0D + reg =3D <0x400000 0x1000>,=0D + <0x410000 0x1000>;=0D + msi-parent =3D <&gic_v2m0>;=0D + clocks =3D <&ap_clk 3>;=0D + dma-coherent;=0D + };=0D +=0D + xor@420000 {=0D + compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2";=0D + reg =3D <0x420000 0x1000>,=0D + <0x430000 0x1000>;=0D + msi-parent =3D <&gic_v2m0>;=0D + clocks =3D <&ap_clk 3>;=0D + dma-coherent;=0D + };=0D +=0D + xor@440000 {=0D + compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2";=0D + reg =3D <0x440000 0x1000>,=0D + <0x450000 0x1000>;=0D + msi-parent =3D <&gic_v2m0>;=0D + clocks =3D <&ap_clk 3>;=0D + dma-coherent;=0D + };=0D +=0D + xor@460000 {=0D + compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2";=0D + reg =3D <0x460000 0x1000>,=0D + <0x470000 0x1000>;=0D + msi-parent =3D <&gic_v2m0>;=0D + clocks =3D <&ap_clk 3>;=0D + dma-coherent;=0D + };=0D +=0D + spi0: spi@510600 {=0D + compatible =3D "marvell,armada-380-spi";=0D + reg =3D <0x510600 0x50>;=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + interrupts =3D ;=0D + clocks =3D <&ap_clk 3>;=0D + status =3D "disabled";=0D + };=0D +=0D + i2c0: i2c@511000 {=0D + compatible =3D "marvell,mv78230-i2c";=0D + reg =3D <0x511000 0x20>;=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + interrupts =3D ;=0D + clocks =3D <&ap_clk 3>;=0D + status =3D "disabled";=0D + };=0D +=0D + uart0: serial@512000 {=0D + compatible =3D "snps,dw-apb-uart";=0D + reg =3D <0x512000 0x100>;=0D + reg-shift =3D <2>;=0D + interrupts =3D ;=0D + reg-io-width =3D <1>;=0D + clocks =3D <&ap_clk 3>;=0D + status =3D "disabled";=0D + };=0D +=0D + uart1: serial@512100 {=0D + compatible =3D "snps,dw-apb-uart";=0D + reg =3D <0x512100 0x100>;=0D + reg-shift =3D <2>;=0D + interrupts =3D ;=0D + reg-io-width =3D <1>;=0D + clocks =3D <&ap_clk 3>;=0D + status =3D "disabled";=0D +=0D + };=0D +=0D + watchdog: watchdog@610000 {=0D + compatible =3D "arm,sbsa-gwdt";=0D + reg =3D <0x610000 0x1000>, <0x600000 0x100= 0>;=0D + interrupts =3D ;=0D + };=0D +=0D + ap_sdhci0: sdhci@6e0000 {=0D + compatible =3D "marvell,armada-ap806-sdhci= ";=0D + reg =3D <0x6e0000 0x300>;=0D + interrupts =3D ;=0D + clock-names =3D "core";=0D + clocks =3D <&ap_clk 4>;=0D + dma-coherent;=0D + marvell,xenon-phy-slow-mode;=0D + status =3D "disabled";=0D + };=0D +=0D + ap_syscon0: system-controller@6f4000 {=0D + compatible =3D "syscon", "simple-mfd";=0D + reg =3D <0x6f4000 0x2000>;=0D +=0D + ap_pinctrl: pinctrl {=0D + compatible =3D "marvell,ap806-pinc= trl";=0D +=0D + uart0_pins: uart0-pins {=0D + marvell,pins =3D "mpp11", = "mpp19";=0D + marvell,function =3D "uart= 0";=0D + };=0D + };=0D +=0D + ap_gpio: gpio@1040 {=0D + compatible =3D "marvell,armada-8k-= gpio";=0D + offset =3D <0x1040>;=0D + ngpios =3D <20>;=0D + gpio-controller;=0D + #gpio-cells =3D <2>;=0D + gpio-ranges =3D <&ap_pinctrl 0 0 2= 0>;=0D + };=0D + };=0D +=0D + ap_syscon1: system-controller@6f8000 {=0D + compatible =3D "syscon", "simple-mfd";=0D + reg =3D <0x6f8000 0x1000>;=0D + #address-cells =3D <1>;=0D + #size-cells =3D <1>;=0D +=0D + ap_thermal: thermal-sensor@80 {=0D + compatible =3D "marvell,armada-ap8= 06-thermal";=0D + reg =3D <0x80 0x10>;=0D + interrupt-parent =3D <&sei>;=0D + interrupts =3D <18>;=0D + #thermal-sensor-cells =3D <1>;=0D + };=0D + };=0D + };=0D + };=0D +=0D + /*=0D + * The thermal IP features one internal sensor plus, if applicable= , one=0D + * remote channel wired to one sensor per CPU.=0D + *=0D + * Only one thermal zone per AP/CP may trigger interrupts at a tim= e, the=0D + * first one that will have a critical trip point will be chosen.= =0D + */=0D + thermal-zones {=0D + ap_thermal_ic: ap-thermal-ic {=0D + polling-delay-passive =3D <0>; /* Interrupt driven= */=0D + polling-delay =3D <0>; /* Interrupt driven */=0D +=0D + thermal-sensors =3D <&ap_thermal 0>;=0D +=0D + trips {=0D + ap_crit: ap-crit {=0D + temperature =3D <100000>; /* mC de= grees */=0D + hysteresis =3D <2000>; /* mC degre= es */=0D + type =3D "critical";=0D + };=0D + };=0D +=0D + cooling-maps { };=0D + };=0D +=0D + ap_thermal_cpu0: ap-thermal-cpu0 {=0D + polling-delay-passive =3D <1000>;=0D + polling-delay =3D <1000>;=0D +=0D + thermal-sensors =3D <&ap_thermal 1>;=0D +=0D + trips {=0D + cpu0_hot: cpu0-hot {=0D + temperature =3D <85000>;=0D + hysteresis =3D <2000>;=0D + type =3D "passive";=0D + };=0D + cpu0_emerg: cpu0-emerg {=0D + temperature =3D <95000>;=0D + hysteresis =3D <2000>;=0D + type =3D "passive";=0D + };=0D + };=0D +=0D + cooling-maps {=0D + map0_hot: map0-hot {=0D + trip =3D <&cpu0_hot>;=0D + cooling-device =3D <&cpu0 1 2>,=0D + <&cpu1 1 2>;=0D + };=0D + map0_emerg: map0-ermerg {=0D + trip =3D <&cpu0_emerg>;=0D + cooling-device =3D <&cpu0 3 3>,=0D + <&cpu1 3 3>;=0D + };=0D + };=0D + };=0D +=0D + ap_thermal_cpu1: ap-thermal-cpu1 {=0D + polling-delay-passive =3D <1000>;=0D + polling-delay =3D <1000>;=0D +=0D + thermal-sensors =3D <&ap_thermal 2>;=0D +=0D + trips {=0D + cpu1_hot: cpu1-hot {=0D + temperature =3D <85000>;=0D + hysteresis =3D <2000>;=0D + type =3D "passive";=0D + };=0D + cpu1_emerg: cpu1-emerg {=0D + temperature =3D <95000>;=0D + hysteresis =3D <2000>;=0D + type =3D "passive";=0D + };=0D + };=0D +=0D + cooling-maps {=0D + map1_hot: map1-hot {=0D + trip =3D <&cpu1_hot>;=0D + cooling-device =3D <&cpu0 1 2>,=0D + <&cpu1 1 2>;=0D + };=0D + map1_emerg: map1-emerg {=0D + trip =3D <&cpu1_emerg>;=0D + cooling-device =3D <&cpu0 3 3>,=0D + <&cpu1 3 3>;=0D + };=0D + };=0D + };=0D +=0D + ap_thermal_cpu2: ap-thermal-cpu2 {=0D + polling-delay-passive =3D <1000>;=0D + polling-delay =3D <1000>;=0D +=0D + thermal-sensors =3D <&ap_thermal 3>;=0D +=0D + trips {=0D + cpu2_hot: cpu2-hot {=0D + temperature =3D <85000>;=0D + hysteresis =3D <2000>;=0D + type =3D "passive";=0D + };=0D + cpu2_emerg: cpu2-emerg {=0D + temperature =3D <95000>;=0D + hysteresis =3D <2000>;=0D + type =3D "passive";=0D + };=0D + };=0D +=0D + cooling-maps {=0D + map2_hot: map2-hot {=0D + trip =3D <&cpu2_hot>;=0D + cooling-device =3D <&cpu2 1 2>,=0D + <&cpu3 1 2>;=0D + };=0D + map2_emerg: map2-emerg {=0D + trip =3D <&cpu2_emerg>;=0D + cooling-device =3D <&cpu2 3 3>,=0D + <&cpu3 3 3>;=0D + };=0D + };=0D + };=0D +=0D + ap_thermal_cpu3: ap-thermal-cpu3 {=0D + polling-delay-passive =3D <1000>;=0D + polling-delay =3D <1000>;=0D +=0D + thermal-sensors =3D <&ap_thermal 4>;=0D +=0D + trips {=0D + cpu3_hot: cpu3-hot {=0D + temperature =3D <85000>;=0D + hysteresis =3D <2000>;=0D + type =3D "passive";=0D + };=0D + cpu3_emerg: cpu3-emerg {=0D + temperature =3D <95000>;=0D + hysteresis =3D <2000>;=0D + type =3D "passive";=0D + };=0D + };=0D +=0D + cooling-maps {=0D + map3_hot: map3-bhot {=0D + trip =3D <&cpu3_hot>;=0D + cooling-device =3D <&cpu2 1 2>,=0D + <&cpu3 1 2>;=0D + };=0D + map3_emerg: map3-emerg {=0D + trip =3D <&cpu3_emerg>;=0D + cooling-device =3D <&cpu2 3 3>,=0D + <&cpu3 3 3>;=0D + };=0D + };=0D + };=0D + };=0D +};=0D diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi b/Sil= icon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi index 8b610fd..f002499 100644 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-common.dtsi @@ -6,5 +6,6 @@ /* Common definitions used by Armada 7K/8K DTs */=0D #define PASTER(x, y) x ## y=0D #define EVALUATOR(x, y) PASTER(x, y)=0D -#define CP110_LABEL(name) EVALUATOR(CP110_NAME, EVALUATOR(_, name))=0D +#define CP11X_LABEL(name) EVALUATOR(CP11X_NAME, EVALUATOR(_, name))=0D +#define CP11X_NODE_NAME(name) EVALUATOR(CP11X_NAME, EVALUATOR(-, name))=0D #define ADDRESSIFY(addr) EVALUATOR(0x, addr)=0D diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi b/Sili= con/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi index 5e8e524..5799e98 100644 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp110.dtsi @@ -1,560 +1,12 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT)=0D /*=0D - * Copyright (C) 2016 Marvell Technology Group Ltd.=0D + * Copyright (C) 2019 Marvell Technology Group Ltd.=0D *=0D * Device Tree file for Marvell Armada CP110.=0D */=0D =0D -#include "armada-common.dtsi"=0D +#define CP11X_TYPE cp110=0D =0D -#define ICU_GRP_NSR 0x0=0D -#define ICU_GRP_SR 0x1=0D -#define ICU_GRP_SEI 0x4=0D -#define ICU_GRP_REI 0x5=0D +#include "armada-cp11x.dtsi"=0D =0D -#define CP110_PCIEx_IO_BASE(iface) (CP110_PCIE_IO_BASE + (iface * = 0x10000))=0D -#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIE_MEM_BASE + (iface *= 0x1000000))=0D -#define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) += 0xf00000)=0D -=0D -/ {=0D - /*=0D - * The contents of the node are defined below, in order to=0D - * save one indentation level=0D - */=0D - CP110_NAME: CP110_NAME { };=0D -};=0D -=0D -&CP110_NAME {=0D - #address-cells =3D <2>;=0D - #size-cells =3D <2>;=0D - compatible =3D "simple-bus";=0D - interrupt-parent =3D <&CP110_LABEL(icu)>;=0D - ranges;=0D -=0D - config-space@CP110_BASE {=0D - #address-cells =3D <1>;=0D - #size-cells =3D <1>;=0D - compatible =3D "simple-bus";=0D - ranges =3D <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>;=0D -=0D - CP110_LABEL(ethernet): ethernet@0 {=0D - compatible =3D "marvell,armada-7k-pp22";=0D - reg =3D <0x0 0x100000>, <0x129000 0xb000>;=0D - clocks =3D <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL= (ppv2_clk)>,=0D - <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL(c= ore_clk)>,=0D - <&CP110_LABEL(core_clk)>;=0D - clock-names =3D "pp_clk", "gop_clk",=0D - "mg_clk", "mg_core_clk", "axi_clk";= =0D - marvell,system-controller =3D <&CP110_LABEL(syscon= 0)>;=0D - status =3D "disabled";=0D - dma-coherent;=0D -=0D - CP110_LABEL(eth0): eth0 {=0D - interrupts =3D ,=0D - ,=0D - ,=0D - ,=0D - ,=0D - ;=0D - interrupt-names =3D "tx-cpu0", "tx-cpu1", = "tx-cpu2",=0D - "tx-cpu3", "rx-shared", "link";=0D - port-id =3D <0>;=0D - gop-port-id =3D <0>;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(eth1): eth1 {=0D - interrupts =3D ,=0D - ,=0D - ,=0D - ,=0D - ,=0D - ;=0D - interrupt-names =3D "tx-cpu0", "tx-cpu1", = "tx-cpu2",=0D - "tx-cpu3", "rx-shared", "link";=0D - port-id =3D <1>;=0D - gop-port-id =3D <2>;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(eth2): eth2 {=0D - interrupts =3D ,=0D - ,=0D - ,=0D - ,=0D - ,=0D - ;=0D - interrupt-names =3D "tx-cpu0", "tx-cpu1", = "tx-cpu2",=0D - "tx-cpu3", "rx-shared", "link";=0D - port-id =3D <2>;=0D - gop-port-id =3D <3>;=0D - status =3D "disabled";=0D - };=0D - };=0D -=0D - CP110_LABEL(comphy): phy@120000 {=0D - compatible =3D "marvell,comphy-cp110";=0D - reg =3D <0x120000 0x6000>;=0D - marvell,system-controller =3D <&CP110_LABEL(syscon= 0)>;=0D - #address-cells =3D <1>;=0D - #size-cells =3D <0>;=0D -=0D - CP110_LABEL(comphy0): phy@0 {=0D - reg =3D <0>;=0D - #phy-cells =3D <1>;=0D - };=0D -=0D - CP110_LABEL(comphy1): phy@1 {=0D - reg =3D <1>;=0D - #phy-cells =3D <1>;=0D - };=0D -=0D - CP110_LABEL(comphy2): phy@2 {=0D - reg =3D <2>;=0D - #phy-cells =3D <1>;=0D - };=0D -=0D - CP110_LABEL(comphy3): phy@3 {=0D - reg =3D <3>;=0D - #phy-cells =3D <1>;=0D - };=0D -=0D - CP110_LABEL(comphy4): phy@4 {=0D - reg =3D <4>;=0D - #phy-cells =3D <1>;=0D - };=0D -=0D - CP110_LABEL(comphy5): phy@5 {=0D - reg =3D <5>;=0D - #phy-cells =3D <1>;=0D - };=0D - };=0D -=0D - CP110_LABEL(mdio): mdio@12a200 {=0D - #address-cells =3D <1>;=0D - #size-cells =3D <0>;=0D - compatible =3D "marvell,orion-mdio";=0D - reg =3D <0x12a200 0x10>;=0D - clocks =3D <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL= (ppv2_clk)>,=0D - <&CP110_LABEL(core_clk)>, <&CP110_LABEL(c= ore_clk)>;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(xmdio): mdio@12a600 {=0D - #address-cells =3D <1>;=0D - #size-cells =3D <0>;=0D - compatible =3D "marvell,xmdio";=0D - reg =3D <0x12a600 0x10>;=0D - clocks =3D <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL= (ppv2_clk)>,=0D - <&CP110_LABEL(core_clk)>;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(icu): interrupt-controller@1e0000 {=0D - compatible =3D "marvell,cp110-icu";=0D - reg =3D <0x1e0000 0x440>;=0D - #interrupt-cells =3D <3>;=0D - interrupt-controller;=0D - msi-parent =3D <&gicp>;=0D - };=0D -=0D - CP110_LABEL(rtc): rtc@284000 {=0D - compatible =3D "marvell,armada-8k-rtc";=0D - reg =3D <0x284000 0x20>, <0x284080 0x24>;=0D - reg-names =3D "rtc", "rtc-soc";=0D - interrupts =3D ;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(thermal): thermal@400078 {=0D - compatible =3D "marvell,armada-cp110-thermal";=0D - reg =3D <0x400078 0x4>,=0D - <0x400070 0x8>;=0D - };=0D -=0D - CP110_LABEL(syscon0): system-controller@440000 {=0D - compatible =3D "syscon", "simple-mfd";=0D - reg =3D <0x440000 0x2000>;=0D -=0D - CP110_LABEL(clk): clock {=0D - compatible =3D "marvell,cp110-clock";=0D - status =3D "disabled";=0D - #clock-cells =3D <2>;=0D - };=0D -=0D - CP110_LABEL(gpio1): gpio@100 {=0D - compatible =3D "marvell,armada-8k-gpio";=0D - offset =3D <0x100>;=0D - ngpios =3D <32>;=0D - gpio-controller;=0D - #gpio-cells =3D <2>;=0D - gpio-ranges =3D <&CP110_LABEL(pinctrl) 0 0= 32>;=0D - interrupt-controller;=0D - interrupts =3D ,=0D - ,=0D - ,=0D - ;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(gpio2): gpio@140 {=0D - compatible =3D "marvell,armada-8k-gpio";=0D - offset =3D <0x140>;=0D - ngpios =3D <31>;=0D - gpio-controller;=0D - #gpio-cells =3D <2>;=0D - gpio-ranges =3D <&CP110_LABEL(pinctrl) 0 3= 2 31>;=0D - interrupt-controller;=0D - interrupts =3D ,=0D - ,=0D - ,=0D - ;=0D - status =3D "disabled";=0D - };=0D - };=0D -=0D - CP110_LABEL(usb3_0): usb3@500000 {=0D - compatible =3D "marvell,armada-8k-xhci",=0D - "generic-xhci";=0D - reg =3D <0x500000 0x4000>;=0D - dma-coherent;=0D - interrupts =3D ;=0D - clock-names =3D "core", "reg";=0D - clocks =3D <&CP110_LABEL(core_clk)>,=0D - <&CP110_LABEL(core_clk)>;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(usb3_1): usb3@510000 {=0D - compatible =3D "marvell,armada-8k-xhci",=0D - "generic-xhci";=0D - reg =3D <0x510000 0x4000>;=0D - dma-coherent;=0D - interrupts =3D ;=0D - clock-names =3D "core", "reg";=0D - clocks =3D <&CP110_LABEL(core_clk)>,=0D - <&CP110_LABEL(core_clk)>;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(sata0): sata@540000 {=0D - compatible =3D "marvell,armada-8k-ahci",=0D - "generic-ahci";=0D - reg =3D <0x540000 0x30000>;=0D - dma-coherent;=0D - interrupts =3D ;=0D - clocks =3D <&CP110_LABEL(core_clk)>,=0D - <&CP110_LABEL(core_clk)>;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(xor0): xor@6a0000 {=0D - compatible =3D "marvell,armada-7k-xor", "marvell,x= or-v2";=0D - reg =3D <0x6a0000 0x1000>, <0x6b0000 0x1000>;=0D - dma-coherent;=0D - msi-parent =3D <&gic_v2m0>;=0D - clock-names =3D "core", "reg";=0D - clocks =3D <&CP110_LABEL(core_clk)>,=0D - <&CP110_LABEL(x2core_clk)>;=0D - };=0D -=0D - CP110_LABEL(xor1): xor@6c0000 {=0D - compatible =3D "marvell,armada-7k-xor", "marvell,x= or-v2";=0D - reg =3D <0x6c0000 0x1000>, <0x6d0000 0x1000>;=0D - dma-coherent;=0D - msi-parent =3D <&gic_v2m0>;=0D - clock-names =3D "core", "reg";=0D - clocks =3D <&CP110_LABEL(core_clk)>,=0D - <&CP110_LABEL(x2core_clk)>;=0D - };=0D -=0D - CP110_LABEL(spi0): spi@700600 {=0D - compatible =3D "marvell,armada-380-spi";=0D - reg =3D <0x700600 0x50>;=0D - #address-cells =3D <0x1>;=0D - #size-cells =3D <0x0>;=0D - clock-names =3D "core", "axi";=0D - clocks =3D <&CP110_LABEL(slow_io_clk)>,=0D - <&CP110_LABEL(x2core_clk)>;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(spi1): spi@700680 {=0D - compatible =3D "marvell,armada-380-spi";=0D - reg =3D <0x700680 0x50>;=0D - #address-cells =3D <1>;=0D - #size-cells =3D <0>;=0D - clock-names =3D "core", "axi";=0D - clocks =3D <&CP110_LABEL(slow_io_clk)>,=0D - <&CP110_LABEL(x2core_clk)>;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(i2c0): i2c@701000 {=0D - compatible =3D "marvell,mv78230-i2c";=0D - reg =3D <0x701000 0x20>;=0D - #address-cells =3D <1>;=0D - #size-cells =3D <0>;=0D - interrupts =3D ;=0D - clock-names =3D "core", "reg";=0D - clocks =3D <&CP110_LABEL(slow_io_clk)>,=0D - <&CP110_LABEL(x2core_clk)>;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(i2c1): i2c@701100 {=0D - compatible =3D "marvell,mv78230-i2c";=0D - reg =3D <0x701100 0x20>;=0D - #address-cells =3D <1>;=0D - #size-cells =3D <0>;=0D - interrupts =3D ;=0D - clock-names =3D "core", "reg";=0D - clocks =3D <&CP110_LABEL(slow_io_clk)>,=0D - <&CP110_LABEL(x2core_clk)>;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(uart0): serial@702000 {=0D - compatible =3D "snps,dw-apb-uart";=0D - reg =3D <0x702000 0x100>;=0D - reg-shift =3D <2>;=0D - interrupts =3D ;=0D - reg-io-width =3D <1>;=0D - clock-names =3D "baudclk", "apb_pclk";=0D - clocks =3D <&CP110_LABEL(slow_io_clk)>,=0D - <&CP110_LABEL(x2core_clk)>;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(uart1): serial@702100 {=0D - compatible =3D "snps,dw-apb-uart";=0D - reg =3D <0x702100 0x100>;=0D - reg-shift =3D <2>;=0D - interrupts =3D ;=0D - reg-io-width =3D <1>;=0D - clock-names =3D "baudclk", "apb_pclk";=0D - clocks =3D <&CP110_LABEL(slow_io_clk)>,=0D - <&CP110_LABEL(x2core_clk)>;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(uart2): serial@702200 {=0D - compatible =3D "snps,dw-apb-uart";=0D - reg =3D <0x702200 0x100>;=0D - reg-shift =3D <2>;=0D - interrupts =3D ;=0D - reg-io-width =3D <1>;=0D - clock-names =3D "baudclk", "apb_pclk";=0D - clocks =3D <&CP110_LABEL(slow_io_clk)>,=0D - <&CP110_LABEL(x2core_clk)>;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(uart3): serial@702300 {=0D - compatible =3D "snps,dw-apb-uart";=0D - reg =3D <0x702300 0x100>;=0D - reg-shift =3D <2>;=0D - interrupts =3D ;=0D - reg-io-width =3D <1>;=0D - clock-names =3D "baudclk", "apb_pclk";=0D - clocks =3D <&CP110_LABEL(slow_io_clk)>,=0D - <&CP110_LABEL(x2core_clk)>;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(nand_controller): nand@720000 {=0D - /*=0D - * Due to the limitation of the pins available=0D - * this controller is only usable on the CPM=0D - * for A7K and on the CPS for A8K.=0D - */=0D - compatible =3D "marvell,armada-8k-nand-controller"= ,=0D - "marvell,armada370-nand-controller";=0D - reg =3D <0x720000 0x54>;=0D - #address-cells =3D <1>;=0D - #size-cells =3D <0>;=0D - interrupts =3D ;=0D - clock-names =3D "core", "reg";=0D - clocks =3D <&CP110_LABEL(nand_clk)>,=0D - <&CP110_LABEL(x2core_clk)>;=0D - marvell,system-controller =3D <&CP110_LABEL(syscon= 0)>;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(trng): trng@760000 {=0D - compatible =3D "marvell,armada-8k-rng",=0D - "inside-secure,safexcel-eip76";=0D - reg =3D <0x760000 0x7d>;=0D - interrupts =3D ;=0D - clock-names =3D "core", "reg";=0D - clocks =3D <&CP110_LABEL(x2core_clk)>,=0D - <&CP110_LABEL(x2core_clk)>;=0D - status =3D "okay";=0D - };=0D -=0D - CP110_LABEL(sdhci0): sdhci@780000 {=0D - compatible =3D "marvell,armada-cp110-sdhci";=0D - reg =3D <0x780000 0x300>;=0D - interrupts =3D ;=0D - clock-names =3D "core", "axi";=0D - clocks =3D <&CP110_LABEL(sdio_clk)>, <&CP110_LABEL= (core_clk)>;=0D - dma-coherent;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(crypto): crypto@800000 {=0D - compatible =3D "inside-secure,safexcel-eip197";=0D - reg =3D <0x800000 0x200000>;=0D - interrupts =3D ,=0D - ,=0D - ,=0D - ,=0D - ,=0D - ;=0D - interrupt-names =3D "mem", "ring0", "ring1",=0D - "ring2", "ring3", "eip";=0D - clock-names =3D "core", "reg";=0D - clocks =3D <&CP110_LABEL(x2core_clk)>,=0D - <&CP110_LABEL(x2core_clk)>;=0D - dma-coherent;=0D - };=0D - };=0D -=0D - CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE {=0D - compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie";=0D - reg =3D <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>,=0D - <0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>;=0D - reg-names =3D "ctrl", "config";=0D - #address-cells =3D <3>;=0D - #size-cells =3D <2>;=0D - #interrupt-cells =3D <1>;=0D - device_type =3D "pci";=0D - dma-coherent;=0D - msi-parent =3D <&gic_v2m0>;=0D -=0D - bus-range =3D <0 0xff>;=0D - ranges =3D=0D - /* downstream I/O */=0D - <0x81000000 0 CP110_PCIEx_IO_BASE(0) 0 CP110_PCIEx_IO_BAS= E(0) 0 0x10000=0D - /* non-prefetchable memory */=0D - 0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BA= SE(0) 0 0xf00000>;=0D - interrupt-map-mask =3D <0 0 0 0>;=0D - interrupt-map =3D <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 2= 2 IRQ_TYPE_LEVEL_HIGH>;=0D - interrupts =3D ;=0D - num-lanes =3D <1>;=0D - clock-names =3D "core", "reg";=0D - clocks =3D <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_= clk)>;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE {=0D - compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie";=0D - reg =3D <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>,=0D - <0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>;=0D - reg-names =3D "ctrl", "config";=0D - #address-cells =3D <3>;=0D - #size-cells =3D <2>;=0D - #interrupt-cells =3D <1>;=0D - device_type =3D "pci";=0D - dma-coherent;=0D - msi-parent =3D <&gic_v2m0>;=0D -=0D - bus-range =3D <0 0xff>;=0D - ranges =3D=0D - /* downstream I/O */=0D - <0x81000000 0 CP110_PCIEx_IO_BASE(1) 0 CP110_PCIEx_IO_BAS= E(1) 0 0x10000=0D - /* non-prefetchable memory */=0D - 0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BA= SE(1) 0 0xf00000>;=0D - interrupt-map-mask =3D <0 0 0 0>;=0D - interrupt-map =3D <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 2= 4 IRQ_TYPE_LEVEL_HIGH>;=0D - interrupts =3D ;=0D -=0D - num-lanes =3D <1>;=0D - clock-names =3D "core", "reg";=0D - clocks =3D <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_= clk)>;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE {=0D - compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie";=0D - reg =3D <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>,=0D - <0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>;=0D - reg-names =3D "ctrl", "config";=0D - #address-cells =3D <3>;=0D - #size-cells =3D <2>;=0D - #interrupt-cells =3D <1>;=0D - device_type =3D "pci";=0D - dma-coherent;=0D - msi-parent =3D <&gic_v2m0>;=0D -=0D - bus-range =3D <0 0xff>;=0D - ranges =3D=0D - /* downstream I/O */=0D - <0x81000000 0 CP110_PCIEx_IO_BASE(2) 0 CP110_PCIEx_IO_BAS= E(2) 0 0x10000=0D - /* non-prefetchable memory */=0D - 0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BA= SE(2) 0 0xf00000>;=0D - interrupt-map-mask =3D <0 0 0 0>;=0D - interrupt-map =3D <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 2= 3 IRQ_TYPE_LEVEL_HIGH>;=0D - interrupts =3D ;=0D -=0D - num-lanes =3D <1>;=0D - clock-names =3D "core", "reg";=0D - clocks =3D <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_= clk)>;=0D - status =3D "disabled";=0D - };=0D -=0D - /* 1 GHz fixed main PLL */=0D - CP110_LABEL(mainpll): CP110_LABEL(mainpll) {=0D - compatible =3D "fixed-clock";=0D - #clock-cells =3D <0>;=0D - clock-frequency =3D <1000000000>;=0D - };=0D -=0D - CP110_LABEL(x2core_clk): CP110_LABEL(x2core_clk) {=0D - compatible =3D "fixed-factor-clock";=0D - clocks =3D <&CP110_LABEL(mainpll)>;=0D - #clock-cells =3D <0>;=0D - clock-mult =3D <1>;=0D - clock-div =3D <2>;=0D - };=0D -=0D - CP110_LABEL(core_clk): CP110_LABEL(core_clk) {=0D - compatible =3D "fixed-factor-clock";=0D - clocks =3D <&CP110_LABEL(mainpll)>;=0D - #clock-cells =3D <0>;=0D - clock-mult =3D <1>;=0D - clock-div =3D <2>;=0D - };=0D -=0D - CP110_LABEL(sdio_clk): CP110_LABEL(sdio_clk) {=0D - compatible =3D "fixed-factor-clock";=0D - clocks =3D <&CP110_LABEL(mainpll)>;=0D - #clock-cells =3D <0>;=0D - clock-mult =3D <2>;=0D - clock-div =3D <5>;=0D - };=0D -=0D - CP110_LABEL(nand_clk): CP110_LABEL(nand_clk) {=0D - compatible =3D "fixed-factor-clock";=0D - clocks =3D <&CP110_LABEL(mainpll)>;=0D - #clock-cells =3D <0>;=0D - clock-mult =3D <2>;=0D - clock-div =3D <5>;=0D - };=0D -=0D - CP110_LABEL(ppv2_clk): CP110_LABEL(ppv2_clk) {=0D - compatible =3D "fixed-factor-clock";=0D - clocks =3D <&CP110_LABEL(mainpll)>;=0D - #clock-cells =3D <0>;=0D - clock-mult =3D <1>;=0D - clock-div =3D <3>;=0D - };=0D -=0D - CP110_LABEL(slow_io_clk): CP110_LABEL(slow_io_clk) {=0D - compatible =3D "fixed-factor-clock";=0D - clocks =3D <&CP110_LABEL(mainpll)>;=0D - #clock-cells =3D <0>;=0D - clock-mult =3D <1>;=0D - clock-div =3D <4>;=0D - };=0D -};=0D +#undef CP11X_TYPE=0D diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp115.dtsi b/Sili= con/Marvell/Armada7k8k/DeviceTree/armada-cp115.dtsi new file mode 100644 index 0000000..f57860f --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp115.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)=0D +/*=0D + * Copyright (C) 2019 Marvell Technology Group Ltd.=0D + *=0D + * Device Tree file for Marvell Armada CP115.=0D + */=0D +=0D +#define CP11X_TYPE cp115=0D +=0D +#include "armada-cp11x.dtsi"=0D +=0D +#undef CP11X_TYPE=0D diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp11x.dtsi b/Sili= con/Marvell/Armada7k8k/DeviceTree/armada-cp11x.dtsi new file mode 100644 index 0000000..7f26842 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp11x.dtsi @@ -0,0 +1,627 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)=0D +/*=0D + * Copyright (C) 2016 Marvell Technology Group Ltd.=0D + *=0D + * Device Tree file for Marvell Armada CP11x.=0D + */=0D +=0D +#define ICU_GRP_NSR 0x0=0D +#define ICU_GRP_SR 0x1=0D +#define ICU_GRP_SEI 0x4=0D +#define ICU_GRP_REI 0x5=0D +=0D +#include "armada-common.dtsi"=0D +=0D +#define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) += CP11X_PCIEx_MEM_SIZE(iface))=0D +=0D +/ {=0D + /*=0D + * The contents of the node are defined below, in order to=0D + * save one indentation level=0D + */=0D + CP11X_NAME: CP11X_NAME { };=0D +=0D + /*=0D + * CPs only have one sensor in the thermal IC.=0D + *=0D + * The cooling maps are empty as there are no cooling devices.=0D + */=0D + thermal-zones {=0D + CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(thermal-ic) {=0D + polling-delay-passive =3D <0>; /* Interrupt driven= */=0D + polling-delay =3D <0>; /* Interrupt driven */=0D +=0D + thermal-sensors =3D <&CP11X_LABEL(thermal) 0>;=0D +=0D + trips {=0D + CP11X_LABEL(crit): crit {=0D + temperature =3D <100000>; /* mC de= grees */=0D + hysteresis =3D <2000>; /* mC degre= es */=0D + type =3D "critical";=0D + };=0D + };=0D +=0D + cooling-maps { };=0D + };=0D + };=0D +};=0D +=0D +&CP11X_NAME {=0D + #address-cells =3D <2>;=0D + #size-cells =3D <2>;=0D + compatible =3D "simple-bus";=0D + interrupt-parent =3D <&CP11X_LABEL(icu_nsr)>;=0D + ranges;=0D +=0D + config-space@CP11X_BASE {=0D + #address-cells =3D <1>;=0D + #size-cells =3D <1>;=0D + compatible =3D "simple-bus";=0D + ranges =3D <0x0 0x0 ADDRESSIFY(CP11X_BASE) 0x2000000>;=0D +=0D + CP11X_LABEL(ethernet): ethernet@0 {=0D + compatible =3D "marvell,armada-7k-pp22";=0D + reg =3D <0x0 0x100000>, <0x129000 0xb000>;=0D + clocks =3D <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL= (ppv2_clk)>,=0D + <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL(c= ore_clk)>,=0D + <&CP11X_LABEL(core_clk)>;=0D + clock-names =3D "pp_clk", "gop_clk",=0D + "mg_clk", "mg_core_clk", "axi_clk";= =0D + marvell,system-controller =3D <&CP11X_LABEL(syscon= 0)>;=0D + status =3D "disabled";=0D + dma-coherent;=0D +=0D + CP11X_LABEL(eth0): eth0 {=0D + interrupts =3D <39 IRQ_TYPE_LEVEL_HIGH>,=0D + <43 IRQ_TYPE_LEVEL_HIGH>,=0D + <47 IRQ_TYPE_LEVEL_HIGH>,=0D + <51 IRQ_TYPE_LEVEL_HIGH>,=0D + <55 IRQ_TYPE_LEVEL_HIGH>,=0D + <59 IRQ_TYPE_LEVEL_HIGH>,=0D + <63 IRQ_TYPE_LEVEL_HIGH>,=0D + <67 IRQ_TYPE_LEVEL_HIGH>,=0D + <71 IRQ_TYPE_LEVEL_HIGH>,=0D + <129 IRQ_TYPE_LEVEL_HIGH>;=0D + interrupt-names =3D "hif0", "hif1", "hif2"= ,=0D + "hif3", "hif4", "hif5", "hif6", "h= if7",=0D + "hif8", "link";=0D + port-id =3D <0>;=0D + gop-port-id =3D <0>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP11X_LABEL(eth1): eth1 {=0D + interrupts =3D <40 IRQ_TYPE_LEVEL_HIGH>,=0D + <44 IRQ_TYPE_LEVEL_HIGH>,=0D + <48 IRQ_TYPE_LEVEL_HIGH>,=0D + <52 IRQ_TYPE_LEVEL_HIGH>,=0D + <56 IRQ_TYPE_LEVEL_HIGH>,=0D + <60 IRQ_TYPE_LEVEL_HIGH>,=0D + <64 IRQ_TYPE_LEVEL_HIGH>,=0D + <68 IRQ_TYPE_LEVEL_HIGH>,=0D + <72 IRQ_TYPE_LEVEL_HIGH>,=0D + <128 IRQ_TYPE_LEVEL_HIGH>;=0D + interrupt-names =3D "hif0", "hif1", "hif2"= ,=0D + "hif3", "hif4", "hif5", "hif6", "h= if7",=0D + "hif8", "link";=0D + port-id =3D <1>;=0D + gop-port-id =3D <2>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP11X_LABEL(eth2): eth2 {=0D + interrupts =3D <41 IRQ_TYPE_LEVEL_HIGH>,=0D + <45 IRQ_TYPE_LEVEL_HIGH>,=0D + <49 IRQ_TYPE_LEVEL_HIGH>,=0D + <53 IRQ_TYPE_LEVEL_HIGH>,=0D + <57 IRQ_TYPE_LEVEL_HIGH>,=0D + <61 IRQ_TYPE_LEVEL_HIGH>,=0D + <65 IRQ_TYPE_LEVEL_HIGH>,=0D + <69 IRQ_TYPE_LEVEL_HIGH>,=0D + <73 IRQ_TYPE_LEVEL_HIGH>,=0D + <127 IRQ_TYPE_LEVEL_HIGH>;=0D + interrupt-names =3D "hif0", "hif1", "hif2"= ,=0D + "hif3", "hif4", "hif5", "hif6", "h= if7",=0D + "hif8", "link";=0D + port-id =3D <2>;=0D + gop-port-id =3D <3>;=0D + status =3D "disabled";=0D + };=0D + };=0D +=0D + CP11X_LABEL(comphy): phy@120000 {=0D + compatible =3D "marvell,comphy-cp110";=0D + reg =3D <0x120000 0x6000>;=0D + marvell,system-controller =3D <&CP11X_LABEL(syscon= 0)>;=0D + clocks =3D <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL= (core_clk)>,=0D + <&CP11X_LABEL(core_clk)>;=0D + clock-names =3D "mg_clk", "mg_core_clk", "axi_clk"= ;=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D +=0D + CP11X_LABEL(comphy0): phy@0 {=0D + reg =3D <0>;=0D + #phy-cells =3D <1>;=0D + };=0D +=0D + CP11X_LABEL(comphy1): phy@1 {=0D + reg =3D <1>;=0D + #phy-cells =3D <1>;=0D + };=0D +=0D + CP11X_LABEL(comphy2): phy@2 {=0D + reg =3D <2>;=0D + #phy-cells =3D <1>;=0D + };=0D +=0D + CP11X_LABEL(comphy3): phy@3 {=0D + reg =3D <3>;=0D + #phy-cells =3D <1>;=0D + };=0D +=0D + CP11X_LABEL(comphy4): phy@4 {=0D + reg =3D <4>;=0D + #phy-cells =3D <1>;=0D + };=0D +=0D + CP11X_LABEL(comphy5): phy@5 {=0D + reg =3D <5>;=0D + #phy-cells =3D <1>;=0D + };=0D + };=0D +=0D + CP11X_LABEL(mdio): mdio@12a200 {=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + compatible =3D "marvell,orion-mdio";=0D + reg =3D <0x12a200 0x10>;=0D + clocks =3D <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL= (ppv2_clk)>,=0D + <&CP11X_LABEL(core_clk)>, <&CP11X_LABEL(c= ore_clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP11X_LABEL(xmdio): mdio@12a600 {=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + compatible =3D "marvell,xmdio";=0D + reg =3D <0x12a600 0x10>;=0D + clocks =3D <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL= (ppv2_clk)>,=0D + <&CP11X_LABEL(core_clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP11X_LABEL(icu): interrupt-controller@1e0000 {=0D + compatible =3D "marvell,cp110-icu";=0D + reg =3D <0x1e0000 0x440>;=0D + #address-cells =3D <1>;=0D + #size-cells =3D <1>;=0D +=0D + CP11X_LABEL(icu_nsr): interrupt-controller@10 {=0D + compatible =3D "marvell,cp110-icu-nsr";=0D + reg =3D <0x10 0x20>;=0D + #interrupt-cells =3D <2>;=0D + interrupt-controller;=0D + msi-parent =3D <&gicp>;=0D + };=0D +=0D + CP11X_LABEL(icu_sei): interrupt-controller@50 {=0D + compatible =3D "marvell,cp110-icu-sei";=0D + reg =3D <0x50 0x10>;=0D + #interrupt-cells =3D <2>;=0D + interrupt-controller;=0D + msi-parent =3D <&sei>;=0D + };=0D + };=0D +=0D + CP11X_LABEL(rtc): rtc@284000 {=0D + compatible =3D "marvell,armada-8k-rtc";=0D + reg =3D <0x284000 0x20>, <0x284080 0x24>;=0D + reg-names =3D "rtc", "rtc-soc";=0D + interrupts =3D <77 IRQ_TYPE_LEVEL_HIGH>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP11X_LABEL(syscon0): system-controller@440000 {=0D + compatible =3D "syscon", "simple-mfd";=0D + reg =3D <0x440000 0x2000>;=0D +=0D + CP11X_LABEL(clk): clock {=0D + compatible =3D "marvell,cp110-clock";=0D + status =3D "disabled";=0D + #clock-cells =3D <2>;=0D + };=0D +=0D + CP11X_LABEL(gpio1): gpio@100 {=0D + compatible =3D "marvell,armada-8k-gpio";=0D + offset =3D <0x100>;=0D + ngpios =3D <32>;=0D + gpio-controller;=0D + #gpio-cells =3D <2>;=0D + gpio-ranges =3D <&CP11X_LABEL(pinctrl) 0 0= 32>;=0D + interrupt-controller;=0D + interrupts =3D <86 IRQ_TYPE_LEVEL_HIGH>,=0D + <85 IRQ_TYPE_LEVEL_HIGH>,=0D + <84 IRQ_TYPE_LEVEL_HIGH>,=0D + <83 IRQ_TYPE_LEVEL_HIGH>;=0D + #interrupt-cells =3D <2>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP11X_LABEL(gpio2): gpio@140 {=0D + compatible =3D "marvell,armada-8k-gpio";=0D + offset =3D <0x140>;=0D + ngpios =3D <31>;=0D + gpio-controller;=0D + #gpio-cells =3D <2>;=0D + gpio-ranges =3D <&CP11X_LABEL(pinctrl) 0 3= 2 31>;=0D + interrupt-controller;=0D + interrupts =3D <82 IRQ_TYPE_LEVEL_HIGH>,=0D + <81 IRQ_TYPE_LEVEL_HIGH>,=0D + <80 IRQ_TYPE_LEVEL_HIGH>,=0D + <79 IRQ_TYPE_LEVEL_HIGH>;=0D + #interrupt-cells =3D <2>;=0D + status =3D "disabled";=0D + };=0D + };=0D +=0D + CP11X_LABEL(syscon1): system-controller@400000 {=0D + compatible =3D "syscon", "simple-mfd";=0D + reg =3D <0x400000 0x1000>;=0D + #address-cells =3D <1>;=0D + #size-cells =3D <1>;=0D +=0D + CP11X_LABEL(thermal): thermal-sensor@70 {=0D + compatible =3D "marvell,armada-cp110-therm= al";=0D + reg =3D <0x70 0x10>;=0D + interrupts-extended =3D=0D + <&CP11X_LABEL(icu_sei) 116 IRQ_TYP= E_LEVEL_HIGH>;=0D + #thermal-sensor-cells =3D <1>;=0D + };=0D + };=0D +=0D + CP11X_LABEL(usb3_0): usb@500000 {=0D + compatible =3D "marvell,armada-8k-xhci",=0D + "generic-xhci";=0D + reg =3D <0x500000 0x4000>;=0D + dma-coherent;=0D + interrupts =3D <106 IRQ_TYPE_LEVEL_HIGH>;=0D + clock-names =3D "core", "reg";=0D + clocks =3D <&CP11X_LABEL(core_clk)>,=0D + <&CP11X_LABEL(core_clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP11X_LABEL(usb3_1): usb@510000 {=0D + compatible =3D "marvell,armada-8k-xhci",=0D + "generic-xhci";=0D + reg =3D <0x510000 0x4000>;=0D + dma-coherent;=0D + interrupts =3D <105 IRQ_TYPE_LEVEL_HIGH>;=0D + clock-names =3D "core", "reg";=0D + clocks =3D <&CP11X_LABEL(core_clk)>,=0D + <&CP11X_LABEL(core_clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP11X_LABEL(sata0): sata@540000 {=0D + compatible =3D "marvell,armada-8k-ahci";=0D + reg =3D <0x540000 0x30000>;=0D + dma-coherent;=0D + clocks =3D <&CP11X_LABEL(core_clk)>,=0D + <&CP11X_LABEL(core_clk)>;=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + status =3D "disabled";=0D +=0D + sata-port@0 {=0D + interrupts =3D <109 IRQ_TYPE_LEVEL_HIGH>;= =0D + reg =3D <0>;=0D + };=0D +=0D + sata-port@1 {=0D + interrupts =3D <107 IRQ_TYPE_LEVEL_HIGH>;= =0D + reg =3D <1>;=0D + };=0D + };=0D +=0D + CP11X_LABEL(xor0): xor@6a0000 {=0D + compatible =3D "marvell,armada-7k-xor", "marvell,x= or-v2";=0D + reg =3D <0x6a0000 0x1000>, <0x6b0000 0x1000>;=0D + dma-coherent;=0D + msi-parent =3D <&gic_v2m0>;=0D + clock-names =3D "core", "reg";=0D + clocks =3D <&CP11X_LABEL(core_clk)>,=0D + <&CP11X_LABEL(x2core_clk)>;=0D + };=0D +=0D + CP11X_LABEL(xor1): xor@6c0000 {=0D + compatible =3D "marvell,armada-7k-xor", "marvell,x= or-v2";=0D + reg =3D <0x6c0000 0x1000>, <0x6d0000 0x1000>;=0D + dma-coherent;=0D + msi-parent =3D <&gic_v2m0>;=0D + clock-names =3D "core", "reg";=0D + clocks =3D <&CP11X_LABEL(core_clk)>,=0D + <&CP11X_LABEL(x2core_clk)>;=0D + };=0D +=0D + CP11X_LABEL(spi0): spi@700600 {=0D + compatible =3D "marvell,armada-380-spi";=0D + reg =3D <0x700600 0x50>;=0D + #address-cells =3D <0x1>;=0D + #size-cells =3D <0x0>;=0D + clock-names =3D "core", "axi";=0D + clocks =3D <&CP11X_LABEL(slow_io_clk)>,=0D + <&CP11X_LABEL(x2core_clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP11X_LABEL(spi1): spi@700680 {=0D + compatible =3D "marvell,armada-380-spi";=0D + reg =3D <0x700680 0x50>;=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + clock-names =3D "core", "axi";=0D + clocks =3D <&CP11X_LABEL(slow_io_clk)>,=0D + <&CP11X_LABEL(x2core_clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP11X_LABEL(i2c0): i2c@701000 {=0D + compatible =3D "marvell,mv78230-i2c";=0D + reg =3D <0x701000 0x20>;=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + interrupts =3D <120 IRQ_TYPE_LEVEL_HIGH>;=0D + clock-names =3D "core", "reg";=0D + clocks =3D <&CP11X_LABEL(slow_io_clk)>,=0D + <&CP11X_LABEL(x2core_clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP11X_LABEL(i2c1): i2c@701100 {=0D + compatible =3D "marvell,mv78230-i2c";=0D + reg =3D <0x701100 0x20>;=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + interrupts =3D <121 IRQ_TYPE_LEVEL_HIGH>;=0D + clock-names =3D "core", "reg";=0D + clocks =3D <&CP11X_LABEL(slow_io_clk)>,=0D + <&CP11X_LABEL(x2core_clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP11X_LABEL(uart0): serial@702000 {=0D + compatible =3D "snps,dw-apb-uart";=0D + reg =3D <0x702000 0x100>;=0D + reg-shift =3D <2>;=0D + interrupts =3D <122 IRQ_TYPE_LEVEL_HIGH>;=0D + reg-io-width =3D <1>;=0D + clock-names =3D "baudclk", "apb_pclk";=0D + clocks =3D <&CP11X_LABEL(slow_io_clk)>,=0D + <&CP11X_LABEL(x2core_clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP11X_LABEL(uart1): serial@702100 {=0D + compatible =3D "snps,dw-apb-uart";=0D + reg =3D <0x702100 0x100>;=0D + reg-shift =3D <2>;=0D + interrupts =3D <123 IRQ_TYPE_LEVEL_HIGH>;=0D + reg-io-width =3D <1>;=0D + clock-names =3D "baudclk", "apb_pclk";=0D + clocks =3D <&CP11X_LABEL(slow_io_clk)>,=0D + <&CP11X_LABEL(x2core_clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP11X_LABEL(uart2): serial@702200 {=0D + compatible =3D "snps,dw-apb-uart";=0D + reg =3D <0x702200 0x100>;=0D + reg-shift =3D <2>;=0D + interrupts =3D <124 IRQ_TYPE_LEVEL_HIGH>;=0D + reg-io-width =3D <1>;=0D + clock-names =3D "baudclk", "apb_pclk";=0D + clocks =3D <&CP11X_LABEL(slow_io_clk)>,=0D + <&CP11X_LABEL(x2core_clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP11X_LABEL(uart3): serial@702300 {=0D + compatible =3D "snps,dw-apb-uart";=0D + reg =3D <0x702300 0x100>;=0D + reg-shift =3D <2>;=0D + interrupts =3D <125 IRQ_TYPE_LEVEL_HIGH>;=0D + reg-io-width =3D <1>;=0D + clock-names =3D "baudclk", "apb_pclk";=0D + clocks =3D <&CP11X_LABEL(slow_io_clk)>,=0D + <&CP11X_LABEL(x2core_clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP11X_LABEL(nand_controller): nand@720000 {=0D + /*=0D + * Due to the limitation of the pins available=0D + * this controller is only usable on the CPM=0D + * for A7K and on the CPS for A8K.=0D + */=0D + compatible =3D "marvell,armada-8k-nand-controller"= ,=0D + "marvell,armada370-nand-controller";=0D + reg =3D <0x720000 0x54>;=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + interrupts =3D <115 IRQ_TYPE_LEVEL_HIGH>;=0D + clock-names =3D "core", "reg";=0D + clocks =3D <&CP11X_LABEL(nand_clk)>,=0D + <&CP11X_LABEL(x2core_clk)>;=0D + marvell,system-controller =3D <&CP11X_LABEL(syscon= 0)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP11X_LABEL(trng): trng@760000 {=0D + compatible =3D "marvell,armada-8k-rng",=0D + "inside-secure,safexcel-eip76";=0D + reg =3D <0x760000 0x7d>;=0D + interrupts =3D <95 IRQ_TYPE_LEVEL_HIGH>;=0D + clock-names =3D "core", "reg";=0D + clocks =3D <&CP11X_LABEL(x2core_clk)>,=0D + <&CP11X_LABEL(x2core_clk)>;=0D + status =3D "okay";=0D + };=0D +=0D + CP11X_LABEL(sdhci0): sdhci@780000 {=0D + compatible =3D "marvell,armada-cp110-sdhci";=0D + reg =3D <0x780000 0x300>;=0D + interrupts =3D <27 IRQ_TYPE_LEVEL_HIGH>;=0D + clock-names =3D "core", "axi";=0D + clocks =3D <&CP11X_LABEL(sdio_clk)>, <&CP11X_LABEL= (core_clk)>;=0D + dma-coherent;=0D + status =3D "disabled";=0D + };=0D +=0D + CP11X_LABEL(crypto): crypto@800000 {=0D + compatible =3D "inside-secure,safexcel-eip197b";=0D + reg =3D <0x800000 0x200000>;=0D + interrupts =3D <87 IRQ_TYPE_LEVEL_HIGH>,=0D + <88 IRQ_TYPE_LEVEL_HIGH>,=0D + <89 IRQ_TYPE_LEVEL_HIGH>,=0D + <90 IRQ_TYPE_LEVEL_HIGH>,=0D + <91 IRQ_TYPE_LEVEL_HIGH>,=0D + <92 IRQ_TYPE_LEVEL_HIGH>;=0D + interrupt-names =3D "mem", "ring0", "ring1",=0D + "ring2", "ring3", "eip";=0D + clock-names =3D "core", "reg";=0D + clocks =3D <&CP11X_LABEL(x2core_clk)>,=0D + <&CP11X_LABEL(x2core_clk)>;=0D + dma-coherent;=0D + };=0D + };=0D +=0D + CP11X_LABEL(pcie0): pcie@CP11X_PCIE0_BASE {=0D + compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie";=0D + reg =3D <0 ADDRESSIFY(CP11X_PCIE0_BASE) 0 0x10000>,=0D + <0 CP11X_PCIEx_CONF_BASE(0) 0 0x80000>;=0D + reg-names =3D "ctrl", "config";=0D + #address-cells =3D <3>;=0D + #size-cells =3D <2>;=0D + #interrupt-cells =3D <1>;=0D + device_type =3D "pci";=0D + dma-coherent;=0D + msi-parent =3D <&gic_v2m0>;=0D +=0D + bus-range =3D <0 0xff>;=0D + /* non-prefetchable memory */=0D + ranges =3D <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_= PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_SIZE(0)>;=0D + interrupt-map-mask =3D <0 0 0 0>;=0D + interrupt-map =3D <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TY= PE_LEVEL_HIGH>;=0D + interrupts =3D <22 IRQ_TYPE_LEVEL_HIGH>;=0D + num-lanes =3D <1>;=0D + clock-names =3D "core", "reg";=0D + clocks =3D <&CP11X_LABEL(core_clk)>, <&CP11X_LABEL(x2core_= clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP11X_LABEL(pcie1): pcie@CP11X_PCIE1_BASE {=0D + compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie";=0D + reg =3D <0 ADDRESSIFY(CP11X_PCIE1_BASE) 0 0x10000>,=0D + <0 CP11X_PCIEx_CONF_BASE(1) 0 0x80000>;=0D + reg-names =3D "ctrl", "config";=0D + #address-cells =3D <3>;=0D + #size-cells =3D <2>;=0D + #interrupt-cells =3D <1>;=0D + device_type =3D "pci";=0D + dma-coherent;=0D + msi-parent =3D <&gic_v2m0>;=0D +=0D + bus-range =3D <0 0xff>;=0D + /* non-prefetchable memory */=0D + ranges =3D <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_= PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_SIZE(1)>;=0D + interrupt-map-mask =3D <0 0 0 0>;=0D + interrupt-map =3D <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TY= PE_LEVEL_HIGH>;=0D + interrupts =3D <24 IRQ_TYPE_LEVEL_HIGH>;=0D +=0D + num-lanes =3D <1>;=0D + clock-names =3D "core", "reg";=0D + clocks =3D <&CP11X_LABEL(core_clk)>, <&CP11X_LABEL(x2core_= clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP11X_LABEL(pcie2): pcie@CP11X_PCIE2_BASE {=0D + compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie";=0D + reg =3D <0 ADDRESSIFY(CP11X_PCIE2_BASE) 0 0x10000>,=0D + <0 CP11X_PCIEx_CONF_BASE(2) 0 0x80000>;=0D + reg-names =3D "ctrl", "config";=0D + #address-cells =3D <3>;=0D + #size-cells =3D <2>;=0D + #interrupt-cells =3D <1>;=0D + device_type =3D "pci";=0D + dma-coherent;=0D + msi-parent =3D <&gic_v2m0>;=0D +=0D + bus-range =3D <0 0xff>;=0D + /* non-prefetchable memory */=0D + ranges =3D <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_= PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_SIZE(2)>;=0D + interrupt-map-mask =3D <0 0 0 0>;=0D + interrupt-map =3D <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TY= PE_LEVEL_HIGH>;=0D + interrupts =3D <23 IRQ_TYPE_LEVEL_HIGH>;=0D +=0D + num-lanes =3D <1>;=0D + clock-names =3D "core", "reg";=0D + clocks =3D <&CP11X_LABEL(core_clk)>, <&CP11X_LABEL(x2core_= clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + /* 1 GHz fixed main PLL */=0D + CP11X_LABEL(mainpll): CP11X_LABEL(mainpll) {=0D + compatible =3D "fixed-clock";=0D + #clock-cells =3D <0>;=0D + clock-frequency =3D <1000000000>;=0D + };=0D +=0D + CP11X_LABEL(x2core_clk): CP11X_LABEL(x2core_clk) {=0D + compatible =3D "fixed-factor-clock";=0D + clocks =3D <&CP11X_LABEL(mainpll)>;=0D + #clock-cells =3D <0>;=0D + clock-mult =3D <1>;=0D + clock-div =3D <2>;=0D + };=0D +=0D + CP11X_LABEL(core_clk): CP11X_LABEL(core_clk) {=0D + compatible =3D "fixed-factor-clock";=0D + clocks =3D <&CP11X_LABEL(mainpll)>;=0D + #clock-cells =3D <0>;=0D + clock-mult =3D <1>;=0D + clock-div =3D <2>;=0D + };=0D +=0D + CP11X_LABEL(sdio_clk): CP11X_LABEL(sdio_clk) {=0D + compatible =3D "fixed-factor-clock";=0D + clocks =3D <&CP11X_LABEL(mainpll)>;=0D + #clock-cells =3D <0>;=0D + clock-mult =3D <2>;=0D + clock-div =3D <5>;=0D + };=0D +=0D + CP11X_LABEL(nand_clk): CP11X_LABEL(nand_clk) {=0D + compatible =3D "fixed-factor-clock";=0D + clocks =3D <&CP11X_LABEL(mainpll)>;=0D + #clock-cells =3D <0>;=0D + clock-mult =3D <2>;=0D + clock-div =3D <5>;=0D + };=0D +=0D + CP11X_LABEL(ppv2_clk): CP11X_LABEL(ppv2_clk) {=0D + compatible =3D "fixed-factor-clock";=0D + clocks =3D <&CP11X_LABEL(mainpll)>;=0D + #clock-cells =3D <0>;=0D + clock-mult =3D <1>;=0D + clock-div =3D <3>;=0D + };=0D +=0D + CP11X_LABEL(slow_io_clk): CP11X_LABEL(slow_io_clk) {=0D + compatible =3D "fixed-factor-clock";=0D + clocks =3D <&CP11X_LABEL(mainpll)>;=0D + #clock-cells =3D <0>;=0D + clock-mult =3D <1>;=0D + clock-div =3D <4>;=0D + };=0D +};=0D --=20 2.29.0