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[193.106.246.138]) by smtp.gmail.com with ESMTPSA id g10sm1153794lfu.265.2021.03.21.18.32.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Mar 2021 18:32:50 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ard.biesheuvel@arm.com, mw@semihalf.com, jaz@semihalf.com, kostap@marvell.com, upstream@semihalf.com, jon@solid-run.com Subject: [edk2-non-osi PATCH v2 4/4] Marvell/OcteonTx: Update device trees Date: Mon, 22 Mar 2021 02:32:31 +0100 Message-Id: <20210322013231.3216058-5-mw@semihalf.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210322013231.3216058-1-mw@semihalf.com> References: <20210322013231.3216058-1-mw@semihalf.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable This patch updates the OcteonTx device trees to the version found in Linux v5.11. All previous modifications, compared to vanilla files, are kept, i.e. disabled SPI flashes & RTC and fixed-clock tree. Also enable the 10G ports and keep AHCI node intact in order to avoid compatibility breakage. Signed-off-by: Marcin Wojtas --- Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf = | 2 +- Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf = | 2 +- Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf = | 2 +- Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806-quad.dtsi = | 43 -- Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807-quad.dtsi = | 93 +++ Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807.dtsi = | 35 ++ Silicon/Marvell/OcteonTx/DeviceTree/T91/{armada-ap806.dtsi =3D> armada-ap8= 0x.dtsi} | 241 +++++++- Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-common.dtsi = | 3 +- Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp110.dtsi = | 552 ----------------- Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp115.dtsi = | 12 + Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11x.dtsi = | 632 ++++++++++++++++++++ Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db-A.dts = | 185 ------ Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dts = | 403 +++++++++++++ Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130.dtsi = | 143 +---- Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db-A.dts = | 29 - Silicon/Marvell/OcteonTx/DeviceTree/T91/{cn9131-db.dtsi =3D> cn9131-db.dts= } | 93 ++- Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts = | 70 --- Silicon/Marvell/OcteonTx/DeviceTree/T91/{cn9132-db.dtsi =3D> cn9132-db.dts= } | 126 +++- 18 files changed, 1586 insertions(+), 1080 deletions(-) delete mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806-qu= ad.dtsi create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807-qu= ad.dtsi create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807.dt= si rename Silicon/Marvell/OcteonTx/DeviceTree/T91/{armada-ap806.dtsi =3D> arm= ada-ap80x.dtsi} (51%) delete mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp110.dt= si create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp115.dt= si create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11x.dt= si delete mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db-A.dts create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dts delete mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db-A.dts rename Silicon/Marvell/OcteonTx/DeviceTree/T91/{cn9131-db.dtsi =3D> cn9131= -db.dts} (66%) delete mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts rename Silicon/Marvell/OcteonTx/DeviceTree/T91/{cn9132-db.dtsi =3D> cn9132= -db.dts} (54%) diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf b/Silico= n/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf index 091a5b4..dfc6c32 100644 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf @@ -16,7 +16,7 @@ VERSION_STRING =3D 1.0=0D =0D [Sources]=0D - cn9130-db-A.dts=0D + cn9130-db.dts=0D =0D [Packages]=0D MdePkg/MdePkg.dec=0D diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf b/Silico= n/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf index 8108197..f5c26a8 100644 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf @@ -16,7 +16,7 @@ VERSION_STRING =3D 1.0=0D =0D [Sources]=0D - cn9131-db-A.dts=0D + cn9131-db.dts=0D =0D [Packages]=0D MdePkg/MdePkg.dec=0D diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf b/Silico= n/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf index c9e3b04..2796541 100644 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf @@ -16,7 +16,7 @@ VERSION_STRING =3D 1.0=0D =0D [Sources]=0D - cn9132-db-A.dts=0D + cn9132-db.dts=0D =0D [Packages]=0D MdePkg/MdePkg.dec=0D diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806-quad.dtsi= b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806-quad.dtsi deleted file mode 100644 index bae0ed9..0000000 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806-quad.dtsi +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT)=0D -/*=0D - * Copyright (C) 2016 Marvell Technology Group Ltd.=0D - *=0D - * Device Tree file for Marvell Armada AP806.=0D - */=0D -=0D -#include "armada-ap806.dtsi"=0D -=0D -/ {=0D - model =3D "Marvell Armada AP806 Quad";=0D - compatible =3D "marvell,armada-ap806-quad", "marvell,armada-ap806"= ;=0D -=0D - cpus {=0D - #address-cells =3D <1>;=0D - #size-cells =3D <0>;=0D -=0D - cpu@0 {=0D - device_type =3D "cpu";=0D - compatible =3D "arm,cortex-a72", "arm,armv8";=0D - reg =3D <0x000>;=0D - enable-method =3D "psci";=0D - };=0D - cpu@1 {=0D - device_type =3D "cpu";=0D - compatible =3D "arm,cortex-a72", "arm,armv8";=0D - reg =3D <0x001>;=0D - enable-method =3D "psci";=0D - };=0D - cpu@100 {=0D - device_type =3D "cpu";=0D - compatible =3D "arm,cortex-a72", "arm,armv8";=0D - reg =3D <0x100>;=0D - enable-method =3D "psci";=0D - };=0D - cpu@101 {=0D - device_type =3D "cpu";=0D - compatible =3D "arm,cortex-a72", "arm,armv8";=0D - reg =3D <0x101>;=0D - enable-method =3D "psci";=0D - };=0D - };=0D -};=0D diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807-quad.dtsi= b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807-quad.dtsi new file mode 100644 index 0000000..6222569 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807-quad.dtsi @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)=0D +/*=0D + * Device Tree file for Marvell Armada AP807 Quad=0D + *=0D + * Copyright (C) 2019 Marvell Technology Group Ltd.=0D + */=0D +=0D +#include "armada-ap807.dtsi"=0D +=0D +/ {=0D + model =3D "Marvell Armada AP807 Quad";=0D + compatible =3D "marvell,armada-ap807-quad", "marvell,armada-ap807"= ;=0D +=0D + cpus {=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D +=0D + cpu0: cpu@0 {=0D + device_type =3D "cpu";=0D + compatible =3D "arm,cortex-a72";=0D + reg =3D <0x000>;=0D + enable-method =3D "psci";=0D + #cooling-cells =3D <2>;=0D + clocks =3D <&cpu_clk 0>;=0D + i-cache-size =3D <0xc000>;=0D + i-cache-line-size =3D <64>;=0D + i-cache-sets =3D <256>;=0D + d-cache-size =3D <0x8000>;=0D + d-cache-line-size =3D <64>;=0D + d-cache-sets =3D <256>;=0D + next-level-cache =3D <&l2_0>;=0D + };=0D + cpu1: cpu@1 {=0D + device_type =3D "cpu";=0D + compatible =3D "arm,cortex-a72";=0D + reg =3D <0x001>;=0D + enable-method =3D "psci";=0D + #cooling-cells =3D <2>;=0D + clocks =3D <&cpu_clk 0>;=0D + i-cache-size =3D <0xc000>;=0D + i-cache-line-size =3D <64>;=0D + i-cache-sets =3D <256>;=0D + d-cache-size =3D <0x8000>;=0D + d-cache-line-size =3D <64>;=0D + d-cache-sets =3D <256>;=0D + next-level-cache =3D <&l2_0>;=0D + };=0D + cpu2: cpu@100 {=0D + device_type =3D "cpu";=0D + compatible =3D "arm,cortex-a72";=0D + reg =3D <0x100>;=0D + enable-method =3D "psci";=0D + #cooling-cells =3D <2>;=0D + clocks =3D <&cpu_clk 1>;=0D + i-cache-size =3D <0xc000>;=0D + i-cache-line-size =3D <64>;=0D + i-cache-sets =3D <256>;=0D + d-cache-size =3D <0x8000>;=0D + d-cache-line-size =3D <64>;=0D + d-cache-sets =3D <256>;=0D + next-level-cache =3D <&l2_1>;=0D + };=0D + cpu3: cpu@101 {=0D + device_type =3D "cpu";=0D + compatible =3D "arm,cortex-a72";=0D + reg =3D <0x101>;=0D + enable-method =3D "psci";=0D + #cooling-cells =3D <2>;=0D + clocks =3D <&cpu_clk 1>;=0D + i-cache-size =3D <0xc000>;=0D + i-cache-line-size =3D <64>;=0D + i-cache-sets =3D <256>;=0D + d-cache-size =3D <0x8000>;=0D + d-cache-line-size =3D <64>;=0D + d-cache-sets =3D <256>;=0D + next-level-cache =3D <&l2_1>;=0D + };=0D +=0D + l2_0: l2-cache0 {=0D + compatible =3D "cache";=0D + cache-size =3D <0x80000>;=0D + cache-line-size =3D <64>;=0D + cache-sets =3D <512>;=0D + };=0D +=0D + l2_1: l2-cache1 {=0D + compatible =3D "cache";=0D + cache-size =3D <0x80000>;=0D + cache-line-size =3D <64>;=0D + cache-sets =3D <512>;=0D + };=0D + };=0D +};=0D diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807.dtsi b/Si= licon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807.dtsi new file mode 100644 index 0000000..0b36eb8 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)=0D +/*=0D + * Device Tree file for Marvell Armada AP807=0D + *=0D + * Copyright (C) 2019 Marvell Technology Group Ltd.=0D + */=0D +=0D +#define AP_NAME ap807=0D +#include "armada-ap80x.dtsi"=0D +=0D +/ {=0D + model =3D "Marvell Armada AP807";=0D + compatible =3D "marvell,armada-ap807";=0D +};=0D +=0D +&ap_syscon0 {=0D + ap_clk: clock {=0D + compatible =3D "marvell,ap807-clock";=0D + #clock-cells =3D <1>;=0D + };=0D +};=0D +=0D +&ap_syscon1 {=0D + cpu_clk: clock-cpu {=0D + compatible =3D "marvell,ap807-cpu-clock";=0D + clocks =3D <&ap_clk 0>, <&ap_clk 1>;=0D + #clock-cells =3D <1>;=0D + };=0D +};=0D +=0D +&ap_sdhci0 {=0D + compatible =3D "marvell,armada-ap807-sdhci",=0D + "marvell,armada-ap806-sdhci"; /* Backward compatibili= ty */=0D +};=0D +=0D diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806.dtsi b/Si= licon/Marvell/OcteonTx/DeviceTree/T91/armada-ap80x.dtsi similarity index 51% rename from Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806.dtsi rename to Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap80x.dtsi index 66124bf..805d782 100644 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806.dtsi +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap80x.dtsi @@ -1,8 +1,8 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT)=0D /*=0D - * Copyright (C) 2016 Marvell Technology Group Ltd.=0D + * Copyright (C) 2019 Marvell Technology Group Ltd.=0D *=0D - * Device Tree file for Marvell Armada AP806.=0D + * Device Tree file for Marvell Armada AP80x.=0D */=0D =0D #define IRQ_TYPE_LEVEL_HIGH (1 << 2)=0D @@ -14,11 +14,12 @@ #define GIC_CPU_MASK_RAW(x) ((x) << 8)=0D #define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1)=0D =0D +#define GPIO_ACTIVE_HIGH 0=0D +#define GPIO_ACTIVE_LOW 1=0D +=0D /dts-v1/;=0D =0D / {=0D - model =3D "Marvell Armada AP806";=0D - compatible =3D "marvell,armada-ap806";=0D #address-cells =3D <2>;=0D #size-cells =3D <2>;=0D =0D @@ -34,7 +35,24 @@ method =3D "smc";=0D };=0D =0D - ap806 {=0D + reserved-memory {=0D + #address-cells =3D <2>;=0D + #size-cells =3D <2>;=0D + ranges;=0D +=0D + /*=0D + * This area matches the mapping done with a=0D + * mainline U-Boot, and should be updated by the=0D + * bootloader.=0D + */=0D +=0D + psci-area@4000000 {=0D + reg =3D <0x0 0x4000000 0x0 0x200000>;=0D + no-map;=0D + };=0D + };=0D +=0D + AP_NAME {=0D #address-cells =3D <2>;=0D #size-cells =3D <2>;=0D compatible =3D "simple-bus";=0D @@ -47,6 +65,24 @@ compatible =3D "simple-bus";=0D ranges =3D <0x0 0x0 0xf0000000 0x1000000>;=0D =0D + smmu: iommu@5000000 {=0D + compatible =3D "marvell,ap806-smmu-500", "= arm,mmu-500";=0D + reg =3D <0x100000 0x100000>;=0D + dma-coherent;=0D + #iommu-cells =3D <1>;=0D + #global-interrupts =3D <1>;=0D + interrupts =3D ,=0D + ,=0D + ,=0D + ,=0D + ,=0D + ,=0D + ,=0D + ,=0D + ;=0D + status =3D "disabled";=0D + };=0D +=0D gic: interrupt-controller@210000 {=0D compatible =3D "arm,gic-400";=0D #interrupt-cells =3D <3>;=0D @@ -131,6 +167,15 @@ interrupts =3D ;=0D };=0D =0D + sei: interrupt-controller@3f0200 {=0D + compatible =3D "marvell,ap806-sei";=0D + reg =3D <0x3f0200 0x40>;=0D + interrupts =3D ;=0D + #interrupt-cells =3D <1>;=0D + interrupt-controller;=0D + msi-controller;=0D + };=0D +=0D xor@400000 {=0D compatible =3D "marvell,armada-7k-xor", "m= arvell,xor-v2";=0D reg =3D <0x400000 0x1000>,=0D @@ -183,7 +228,6 @@ #address-cells =3D <1>;=0D #size-cells =3D <0>;=0D interrupts =3D ;=0D - timeout-ms =3D <1000>;=0D clocks =3D <&ap_clk 3>;=0D status =3D "disabled";=0D };=0D @@ -226,15 +270,10 @@ status =3D "disabled";=0D };=0D =0D - ap_syscon: system-controller@6f4000 {=0D + ap_syscon0: system-controller@6f4000 {=0D compatible =3D "syscon", "simple-mfd";=0D reg =3D <0x6f4000 0x2000>;=0D =0D - ap_clk: clock {=0D - compatible =3D "marvell,ap806-cloc= k";=0D - #clock-cells =3D <1>;=0D - };=0D -=0D ap_pinctrl: pinctrl {=0D compatible =3D "marvell,ap806-pinc= trl";=0D =0D @@ -251,13 +290,183 @@ gpio-controller;=0D #gpio-cells =3D <2>;=0D gpio-ranges =3D <&ap_pinctrl 0 0 2= 0>;=0D + marvell,pwm-offset =3D <0x10c0>;=0D + #pwm-cells =3D <2>;=0D + clocks =3D <&ap_clk 3>;=0D + };=0D + };=0D +=0D + ap_syscon1: system-controller@6f8000 {=0D + compatible =3D "syscon", "simple-mfd";=0D + reg =3D <0x6f8000 0x1000>;=0D + #address-cells =3D <1>;=0D + #size-cells =3D <1>;=0D +=0D + ap_thermal: thermal-sensor@80 {=0D + compatible =3D "marvell,armada-ap8= 06-thermal";=0D + reg =3D <0x80 0x10>;=0D + interrupt-parent =3D <&sei>;=0D + interrupts =3D <18>;=0D + #thermal-sensor-cells =3D <1>;=0D };=0D };=0D + };=0D + };=0D =0D - ap_thermal: thermal@6f808c {=0D - compatible =3D "marvell,armada-ap806-therm= al";=0D - reg =3D <0x6f808c 0x4>,=0D - <0x6f8084 0x8>;=0D + /*=0D + * The thermal IP features one internal sensor plus, if applicable= , one=0D + * remote channel wired to one sensor per CPU.=0D + *=0D + * Only one thermal zone per AP/CP may trigger interrupts at a tim= e, the=0D + * first one that will have a critical trip point will be chosen.= =0D + */=0D + thermal-zones {=0D + ap_thermal_ic: ap-thermal-ic {=0D + polling-delay-passive =3D <0>; /* Interrupt driven= */=0D + polling-delay =3D <0>; /* Interrupt driven */=0D +=0D + thermal-sensors =3D <&ap_thermal 0>;=0D +=0D + trips {=0D + ap_crit: ap-crit {=0D + temperature =3D <100000>; /* mC de= grees */=0D + hysteresis =3D <2000>; /* mC degre= es */=0D + type =3D "critical";=0D + };=0D + };=0D +=0D + cooling-maps { };=0D + };=0D +=0D + ap_thermal_cpu0: ap-thermal-cpu0 {=0D + polling-delay-passive =3D <1000>;=0D + polling-delay =3D <1000>;=0D +=0D + thermal-sensors =3D <&ap_thermal 1>;=0D +=0D + trips {=0D + cpu0_hot: cpu0-hot {=0D + temperature =3D <85000>;=0D + hysteresis =3D <2000>;=0D + type =3D "passive";=0D + };=0D + cpu0_emerg: cpu0-emerg {=0D + temperature =3D <95000>;=0D + hysteresis =3D <2000>;=0D + type =3D "passive";=0D + };=0D + };=0D +=0D + cooling-maps {=0D + map0_hot: map0-hot {=0D + trip =3D <&cpu0_hot>;=0D + cooling-device =3D <&cpu0 1 2>,=0D + <&cpu1 1 2>;=0D + };=0D + map0_emerg: map0-ermerg {=0D + trip =3D <&cpu0_emerg>;=0D + cooling-device =3D <&cpu0 3 3>,=0D + <&cpu1 3 3>;=0D + };=0D + };=0D + };=0D +=0D + ap_thermal_cpu1: ap-thermal-cpu1 {=0D + polling-delay-passive =3D <1000>;=0D + polling-delay =3D <1000>;=0D +=0D + thermal-sensors =3D <&ap_thermal 2>;=0D +=0D + trips {=0D + cpu1_hot: cpu1-hot {=0D + temperature =3D <85000>;=0D + hysteresis =3D <2000>;=0D + type =3D "passive";=0D + };=0D + cpu1_emerg: cpu1-emerg {=0D + temperature =3D <95000>;=0D + hysteresis =3D <2000>;=0D + type =3D "passive";=0D + };=0D + };=0D +=0D + cooling-maps {=0D + map1_hot: map1-hot {=0D + trip =3D <&cpu1_hot>;=0D + cooling-device =3D <&cpu0 1 2>,=0D + <&cpu1 1 2>;=0D + };=0D + map1_emerg: map1-emerg {=0D + trip =3D <&cpu1_emerg>;=0D + cooling-device =3D <&cpu0 3 3>,=0D + <&cpu1 3 3>;=0D + };=0D + };=0D + };=0D +=0D + ap_thermal_cpu2: ap-thermal-cpu2 {=0D + polling-delay-passive =3D <1000>;=0D + polling-delay =3D <1000>;=0D +=0D + thermal-sensors =3D <&ap_thermal 3>;=0D +=0D + trips {=0D + cpu2_hot: cpu2-hot {=0D + temperature =3D <85000>;=0D + hysteresis =3D <2000>;=0D + type =3D "passive";=0D + };=0D + cpu2_emerg: cpu2-emerg {=0D + temperature =3D <95000>;=0D + hysteresis =3D <2000>;=0D + type =3D "passive";=0D + };=0D + };=0D +=0D + cooling-maps {=0D + map2_hot: map2-hot {=0D + trip =3D <&cpu2_hot>;=0D + cooling-device =3D <&cpu2 1 2>,=0D + <&cpu3 1 2>;=0D + };=0D + map2_emerg: map2-emerg {=0D + trip =3D <&cpu2_emerg>;=0D + cooling-device =3D <&cpu2 3 3>,=0D + <&cpu3 3 3>;=0D + };=0D + };=0D + };=0D +=0D + ap_thermal_cpu3: ap-thermal-cpu3 {=0D + polling-delay-passive =3D <1000>;=0D + polling-delay =3D <1000>;=0D +=0D + thermal-sensors =3D <&ap_thermal 4>;=0D +=0D + trips {=0D + cpu3_hot: cpu3-hot {=0D + temperature =3D <85000>;=0D + hysteresis =3D <2000>;=0D + type =3D "passive";=0D + };=0D + cpu3_emerg: cpu3-emerg {=0D + temperature =3D <95000>;=0D + hysteresis =3D <2000>;=0D + type =3D "passive";=0D + };=0D + };=0D +=0D + cooling-maps {=0D + map3_hot: map3-bhot {=0D + trip =3D <&cpu3_hot>;=0D + cooling-device =3D <&cpu2 1 2>,=0D + <&cpu3 1 2>;=0D + };=0D + map3_emerg: map3-emerg {=0D + trip =3D <&cpu3_emerg>;=0D + cooling-device =3D <&cpu2 3 3>,=0D + <&cpu3 3 3>;=0D + };=0D };=0D };=0D };=0D diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-common.dtsi b/S= ilicon/Marvell/OcteonTx/DeviceTree/T91/armada-common.dtsi index 8b610fd..f002499 100644 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-common.dtsi +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-common.dtsi @@ -6,5 +6,6 @@ /* Common definitions used by Armada 7K/8K DTs */=0D #define PASTER(x, y) x ## y=0D #define EVALUATOR(x, y) PASTER(x, y)=0D -#define CP110_LABEL(name) EVALUATOR(CP110_NAME, EVALUATOR(_, name))=0D +#define CP11X_LABEL(name) EVALUATOR(CP11X_NAME, EVALUATOR(_, name))=0D +#define CP11X_NODE_NAME(name) EVALUATOR(CP11X_NAME, EVALUATOR(-, name))=0D #define ADDRESSIFY(addr) EVALUATOR(0x, addr)=0D diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp110.dtsi b/Si= licon/Marvell/OcteonTx/DeviceTree/T91/armada-cp110.dtsi deleted file mode 100644 index b6e5ded..0000000 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp110.dtsi +++ /dev/null @@ -1,552 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT)=0D -/*=0D - * Copyright (C) 2016 Marvell Technology Group Ltd.=0D - *=0D - * Device Tree file for Marvell Armada CP110.=0D - */=0D -=0D -#include "armada-common.dtsi"=0D -=0D -#define ICU_GRP_NSR 0x0=0D -#define ICU_GRP_SR 0x1=0D -#define ICU_GRP_SEI 0x4=0D -#define ICU_GRP_REI 0x5=0D -=0D -#define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) + 0= xf00000)=0D -=0D -/ {=0D - /*=0D - * The contents of the node are defined below, in order to=0D - * save one indentation level=0D - */=0D - CP110_NAME: CP110_NAME { };=0D -};=0D -=0D -&CP110_NAME {=0D - #address-cells =3D <2>;=0D - #size-cells =3D <2>;=0D - compatible =3D "simple-bus";=0D - interrupt-parent =3D <&CP110_LABEL(icu)>;=0D - ranges;=0D -=0D - config-space@CP110_BASE {=0D - #address-cells =3D <1>;=0D - #size-cells =3D <1>;=0D - compatible =3D "simple-bus";=0D - ranges =3D <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>;=0D -=0D - CP110_LABEL(ethernet): ethernet@0 {=0D - compatible =3D "marvell,armada-7k-pp22";=0D - reg =3D <0x0 0x100000>, <0x129000 0xb000>;=0D - clocks =3D <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL= (ppv2_clk)>,=0D - <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL(c= ore_clk)>,=0D - <&CP110_LABEL(core_clk)>;=0D - clock-names =3D "pp_clk", "gop_clk",=0D - "mg_clk", "mg_core_clk", "axi_clk";= =0D - marvell,system-controller =3D <&CP110_LABEL(syscon= 0)>;=0D - status =3D "disabled";=0D - dma-coherent;=0D -=0D - CP110_LABEL(eth0): eth0 {=0D - interrupts =3D ,=0D - ,=0D - ,=0D - ,=0D - ,=0D - ;=0D - interrupt-names =3D "tx-cpu0", "tx-cpu1", = "tx-cpu2",=0D - "tx-cpu3", "rx-shared", "link";=0D - port-id =3D <0>;=0D - gop-port-id =3D <0>;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(eth1): eth1 {=0D - interrupts =3D ,=0D - ,=0D - ,=0D - ,=0D - ,=0D - ;=0D - interrupt-names =3D "tx-cpu0", "tx-cpu1", = "tx-cpu2",=0D - "tx-cpu3", "rx-shared", "link";=0D - port-id =3D <1>;=0D - gop-port-id =3D <2>;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(eth2): eth2 {=0D - interrupts =3D ,=0D - ,=0D - ,=0D - ,=0D - ,=0D - ;=0D - interrupt-names =3D "tx-cpu0", "tx-cpu1", = "tx-cpu2",=0D - "tx-cpu3", "rx-shared", "link";=0D - port-id =3D <2>;=0D - gop-port-id =3D <3>;=0D - status =3D "disabled";=0D - };=0D - };=0D -=0D - CP110_LABEL(comphy): phy@120000 {=0D - compatible =3D "marvell,comphy-cp110";=0D - reg =3D <0x120000 0x6000>;=0D - marvell,system-controller =3D <&CP110_LABEL(syscon= 0)>;=0D - #address-cells =3D <1>;=0D - #size-cells =3D <0>;=0D -=0D - CP110_LABEL(comphy0): phy@0 {=0D - reg =3D <0>;=0D - #phy-cells =3D <1>;=0D - };=0D -=0D - CP110_LABEL(comphy1): phy@1 {=0D - reg =3D <1>;=0D - #phy-cells =3D <1>;=0D - };=0D -=0D - CP110_LABEL(comphy2): phy@2 {=0D - reg =3D <2>;=0D - #phy-cells =3D <1>;=0D - };=0D -=0D - CP110_LABEL(comphy3): phy@3 {=0D - reg =3D <3>;=0D - #phy-cells =3D <1>;=0D - };=0D -=0D - CP110_LABEL(comphy4): phy@4 {=0D - reg =3D <4>;=0D - #phy-cells =3D <1>;=0D - };=0D -=0D - CP110_LABEL(comphy5): phy@5 {=0D - reg =3D <5>;=0D - #phy-cells =3D <1>;=0D - };=0D - };=0D -=0D - CP110_LABEL(mdio): mdio@12a200 {=0D - #address-cells =3D <1>;=0D - #size-cells =3D <0>;=0D - compatible =3D "marvell,orion-mdio";=0D - reg =3D <0x12a200 0x10>;=0D - clocks =3D <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL= (ppv2_clk)>,=0D - <&CP110_LABEL(core_clk)>, <&CP110_LABEL(c= ore_clk)>;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(xmdio): mdio@12a600 {=0D - #address-cells =3D <1>;=0D - #size-cells =3D <0>;=0D - compatible =3D "marvell,xmdio";=0D - reg =3D <0x12a600 0x10>;=0D - clocks =3D <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL= (ppv2_clk)>,=0D - <&CP110_LABEL(core_clk)>;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(icu): interrupt-controller@1e0000 {=0D - compatible =3D "marvell,cp110-icu";=0D - reg =3D <0x1e0000 0x440>;=0D - #interrupt-cells =3D <3>;=0D - interrupt-controller;=0D - msi-parent =3D <&gicp>;=0D - };=0D -=0D - CP110_LABEL(rtc): rtc@284000 {=0D - compatible =3D "marvell,armada-8k-rtc";=0D - reg =3D <0x284000 0x20>, <0x284080 0x24>;=0D - reg-names =3D "rtc", "rtc-soc";=0D - interrupts =3D ;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(thermal): thermal@400078 {=0D - compatible =3D "marvell,armada-cp110-thermal";=0D - reg =3D <0x400078 0x4>,=0D - <0x400070 0x8>;=0D - };=0D -=0D - CP110_LABEL(syscon0): system-controller@440000 {=0D - compatible =3D "syscon", "simple-mfd";=0D - reg =3D <0x440000 0x2000>;=0D -=0D - CP110_LABEL(clk): clock {=0D - compatible =3D "marvell,cp110-clock";=0D - status =3D "disabled";=0D - #clock-cells =3D <2>;=0D - };=0D -=0D - CP110_LABEL(gpio1): gpio@100 {=0D - compatible =3D "marvell,armada-8k-gpio";=0D - offset =3D <0x100>;=0D - ngpios =3D <32>;=0D - gpio-controller;=0D - #gpio-cells =3D <2>;=0D - gpio-ranges =3D <&CP110_LABEL(pinctrl) 0 0= 32>;=0D - interrupt-controller;=0D - interrupts =3D ,=0D - ,=0D - ,=0D - ;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(gpio2): gpio@140 {=0D - compatible =3D "marvell,armada-8k-gpio";=0D - offset =3D <0x140>;=0D - ngpios =3D <31>;=0D - gpio-controller;=0D - #gpio-cells =3D <2>;=0D - gpio-ranges =3D <&CP110_LABEL(pinctrl) 0 3= 2 31>;=0D - interrupt-controller;=0D - interrupts =3D ,=0D - ,=0D - ,=0D - ;=0D - status =3D "disabled";=0D - };=0D - };=0D -=0D - CP110_LABEL(usb3_0): usb3@500000 {=0D - compatible =3D "marvell,armada-8k-xhci",=0D - "generic-xhci";=0D - reg =3D <0x500000 0x4000>;=0D - dma-coherent;=0D - interrupts =3D ;=0D - clock-names =3D "core", "reg";=0D - clocks =3D <&CP110_LABEL(core_clk)>,=0D - <&CP110_LABEL(core_clk)>;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(usb3_1): usb3@510000 {=0D - compatible =3D "marvell,armada-8k-xhci",=0D - "generic-xhci";=0D - reg =3D <0x510000 0x4000>;=0D - dma-coherent;=0D - interrupts =3D ;=0D - clock-names =3D "core", "reg";=0D - clocks =3D <&CP110_LABEL(core_clk)>,=0D - <&CP110_LABEL(core_clk)>;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(sata0): sata@540000 {=0D - compatible =3D "marvell,armada-8k-ahci",=0D - "generic-ahci";=0D - reg =3D <0x540000 0x30000>;=0D - dma-coherent;=0D - interrupts =3D ;=0D - clocks =3D <&CP110_LABEL(core_clk)>,=0D - <&CP110_LABEL(core_clk)>;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(xor0): xor@6a0000 {=0D - compatible =3D "marvell,armada-7k-xor", "marvell,x= or-v2";=0D - reg =3D <0x6a0000 0x1000>, <0x6b0000 0x1000>;=0D - dma-coherent;=0D - msi-parent =3D <&gic_v2m0>;=0D - clock-names =3D "core", "reg";=0D - clocks =3D <&CP110_LABEL(core_clk)>,=0D - <&CP110_LABEL(x2core_clk)>;=0D - };=0D -=0D - CP110_LABEL(xor1): xor@6c0000 {=0D - compatible =3D "marvell,armada-7k-xor", "marvell,x= or-v2";=0D - reg =3D <0x6c0000 0x1000>, <0x6d0000 0x1000>;=0D - dma-coherent;=0D - msi-parent =3D <&gic_v2m0>;=0D - clock-names =3D "core", "reg";=0D - clocks =3D <&CP110_LABEL(core_clk)>,=0D - <&CP110_LABEL(x2core_clk)>;=0D - };=0D -=0D - CP110_LABEL(spi0): spi@700600 {=0D - compatible =3D "marvell,armada-380-spi";=0D - reg =3D <0x700600 0x50>;=0D - #address-cells =3D <0x1>;=0D - #size-cells =3D <0x0>;=0D - clock-names =3D "core", "axi";=0D - clocks =3D <&CP110_LABEL(slow_io_clk)>,=0D - <&CP110_LABEL(x2core_clk)>;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(spi1): spi@700680 {=0D - compatible =3D "marvell,armada-380-spi";=0D - reg =3D <0x700680 0x50>;=0D - #address-cells =3D <1>;=0D - #size-cells =3D <0>;=0D - clock-names =3D "core", "axi";=0D - clocks =3D <&CP110_LABEL(slow_io_clk)>,=0D - <&CP110_LABEL(x2core_clk)>;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(i2c0): i2c@701000 {=0D - compatible =3D "marvell,mv78230-i2c";=0D - reg =3D <0x701000 0x20>;=0D - #address-cells =3D <1>;=0D - #size-cells =3D <0>;=0D - interrupts =3D ;=0D - clock-names =3D "core", "reg";=0D - clocks =3D <&CP110_LABEL(slow_io_clk)>,=0D - <&CP110_LABEL(x2core_clk)>;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(i2c1): i2c@701100 {=0D - compatible =3D "marvell,mv78230-i2c";=0D - reg =3D <0x701100 0x20>;=0D - #address-cells =3D <1>;=0D - #size-cells =3D <0>;=0D - interrupts =3D ;=0D - clock-names =3D "core", "reg";=0D - clocks =3D <&CP110_LABEL(slow_io_clk)>,=0D - <&CP110_LABEL(x2core_clk)>;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(uart0): serial@702000 {=0D - compatible =3D "snps,dw-apb-uart";=0D - reg =3D <0x702000 0x100>;=0D - reg-shift =3D <2>;=0D - interrupts =3D ;=0D - reg-io-width =3D <1>;=0D - clock-names =3D "baudclk", "apb_pclk";=0D - clocks =3D <&CP110_LABEL(slow_io_clk)>,=0D - <&CP110_LABEL(x2core_clk)>;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(uart1): serial@702100 {=0D - compatible =3D "snps,dw-apb-uart";=0D - reg =3D <0x702100 0x100>;=0D - reg-shift =3D <2>;=0D - interrupts =3D ;=0D - reg-io-width =3D <1>;=0D - clock-names =3D "baudclk", "apb_pclk";=0D - clocks =3D <&CP110_LABEL(slow_io_clk)>,=0D - <&CP110_LABEL(x2core_clk)>;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(uart2): serial@702200 {=0D - compatible =3D "snps,dw-apb-uart";=0D - reg =3D <0x702200 0x100>;=0D - reg-shift =3D <2>;=0D - interrupts =3D ;=0D - reg-io-width =3D <1>;=0D - clock-names =3D "baudclk", "apb_pclk";=0D - clocks =3D <&CP110_LABEL(slow_io_clk)>,=0D - <&CP110_LABEL(x2core_clk)>;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(uart3): serial@702300 {=0D - compatible =3D "snps,dw-apb-uart";=0D - reg =3D <0x702300 0x100>;=0D - reg-shift =3D <2>;=0D - interrupts =3D ;=0D - reg-io-width =3D <1>;=0D - clock-names =3D "baudclk", "apb_pclk";=0D - clocks =3D <&CP110_LABEL(slow_io_clk)>,=0D - <&CP110_LABEL(x2core_clk)>;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(nand_controller): nand@720000 {=0D - /*=0D - * Due to the limitation of the pins available=0D - * this controller is only usable on the CPM=0D - * for A7K and on the CPS for A8K.=0D - */=0D - compatible =3D "marvell,armada-8k-nand-controller"= ,=0D - "marvell,armada370-nand-controller";=0D - reg =3D <0x720000 0x54>;=0D - #address-cells =3D <1>;=0D - #size-cells =3D <0>;=0D - interrupts =3D ;=0D - clock-names =3D "core", "reg";=0D - clocks =3D <&CP110_LABEL(nand_clk)>,=0D - <&CP110_LABEL(x2core_clk)>;=0D - marvell,system-controller =3D <&CP110_LABEL(syscon= 0)>;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(trng): trng@760000 {=0D - compatible =3D "marvell,armada-8k-rng",=0D - "inside-secure,safexcel-eip76";=0D - reg =3D <0x760000 0x7d>;=0D - interrupts =3D ;=0D - clock-names =3D "core", "reg";=0D - clocks =3D <&CP110_LABEL(x2core_clk)>,=0D - <&CP110_LABEL(x2core_clk)>;=0D - status =3D "okay";=0D - };=0D -=0D - CP110_LABEL(sdhci0): sdhci@780000 {=0D - compatible =3D "marvell,armada-cp110-sdhci";=0D - reg =3D <0x780000 0x300>;=0D - interrupts =3D ;=0D - clock-names =3D "core", "axi";=0D - clocks =3D <&CP110_LABEL(sdio_clk)>, <&CP110_LABEL= (core_clk)>;=0D - dma-coherent;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(crypto): crypto@800000 {=0D - compatible =3D "inside-secure,safexcel-eip197";=0D - reg =3D <0x800000 0x200000>;=0D - interrupts =3D ,=0D - ,=0D - ,=0D - ,=0D - ,=0D - ;=0D - interrupt-names =3D "mem", "ring0", "ring1",=0D - "ring2", "ring3", "eip";=0D - clock-names =3D "core", "reg";=0D - clocks =3D <&CP110_LABEL(x2core_clk)>,=0D - <&CP110_LABEL(x2core_clk)>;=0D - dma-coherent;=0D - };=0D - };=0D -=0D - CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE {=0D - compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie";=0D - reg =3D <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>,=0D - <0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>;=0D - reg-names =3D "ctrl", "config";=0D - #address-cells =3D <3>;=0D - #size-cells =3D <2>;=0D - #interrupt-cells =3D <1>;=0D - device_type =3D "pci";=0D - dma-coherent;=0D - msi-parent =3D <&gic_v2m0>;=0D -=0D - bus-range =3D <0 0xff>;=0D - ranges =3D=0D - /* non-prefetchable memory */=0D - <0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_B= ASE(0) 0 0xf00000>;=0D - interrupt-map-mask =3D <0 0 0 0>;=0D - interrupt-map =3D <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 2= 2 IRQ_TYPE_LEVEL_HIGH>;=0D - interrupts =3D ;=0D - num-lanes =3D <1>;=0D - clock-names =3D "core", "reg";=0D - clocks =3D <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_= clk)>;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE {=0D - compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie";=0D - reg =3D <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>,=0D - <0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>;=0D - reg-names =3D "ctrl", "config";=0D - #address-cells =3D <3>;=0D - #size-cells =3D <2>;=0D - #interrupt-cells =3D <1>;=0D - device_type =3D "pci";=0D - dma-coherent;=0D - msi-parent =3D <&gic_v2m0>;=0D -=0D - bus-range =3D <0 0xff>;=0D - ranges =3D=0D - /* non-prefetchable memory */=0D - <0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_B= ASE(1) 0 0xf00000>;=0D - interrupt-map-mask =3D <0 0 0 0>;=0D - interrupt-map =3D <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 2= 4 IRQ_TYPE_LEVEL_HIGH>;=0D - interrupts =3D ;=0D -=0D - num-lanes =3D <1>;=0D - clock-names =3D "core", "reg";=0D - clocks =3D <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_= clk)>;=0D - status =3D "disabled";=0D - };=0D -=0D - CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE {=0D - compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie";=0D - reg =3D <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>,=0D - <0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>;=0D - reg-names =3D "ctrl", "config";=0D - #address-cells =3D <3>;=0D - #size-cells =3D <2>;=0D - #interrupt-cells =3D <1>;=0D - device_type =3D "pci";=0D - dma-coherent;=0D - msi-parent =3D <&gic_v2m0>;=0D -=0D - bus-range =3D <0 0xff>;=0D - ranges =3D=0D - /* non-prefetchable memory */=0D - <0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_B= ASE(2) 0 0xf00000>;=0D - interrupt-map-mask =3D <0 0 0 0>;=0D - interrupt-map =3D <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 2= 3 IRQ_TYPE_LEVEL_HIGH>;=0D - interrupts =3D ;=0D -=0D - num-lanes =3D <1>;=0D - clock-names =3D "core", "reg";=0D - clocks =3D <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_= clk)>;=0D - status =3D "disabled";=0D - };=0D -=0D - /* 1 GHz fixed main PLL */=0D - CP110_LABEL(mainpll): CP110_LABEL(mainpll) {=0D - compatible =3D "fixed-clock";=0D - #clock-cells =3D <0>;=0D - clock-frequency =3D <1000000000>;=0D - };=0D -=0D - CP110_LABEL(x2core_clk): CP110_LABEL(x2core_clk) {=0D - compatible =3D "fixed-factor-clock";=0D - clocks =3D <&CP110_LABEL(mainpll)>;=0D - #clock-cells =3D <0>;=0D - clock-mult =3D <1>;=0D - clock-div =3D <2>;=0D - };=0D -=0D - CP110_LABEL(core_clk): CP110_LABEL(core_clk) {=0D - compatible =3D "fixed-factor-clock";=0D - clocks =3D <&CP110_LABEL(mainpll)>;=0D - #clock-cells =3D <0>;=0D - clock-mult =3D <1>;=0D - clock-div =3D <2>;=0D - };=0D -=0D - CP110_LABEL(sdio_clk): CP110_LABEL(sdio_clk) {=0D - compatible =3D "fixed-factor-clock";=0D - clocks =3D <&CP110_LABEL(mainpll)>;=0D - #clock-cells =3D <0>;=0D - clock-mult =3D <2>;=0D - clock-div =3D <5>;=0D - };=0D -=0D - CP110_LABEL(nand_clk): CP110_LABEL(nand_clk) {=0D - compatible =3D "fixed-factor-clock";=0D - clocks =3D <&CP110_LABEL(mainpll)>;=0D - #clock-cells =3D <0>;=0D - clock-mult =3D <2>;=0D - clock-div =3D <5>;=0D - };=0D -=0D - CP110_LABEL(ppv2_clk): CP110_LABEL(ppv2_clk) {=0D - compatible =3D "fixed-factor-clock";=0D - clocks =3D <&CP110_LABEL(mainpll)>;=0D - #clock-cells =3D <0>;=0D - clock-mult =3D <1>;=0D - clock-div =3D <3>;=0D - };=0D -=0D - CP110_LABEL(slow_io_clk): CP110_LABEL(slow_io_clk) {=0D - compatible =3D "fixed-factor-clock";=0D - clocks =3D <&CP110_LABEL(mainpll)>;=0D - #clock-cells =3D <0>;=0D - clock-mult =3D <1>;=0D - clock-div =3D <4>;=0D - };=0D -};=0D diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp115.dtsi b/Si= licon/Marvell/OcteonTx/DeviceTree/T91/armada-cp115.dtsi new file mode 100644 index 0000000..f57860f --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp115.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)=0D +/*=0D + * Copyright (C) 2019 Marvell Technology Group Ltd.=0D + *=0D + * Device Tree file for Marvell Armada CP115.=0D + */=0D +=0D +#define CP11X_TYPE cp115=0D +=0D +#include "armada-cp11x.dtsi"=0D +=0D +#undef CP11X_TYPE=0D diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11x.dtsi b/Si= licon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11x.dtsi new file mode 100644 index 0000000..c309aaa --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11x.dtsi @@ -0,0 +1,632 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)=0D +/*=0D + * Copyright (C) 2016 Marvell Technology Group Ltd.=0D + *=0D + * Device Tree file for Marvell Armada CP11x.=0D + */=0D +=0D +#include "armada-common.dtsi"=0D +=0D +#define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) += CP11X_PCIEx_MEM_SIZE(iface))=0D +=0D +/ {=0D + /*=0D + * The contents of the node are defined below, in order to=0D + * save one indentation level=0D + */=0D + CP11X_NAME: CP11X_NAME { };=0D +=0D + /*=0D + * CPs only have one sensor in the thermal IC.=0D + *=0D + * The cooling maps are empty as there are no cooling devices.=0D + */=0D + thermal-zones {=0D + CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(thermal-ic) {=0D + polling-delay-passive =3D <0>; /* Interrupt driven= */=0D + polling-delay =3D <0>; /* Interrupt driven */=0D +=0D + thermal-sensors =3D <&CP11X_LABEL(thermal) 0>;=0D +=0D + trips {=0D + CP11X_LABEL(crit): crit {=0D + temperature =3D <100000>; /* mC de= grees */=0D + hysteresis =3D <2000>; /* mC degre= es */=0D + type =3D "critical";=0D + };=0D + };=0D +=0D + cooling-maps { };=0D + };=0D + };=0D +};=0D +=0D +&CP11X_NAME {=0D + #address-cells =3D <2>;=0D + #size-cells =3D <2>;=0D + compatible =3D "simple-bus";=0D + interrupt-parent =3D <&CP11X_LABEL(icu_nsr)>;=0D + ranges;=0D +=0D + config-space@CP11X_BASE {=0D + #address-cells =3D <1>;=0D + #size-cells =3D <1>;=0D + compatible =3D "simple-bus";=0D + ranges =3D <0x0 0x0 ADDRESSIFY(CP11X_BASE) 0x2000000>;=0D +=0D + CP11X_LABEL(ethernet): ethernet@0 {=0D + compatible =3D "marvell,armada-7k-pp22";=0D + reg =3D <0x0 0x100000>, <0x129000 0xb000>, <0x2200= 00 0x800>;=0D + clocks =3D <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL= (ppv2_clk)>,=0D + <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL(c= ore_clk)>,=0D + <&CP11X_LABEL(core_clk)>;=0D + clock-names =3D "pp_clk", "gop_clk",=0D + "mg_clk", "mg_core_clk", "axi_clk";= =0D + marvell,system-controller =3D <&CP11X_LABEL(syscon= 0)>;=0D + status =3D "disabled";=0D + dma-coherent;=0D +=0D + CP11X_LABEL(eth0): eth0 {=0D + interrupts =3D <39 IRQ_TYPE_LEVEL_HIGH>,=0D + <43 IRQ_TYPE_LEVEL_HIGH>,=0D + <47 IRQ_TYPE_LEVEL_HIGH>,=0D + <51 IRQ_TYPE_LEVEL_HIGH>,=0D + <55 IRQ_TYPE_LEVEL_HIGH>,=0D + <59 IRQ_TYPE_LEVEL_HIGH>,=0D + <63 IRQ_TYPE_LEVEL_HIGH>,=0D + <67 IRQ_TYPE_LEVEL_HIGH>,=0D + <71 IRQ_TYPE_LEVEL_HIGH>,=0D + <129 IRQ_TYPE_LEVEL_HIGH>;=0D + interrupt-names =3D "hif0", "hif1", "hif2"= ,=0D + "hif3", "hif4", "hif5", "hif6", "h= if7",=0D + "hif8", "link";=0D + port-id =3D <0>;=0D + gop-port-id =3D <0>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP11X_LABEL(eth1): eth1 {=0D + interrupts =3D <40 IRQ_TYPE_LEVEL_HIGH>,=0D + <44 IRQ_TYPE_LEVEL_HIGH>,=0D + <48 IRQ_TYPE_LEVEL_HIGH>,=0D + <52 IRQ_TYPE_LEVEL_HIGH>,=0D + <56 IRQ_TYPE_LEVEL_HIGH>,=0D + <60 IRQ_TYPE_LEVEL_HIGH>,=0D + <64 IRQ_TYPE_LEVEL_HIGH>,=0D + <68 IRQ_TYPE_LEVEL_HIGH>,=0D + <72 IRQ_TYPE_LEVEL_HIGH>,=0D + <128 IRQ_TYPE_LEVEL_HIGH>;=0D + interrupt-names =3D "hif0", "hif1", "hif2"= ,=0D + "hif3", "hif4", "hif5", "hif6", "h= if7",=0D + "hif8", "link";=0D + port-id =3D <1>;=0D + gop-port-id =3D <2>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP11X_LABEL(eth2): eth2 {=0D + interrupts =3D <41 IRQ_TYPE_LEVEL_HIGH>,=0D + <45 IRQ_TYPE_LEVEL_HIGH>,=0D + <49 IRQ_TYPE_LEVEL_HIGH>,=0D + <53 IRQ_TYPE_LEVEL_HIGH>,=0D + <57 IRQ_TYPE_LEVEL_HIGH>,=0D + <61 IRQ_TYPE_LEVEL_HIGH>,=0D + <65 IRQ_TYPE_LEVEL_HIGH>,=0D + <69 IRQ_TYPE_LEVEL_HIGH>,=0D + <73 IRQ_TYPE_LEVEL_HIGH>,=0D + <127 IRQ_TYPE_LEVEL_HIGH>;=0D + interrupt-names =3D "hif0", "hif1", "hif2"= ,=0D + "hif3", "hif4", "hif5", "hif6", "h= if7",=0D + "hif8", "link";=0D + port-id =3D <2>;=0D + gop-port-id =3D <3>;=0D + status =3D "disabled";=0D + };=0D + };=0D +=0D + CP11X_LABEL(comphy): phy@120000 {=0D + compatible =3D "marvell,comphy-cp110";=0D + reg =3D <0x120000 0x6000>;=0D + marvell,system-controller =3D <&CP11X_LABEL(syscon= 0)>;=0D + clocks =3D <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL= (core_clk)>,=0D + <&CP11X_LABEL(core_clk)>;=0D + clock-names =3D "mg_clk", "mg_core_clk", "axi_clk"= ;=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D +=0D + CP11X_LABEL(comphy0): phy@0 {=0D + reg =3D <0>;=0D + #phy-cells =3D <1>;=0D + };=0D +=0D + CP11X_LABEL(comphy1): phy@1 {=0D + reg =3D <1>;=0D + #phy-cells =3D <1>;=0D + };=0D +=0D + CP11X_LABEL(comphy2): phy@2 {=0D + reg =3D <2>;=0D + #phy-cells =3D <1>;=0D + };=0D +=0D + CP11X_LABEL(comphy3): phy@3 {=0D + reg =3D <3>;=0D + #phy-cells =3D <1>;=0D + };=0D +=0D + CP11X_LABEL(comphy4): phy@4 {=0D + reg =3D <4>;=0D + #phy-cells =3D <1>;=0D + };=0D +=0D + CP11X_LABEL(comphy5): phy@5 {=0D + reg =3D <5>;=0D + #phy-cells =3D <1>;=0D + };=0D + };=0D +=0D + CP11X_LABEL(mdio): mdio@12a200 {=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + compatible =3D "marvell,orion-mdio";=0D + reg =3D <0x12a200 0x10>;=0D + clocks =3D <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL= (ppv2_clk)>,=0D + <&CP11X_LABEL(core_clk)>, <&CP11X_LABEL(c= ore_clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP11X_LABEL(xmdio): mdio@12a600 {=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + compatible =3D "marvell,xmdio";=0D + reg =3D <0x12a600 0x10>;=0D + clocks =3D <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL= (ppv2_clk)>,=0D + <&CP11X_LABEL(core_clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP11X_LABEL(icu): interrupt-controller@1e0000 {=0D + compatible =3D "marvell,cp110-icu";=0D + reg =3D <0x1e0000 0x440>;=0D + #address-cells =3D <1>;=0D + #size-cells =3D <1>;=0D +=0D + CP11X_LABEL(icu_nsr): interrupt-controller@10 {=0D + compatible =3D "marvell,cp110-icu-nsr";=0D + reg =3D <0x10 0x20>;=0D + #interrupt-cells =3D <2>;=0D + interrupt-controller;=0D + msi-parent =3D <&gicp>;=0D + };=0D +=0D + CP11X_LABEL(icu_sei): interrupt-controller@50 {=0D + compatible =3D "marvell,cp110-icu-sei";=0D + reg =3D <0x50 0x10>;=0D + #interrupt-cells =3D <2>;=0D + interrupt-controller;=0D + msi-parent =3D <&sei>;=0D + };=0D + };=0D +=0D + CP11X_LABEL(rtc): rtc@284000 {=0D + compatible =3D "marvell,armada-8k-rtc";=0D + reg =3D <0x284000 0x20>, <0x284080 0x24>;=0D + reg-names =3D "rtc", "rtc-soc";=0D + interrupts =3D <77 IRQ_TYPE_LEVEL_HIGH>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP11X_LABEL(syscon0): system-controller@440000 {=0D + compatible =3D "syscon", "simple-mfd";=0D + reg =3D <0x440000 0x2000>;=0D +=0D + CP11X_LABEL(clk): clock {=0D + compatible =3D "marvell,cp110-clock";=0D + status =3D "disabled";=0D + #clock-cells =3D <2>;=0D + };=0D +=0D + CP11X_LABEL(gpio1): gpio@100 {=0D + compatible =3D "marvell,armada-8k-gpio";=0D + offset =3D <0x100>;=0D + ngpios =3D <32>;=0D + gpio-controller;=0D + #gpio-cells =3D <2>;=0D + gpio-ranges =3D <&CP11X_LABEL(pinctrl) 0 0= 32>;=0D + marvell,pwm-offset =3D <0x1f0>;=0D + #pwm-cells =3D <2>;=0D + interrupt-controller;=0D + interrupts =3D <86 IRQ_TYPE_LEVEL_HIGH>,=0D + <85 IRQ_TYPE_LEVEL_HIGH>,=0D + <84 IRQ_TYPE_LEVEL_HIGH>,=0D + <83 IRQ_TYPE_LEVEL_HIGH>;=0D + #interrupt-cells =3D <2>;=0D + clock-names =3D "core", "axi";=0D + clocks =3D <&CP11X_LABEL(slow_io_clk)>,=0D + <&CP11X_LABEL(x2core_clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP11X_LABEL(gpio2): gpio@140 {=0D + compatible =3D "marvell,armada-8k-gpio";=0D + offset =3D <0x140>;=0D + ngpios =3D <31>;=0D + gpio-controller;=0D + #gpio-cells =3D <2>;=0D + gpio-ranges =3D <&CP11X_LABEL(pinctrl) 0 3= 2 31>;=0D + marvell,pwm-offset =3D <0x1f0>;=0D + #pwm-cells =3D <2>;=0D + interrupt-controller;=0D + interrupts =3D <82 IRQ_TYPE_LEVEL_HIGH>,=0D + <81 IRQ_TYPE_LEVEL_HIGH>,=0D + <80 IRQ_TYPE_LEVEL_HIGH>,=0D + <79 IRQ_TYPE_LEVEL_HIGH>;=0D + #interrupt-cells =3D <2>;=0D + clock-names =3D "core", "axi";=0D + clocks =3D <&CP11X_LABEL(slow_io_clk)>,=0D + <&CP11X_LABEL(x2core_clk)>;=0D + status =3D "disabled";=0D + };=0D + };=0D +=0D + CP11X_LABEL(syscon1): system-controller@400000 {=0D + compatible =3D "syscon", "simple-mfd";=0D + reg =3D <0x400000 0x1000>;=0D + #address-cells =3D <1>;=0D + #size-cells =3D <1>;=0D +=0D + CP11X_LABEL(thermal): thermal-sensor@70 {=0D + compatible =3D "marvell,armada-cp110-therm= al";=0D + reg =3D <0x70 0x10>;=0D + interrupts-extended =3D=0D + <&CP11X_LABEL(icu_sei) 116 IRQ_TYP= E_LEVEL_HIGH>;=0D + #thermal-sensor-cells =3D <1>;=0D + };=0D + };=0D +=0D + CP11X_LABEL(usb3_0): usb@500000 {=0D + compatible =3D "marvell,armada-8k-xhci",=0D + "generic-xhci";=0D + reg =3D <0x500000 0x4000>;=0D + dma-coherent;=0D + interrupts =3D <106 IRQ_TYPE_LEVEL_HIGH>;=0D + clock-names =3D "core", "reg";=0D + clocks =3D <&CP11X_LABEL(core_clk)>,=0D + <&CP11X_LABEL(core_clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP11X_LABEL(usb3_1): usb@510000 {=0D + compatible =3D "marvell,armada-8k-xhci",=0D + "generic-xhci";=0D + reg =3D <0x510000 0x4000>;=0D + dma-coherent;=0D + interrupts =3D <105 IRQ_TYPE_LEVEL_HIGH>;=0D + clock-names =3D "core", "reg";=0D + clocks =3D <&CP11X_LABEL(core_clk)>,=0D + <&CP11X_LABEL(core_clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP11X_LABEL(sata0): sata@540000 {=0D + compatible =3D "marvell,armada-8k-ahci",=0D + "generic-ahci";=0D + reg =3D <0x540000 0x30000>;=0D + dma-coherent;=0D + interrupts =3D <107 IRQ_TYPE_LEVEL_HIGH>;=0D + clocks =3D <&CP11X_LABEL(core_clk)>,=0D + <&CP11X_LABEL(core_clk)>;=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + status =3D "disabled";=0D +=0D + sata-port@0 {=0D + reg =3D <0>;=0D + };=0D +=0D + sata-port@1 {=0D + reg =3D <1>;=0D + };=0D + };=0D +=0D + CP11X_LABEL(xor0): xor@6a0000 {=0D + compatible =3D "marvell,armada-7k-xor", "marvell,x= or-v2";=0D + reg =3D <0x6a0000 0x1000>, <0x6b0000 0x1000>;=0D + dma-coherent;=0D + msi-parent =3D <&gic_v2m0>;=0D + clock-names =3D "core", "reg";=0D + clocks =3D <&CP11X_LABEL(core_clk)>,=0D + <&CP11X_LABEL(x2core_clk)>;=0D + };=0D +=0D + CP11X_LABEL(xor1): xor@6c0000 {=0D + compatible =3D "marvell,armada-7k-xor", "marvell,x= or-v2";=0D + reg =3D <0x6c0000 0x1000>, <0x6d0000 0x1000>;=0D + dma-coherent;=0D + msi-parent =3D <&gic_v2m0>;=0D + clock-names =3D "core", "reg";=0D + clocks =3D <&CP11X_LABEL(core_clk)>,=0D + <&CP11X_LABEL(x2core_clk)>;=0D + };=0D +=0D + CP11X_LABEL(spi0): spi@700600 {=0D + compatible =3D "marvell,armada-380-spi";=0D + reg =3D <0x700600 0x50>;=0D + #address-cells =3D <0x1>;=0D + #size-cells =3D <0x0>;=0D + clock-names =3D "core", "axi";=0D + clocks =3D <&CP11X_LABEL(slow_io_clk)>,=0D + <&CP11X_LABEL(x2core_clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP11X_LABEL(spi1): spi@700680 {=0D + compatible =3D "marvell,armada-380-spi";=0D + reg =3D <0x700680 0x50>;=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + clock-names =3D "core", "axi";=0D + clocks =3D <&CP11X_LABEL(slow_io_clk)>,=0D + <&CP11X_LABEL(x2core_clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP11X_LABEL(i2c0): i2c@701000 {=0D + compatible =3D "marvell,mv78230-i2c";=0D + reg =3D <0x701000 0x20>;=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + interrupts =3D <120 IRQ_TYPE_LEVEL_HIGH>;=0D + clock-names =3D "core", "reg";=0D + clocks =3D <&CP11X_LABEL(slow_io_clk)>,=0D + <&CP11X_LABEL(x2core_clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP11X_LABEL(i2c1): i2c@701100 {=0D + compatible =3D "marvell,mv78230-i2c";=0D + reg =3D <0x701100 0x20>;=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + interrupts =3D <121 IRQ_TYPE_LEVEL_HIGH>;=0D + clock-names =3D "core", "reg";=0D + clocks =3D <&CP11X_LABEL(slow_io_clk)>,=0D + <&CP11X_LABEL(x2core_clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP11X_LABEL(uart0): serial@702000 {=0D + compatible =3D "snps,dw-apb-uart";=0D + reg =3D <0x702000 0x100>;=0D + reg-shift =3D <2>;=0D + interrupts =3D <122 IRQ_TYPE_LEVEL_HIGH>;=0D + reg-io-width =3D <1>;=0D + clock-names =3D "baudclk", "apb_pclk";=0D + clocks =3D <&CP11X_LABEL(slow_io_clk)>,=0D + <&CP11X_LABEL(x2core_clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP11X_LABEL(uart1): serial@702100 {=0D + compatible =3D "snps,dw-apb-uart";=0D + reg =3D <0x702100 0x100>;=0D + reg-shift =3D <2>;=0D + interrupts =3D <123 IRQ_TYPE_LEVEL_HIGH>;=0D + reg-io-width =3D <1>;=0D + clock-names =3D "baudclk", "apb_pclk";=0D + clocks =3D <&CP11X_LABEL(slow_io_clk)>,=0D + <&CP11X_LABEL(x2core_clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP11X_LABEL(uart2): serial@702200 {=0D + compatible =3D "snps,dw-apb-uart";=0D + reg =3D <0x702200 0x100>;=0D + reg-shift =3D <2>;=0D + interrupts =3D <124 IRQ_TYPE_LEVEL_HIGH>;=0D + reg-io-width =3D <1>;=0D + clock-names =3D "baudclk", "apb_pclk";=0D + clocks =3D <&CP11X_LABEL(slow_io_clk)>,=0D + <&CP11X_LABEL(x2core_clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP11X_LABEL(uart3): serial@702300 {=0D + compatible =3D "snps,dw-apb-uart";=0D + reg =3D <0x702300 0x100>;=0D + reg-shift =3D <2>;=0D + interrupts =3D <125 IRQ_TYPE_LEVEL_HIGH>;=0D + reg-io-width =3D <1>;=0D + clock-names =3D "baudclk", "apb_pclk";=0D + clocks =3D <&CP11X_LABEL(slow_io_clk)>,=0D + <&CP11X_LABEL(x2core_clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP11X_LABEL(nand_controller): nand@720000 {=0D + /*=0D + * Due to the limitation of the pins available=0D + * this controller is only usable on the CPM=0D + * for A7K and on the CPS for A8K.=0D + */=0D + compatible =3D "marvell,armada-8k-nand-controller"= ,=0D + "marvell,armada370-nand-controller";=0D + reg =3D <0x720000 0x54>;=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + interrupts =3D <115 IRQ_TYPE_LEVEL_HIGH>;=0D + clock-names =3D "core", "reg";=0D + clocks =3D <&CP11X_LABEL(nand_clk)>,=0D + <&CP11X_LABEL(x2core_clk)>;=0D + marvell,system-controller =3D <&CP11X_LABEL(syscon= 0)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP11X_LABEL(trng): trng@760000 {=0D + compatible =3D "marvell,armada-8k-rng",=0D + "inside-secure,safexcel-eip76";=0D + reg =3D <0x760000 0x7d>;=0D + interrupts =3D <95 IRQ_TYPE_LEVEL_HIGH>;=0D + clock-names =3D "core", "reg";=0D + clocks =3D <&CP11X_LABEL(x2core_clk)>,=0D + <&CP11X_LABEL(x2core_clk)>;=0D + status =3D "okay";=0D + };=0D +=0D + CP11X_LABEL(sdhci0): sdhci@780000 {=0D + compatible =3D "marvell,armada-cp110-sdhci";=0D + reg =3D <0x780000 0x300>;=0D + interrupts =3D <27 IRQ_TYPE_LEVEL_HIGH>;=0D + clock-names =3D "core", "axi";=0D + clocks =3D <&CP11X_LABEL(sdio_clk)>, <&CP11X_LABEL= (core_clk)>;=0D + dma-coherent;=0D + status =3D "disabled";=0D + };=0D +=0D + CP11X_LABEL(crypto): crypto@800000 {=0D + compatible =3D "inside-secure,safexcel-eip197b";=0D + reg =3D <0x800000 0x200000>;=0D + interrupts =3D <87 IRQ_TYPE_LEVEL_HIGH>,=0D + <88 IRQ_TYPE_LEVEL_HIGH>,=0D + <89 IRQ_TYPE_LEVEL_HIGH>,=0D + <90 IRQ_TYPE_LEVEL_HIGH>,=0D + <91 IRQ_TYPE_LEVEL_HIGH>,=0D + <92 IRQ_TYPE_LEVEL_HIGH>;=0D + interrupt-names =3D "mem", "ring0", "ring1",=0D + "ring2", "ring3", "eip";=0D + clock-names =3D "core", "reg";=0D + clocks =3D <&CP11X_LABEL(x2core_clk)>,=0D + <&CP11X_LABEL(x2core_clk)>;=0D + dma-coherent;=0D + };=0D + };=0D +=0D + CP11X_LABEL(pcie0): pcie@CP11X_PCIE0_BASE {=0D + compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie";=0D + reg =3D <0 ADDRESSIFY(CP11X_PCIE0_BASE) 0 0x10000>,=0D + <0 CP11X_PCIEx_CONF_BASE(0) 0 0x80000>;=0D + reg-names =3D "ctrl", "config";=0D + #address-cells =3D <3>;=0D + #size-cells =3D <2>;=0D + #interrupt-cells =3D <1>;=0D + device_type =3D "pci";=0D + dma-coherent;=0D + msi-parent =3D <&gic_v2m0>;=0D +=0D + bus-range =3D <0 0xff>;=0D + /* non-prefetchable memory */=0D + ranges =3D <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_= PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_SIZE(0)>;=0D + interrupt-map-mask =3D <0 0 0 0>;=0D + interrupt-map =3D <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TY= PE_LEVEL_HIGH>;=0D + interrupts =3D <22 IRQ_TYPE_LEVEL_HIGH>;=0D + num-lanes =3D <1>;=0D + clock-names =3D "core", "reg";=0D + clocks =3D <&CP11X_LABEL(core_clk)>, <&CP11X_LABEL(x2core_= clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP11X_LABEL(pcie1): pcie@CP11X_PCIE1_BASE {=0D + compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie";=0D + reg =3D <0 ADDRESSIFY(CP11X_PCIE1_BASE) 0 0x10000>,=0D + <0 CP11X_PCIEx_CONF_BASE(1) 0 0x80000>;=0D + reg-names =3D "ctrl", "config";=0D + #address-cells =3D <3>;=0D + #size-cells =3D <2>;=0D + #interrupt-cells =3D <1>;=0D + device_type =3D "pci";=0D + dma-coherent;=0D + msi-parent =3D <&gic_v2m0>;=0D +=0D + bus-range =3D <0 0xff>;=0D + /* non-prefetchable memory */=0D + ranges =3D <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_= PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_SIZE(1)>;=0D + interrupt-map-mask =3D <0 0 0 0>;=0D + interrupt-map =3D <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TY= PE_LEVEL_HIGH>;=0D + interrupts =3D <24 IRQ_TYPE_LEVEL_HIGH>;=0D +=0D + num-lanes =3D <1>;=0D + clock-names =3D "core", "reg";=0D + clocks =3D <&CP11X_LABEL(core_clk)>, <&CP11X_LABEL(x2core_= clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + CP11X_LABEL(pcie2): pcie@CP11X_PCIE2_BASE {=0D + compatible =3D "marvell,armada8k-pcie", "snps,dw-pcie";=0D + reg =3D <0 ADDRESSIFY(CP11X_PCIE2_BASE) 0 0x10000>,=0D + <0 CP11X_PCIEx_CONF_BASE(2) 0 0x80000>;=0D + reg-names =3D "ctrl", "config";=0D + #address-cells =3D <3>;=0D + #size-cells =3D <2>;=0D + #interrupt-cells =3D <1>;=0D + device_type =3D "pci";=0D + dma-coherent;=0D + msi-parent =3D <&gic_v2m0>;=0D +=0D + bus-range =3D <0 0xff>;=0D + /* non-prefetchable memory */=0D + ranges =3D <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_= PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_SIZE(2)>;=0D + interrupt-map-mask =3D <0 0 0 0>;=0D + interrupt-map =3D <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TY= PE_LEVEL_HIGH>;=0D + interrupts =3D <23 IRQ_TYPE_LEVEL_HIGH>;=0D +=0D + num-lanes =3D <1>;=0D + clock-names =3D "core", "reg";=0D + clocks =3D <&CP11X_LABEL(core_clk)>, <&CP11X_LABEL(x2core_= clk)>;=0D + status =3D "disabled";=0D + };=0D +=0D + /* 1 GHz fixed main PLL */=0D + CP11X_LABEL(mainpll): CP11X_LABEL(mainpll) {=0D + compatible =3D "fixed-clock";=0D + #clock-cells =3D <0>;=0D + clock-frequency =3D <1000000000>;=0D + };=0D +=0D + CP11X_LABEL(x2core_clk): CP11X_LABEL(x2core_clk) {=0D + compatible =3D "fixed-factor-clock";=0D + clocks =3D <&CP11X_LABEL(mainpll)>;=0D + #clock-cells =3D <0>;=0D + clock-mult =3D <1>;=0D + clock-div =3D <2>;=0D + };=0D +=0D + CP11X_LABEL(core_clk): CP11X_LABEL(core_clk) {=0D + compatible =3D "fixed-factor-clock";=0D + clocks =3D <&CP11X_LABEL(mainpll)>;=0D + #clock-cells =3D <0>;=0D + clock-mult =3D <1>;=0D + clock-div =3D <2>;=0D + };=0D +=0D + CP11X_LABEL(sdio_clk): CP11X_LABEL(sdio_clk) {=0D + compatible =3D "fixed-factor-clock";=0D + clocks =3D <&CP11X_LABEL(mainpll)>;=0D + #clock-cells =3D <0>;=0D + clock-mult =3D <2>;=0D + clock-div =3D <5>;=0D + };=0D +=0D + CP11X_LABEL(nand_clk): CP11X_LABEL(nand_clk) {=0D + compatible =3D "fixed-factor-clock";=0D + clocks =3D <&CP11X_LABEL(mainpll)>;=0D + #clock-cells =3D <0>;=0D + clock-mult =3D <2>;=0D + clock-div =3D <5>;=0D + };=0D +=0D + CP11X_LABEL(ppv2_clk): CP11X_LABEL(ppv2_clk) {=0D + compatible =3D "fixed-factor-clock";=0D + clocks =3D <&CP11X_LABEL(mainpll)>;=0D + #clock-cells =3D <0>;=0D + clock-mult =3D <1>;=0D + clock-div =3D <3>;=0D + };=0D +=0D + CP11X_LABEL(slow_io_clk): CP11X_LABEL(slow_io_clk) {=0D + compatible =3D "fixed-factor-clock";=0D + clocks =3D <&CP11X_LABEL(mainpll)>;=0D + #clock-cells =3D <0>;=0D + clock-mult =3D <1>;=0D + clock-div =3D <4>;=0D + };=0D +};=0D diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db-A.dts b/Sili= con/Marvell/OcteonTx/DeviceTree/T91/cn9130-db-A.dts deleted file mode 100644 index 9e4aa51..0000000 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db-A.dts +++ /dev/null @@ -1,185 +0,0 @@ -/*=0D - * Copyright (C) 2018 Marvell International Ltd.=0D - *=0D - * SPDX-License-Identifier: GPL-2.0=0D - * https://spdx.org/licenses=0D - */=0D -=0D -#include "cn9130-db.dtsi"=0D -=0D -/ {=0D - model =3D "Model: Marvell CN9130 development board (CP NOR) setup(= A)";=0D - compatible =3D "marvell,cn9130-db-A", "marvell,armada-ap807-quad",= =0D - "marvell,armada-ap807";=0D -=0D - chosen {=0D - stdout-path =3D "serial0:115200n8";=0D - };=0D -=0D - aliases {=0D - i2c0 =3D &cp0_i2c0;=0D - ethernet0 =3D &cp0_eth0;=0D - ethernet1 =3D &cp0_eth1;=0D - ethernet2 =3D &cp0_eth2;=0D - };=0D -=0D - memory@00000000 {=0D - device_type =3D "memory";=0D - reg =3D <0x0 0x0 0x0 0x80000000>;=0D - };=0D -};=0D -=0D -&uart0 {=0D - status =3D "okay";=0D -};=0D -=0D -/* on-board eMMC - U9 */=0D -&ap_sdhci0 {=0D - pinctrl-names =3D "default";=0D - bus-width =3D <8>;=0D - status =3D "okay";=0D - vqmmc-supply =3D <&ap0_reg_sd_vccq>;=0D -};=0D -=0D -/*=0D - * CP related configuration=0D - */=0D -&cp0_i2c0 {=0D - pinctrl-names =3D "default";=0D - pinctrl-0 =3D <&cp0_i2c0_pins>;=0D - status =3D "okay";=0D - clock-frequency =3D <100000>;=0D -};=0D -=0D -&cp0_i2c1 {=0D - status =3D "okay";=0D -};=0D -=0D -/* CON 28 */=0D -&cp0_sdhci0 {=0D - status =3D "okay";=0D -};=0D -=0D -/* U54 */=0D -&cp0_nand_controller {=0D - pinctrl-names =3D "default";=0D - pinctrl-0 =3D <&nand_pins>;=0D -=0D - nand@0 {=0D - reg =3D <0>;=0D - label =3D "main-storage";=0D - nand-rb =3D <0>;=0D - nand-ecc-mode =3D "hw";=0D - nand-on-flash-bbt;=0D - nand-ecc-strength =3D <8>;=0D - nand-ecc-step-size =3D <512>;=0D -=0D - partitions {=0D - compatible =3D "fixed-partitions";=0D - #address-cells =3D <1>;=0D - #size-cells =3D <1>;=0D -=0D - partition@0 {=0D - label =3D "U-Boot";=0D - reg =3D <0 0x200000>;=0D - };=0D - partition@200000 {=0D - label =3D "Linux";=0D - reg =3D <0x200000 0xd00000>;=0D - };=0D - partition@1000000 {=0D - label =3D "Filesystem";=0D - reg =3D <0x1000000 0x3f000000>;=0D - };=0D - };=0D - };=0D -};=0D -=0D -/* U55 */=0D -&cp0_spi1 {=0D - pinctrl-names =3D "default";=0D - pinctrl-0 =3D <&cp0_spi0_pins>;=0D - reg =3D <0x700680 0x50>, /* control */=0D - <0x2000000 0x1000000>; /* CS0 */=0D - status =3D "disabled";=0D -=0D - spi-flash@0 {=0D - #address-cells =3D <0x1>;=0D - #size-cells =3D <0x1>;=0D - compatible =3D "jedec,spi-nor";=0D - reg =3D <0x0>;=0D - /* On-board MUX does not allow higher frequencies */=0D - spi-max-frequency =3D <40000000>;=0D -=0D - partitions {=0D - compatible =3D "fixed-partitions";=0D - #address-cells =3D <1>;=0D - #size-cells =3D <1>;=0D -=0D - partition@0 {=0D - label =3D "U-Boot";=0D - reg =3D <0x0 0x200000>;=0D - };=0D -=0D - partition@400000 {=0D - label =3D "Filesystem";=0D - reg =3D <0x200000 0xe00000>;=0D - };=0D - };=0D - };=0D -};=0D -=0D -/* SLM-1521-V2, CON6 */=0D -&cp0_pcie0 {=0D - status =3D "okay";=0D - num-lanes =3D <4>;=0D - num-viewport =3D <8>;=0D - /* Generic PHY, providing serdes lanes */=0D - phys =3D <&cp0_comphy0 0=0D - &cp0_comphy1 0=0D - &cp0_comphy2 0=0D - &cp0_comphy3 0>;=0D -};=0D -=0D -&cp0_sata0 {=0D - status =3D "okay";=0D - /* SLM-1521-V2, CON2 */=0D -};=0D -=0D -&cp0_mdio {=0D - status =3D "okay";=0D - phy0: ethernet-phy@0 {=0D - reg =3D <0>;=0D - };=0D - phy1: ethernet-phy@1 {=0D - reg =3D <1>;=0D - };=0D -};=0D -=0D -&cp0_ethernet {=0D - status =3D "okay";=0D -};=0D -=0D -/* SLM-1521-V2, CON9 */=0D -&cp0_eth0 {=0D - status =3D "okay";=0D - phy-mode =3D "10gbase-kr";=0D - /* Generic PHY, providing serdes lanes */=0D - phys =3D <&cp0_comphy4 0>;=0D - managed =3D "in-band-status";=0D - sfp =3D <&cp0_sfp_eth0>;=0D -};=0D -=0D -/* CON56 */=0D -&cp0_eth1 {=0D - status =3D "okay";=0D - phy =3D <&phy0>;=0D - phy-mode =3D "rgmii-id";=0D -};=0D -=0D -/* CON57 */=0D -&cp0_eth2 {=0D - status =3D "okay";=0D - phy =3D <&phy1>;=0D - phy-mode =3D "rgmii-id";=0D -};=0D diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dts b/Silico= n/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dts new file mode 100644 index 0000000..7f54f36 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dts @@ -0,0 +1,403 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)=0D +/*=0D + * Copyright (C) 2019 Marvell International Ltd.=0D + *=0D + * Device tree for the CN9130-DB board.=0D + */=0D +=0D +#include "cn9130.dtsi"=0D +=0D +/ {=0D + model =3D "Marvell Armada CN9130-DB";=0D +=0D + chosen {=0D + stdout-path =3D "serial0:115200n8";=0D + };=0D +=0D + aliases {=0D + gpio1 =3D &cp0_gpio1;=0D + gpio2 =3D &cp0_gpio2;=0D + i2c0 =3D &cp0_i2c0;=0D + ethernet0 =3D &cp0_eth0;=0D + ethernet1 =3D &cp0_eth1;=0D + ethernet2 =3D &cp0_eth2;=0D + spi1 =3D &cp0_spi0;=0D + spi2 =3D &cp0_spi1;=0D + };=0D +=0D + memory@00000000 {=0D + device_type =3D "memory";=0D + reg =3D <0x0 0x0 0x0 0x80000000>;=0D + };=0D +=0D + ap0_reg_sd_vccq: ap0_sd_vccq@0 {=0D + compatible =3D "regulator-gpio";=0D + regulator-name =3D "ap0_sd_vccq";=0D + regulator-min-microvolt =3D <1800000>;=0D + regulator-max-microvolt =3D <3300000>;=0D + gpios =3D <&expander0 8 GPIO_ACTIVE_HIGH>;=0D + states =3D <1800000 0x1 3300000 0x0>;=0D + };=0D +=0D + cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {=0D + compatible =3D "regulator-fixed";=0D + regulator-name =3D "cp0-xhci0-vbus";=0D + regulator-min-microvolt =3D <5000000>;=0D + regulator-max-microvolt =3D <5000000>;=0D + enable-active-high;=0D + gpio =3D <&expander0 0 GPIO_ACTIVE_HIGH>;=0D + };=0D +=0D + cp0_usb3_0_phy0: cp0_usb3_phy@0 {=0D + compatible =3D "usb-nop-xceiv";=0D + vcc-supply =3D <&cp0_reg_usb3_vbus0>;=0D + };=0D +=0D + cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {=0D + compatible =3D "regulator-fixed";=0D + regulator-name =3D "cp0-xhci1-vbus";=0D + regulator-min-microvolt =3D <5000000>;=0D + regulator-max-microvolt =3D <5000000>;=0D + enable-active-high;=0D + gpio =3D <&expander0 1 GPIO_ACTIVE_HIGH>;=0D + };=0D +=0D + cp0_usb3_0_phy1: cp0_usb3_phy@1 {=0D + compatible =3D "usb-nop-xceiv";=0D + vcc-supply =3D <&cp0_reg_usb3_vbus1>;=0D + };=0D +=0D + cp0_reg_sd_vccq: cp0_sd_vccq@0 {=0D + compatible =3D "regulator-gpio";=0D + regulator-name =3D "cp0_sd_vccq";=0D + regulator-min-microvolt =3D <1800000>;=0D + regulator-max-microvolt =3D <3300000>;=0D + gpios =3D <&expander0 15 GPIO_ACTIVE_HIGH>;=0D + states =3D <1800000 0x1=0D + 3300000 0x0>;=0D + };=0D +=0D + cp0_reg_sd_vcc: cp0_sd_vcc@0 {=0D + compatible =3D "regulator-fixed";=0D + regulator-name =3D "cp0_sd_vcc";=0D + regulator-min-microvolt =3D <3300000>;=0D + regulator-max-microvolt =3D <3300000>;=0D + gpio =3D <&expander0 14 GPIO_ACTIVE_HIGH>;=0D + enable-active-high;=0D + regulator-always-on;=0D + };=0D +=0D + cp0_sfp_eth0: sfp-eth@0 {=0D + compatible =3D "sff,sfp";=0D + i2c-bus =3D <&cp0_sfpp0_i2c>;=0D + los-gpio =3D <&cp0_module_expander1 11 GPIO_ACTIVE_HIGH>;= =0D + mod-def0-gpio =3D <&cp0_module_expander1 10 GPIO_ACTIVE_LO= W>;=0D + tx-disable-gpio =3D <&cp0_module_expander1 9 GPIO_ACTIVE_H= IGH>;=0D + tx-fault-gpio =3D <&cp0_module_expander1 8 GPIO_ACTIVE_HIG= H>;=0D + /*=0D + * SFP cages are unconnected on early PCBs because of an t= he I2C=0D + * lanes not being connected. Prevent the port for being=0D + * unusable by disabling the SFP node.=0D + */=0D + status =3D "disabled";=0D + };=0D +};=0D +=0D +&uart0 {=0D + status =3D "okay";=0D +};=0D +=0D +/* on-board eMMC - U9 */=0D +&ap_sdhci0 {=0D + pinctrl-names =3D "default";=0D + bus-width =3D <8>;=0D + mmc-ddr-1_8v;=0D + mmc-hs400-1_8v;=0D + vqmmc-supply =3D <&ap0_reg_sd_vccq>;=0D + status =3D "okay";=0D +};=0D +=0D +&cp0_crypto {=0D + status =3D "disabled";=0D +};=0D +=0D +&cp0_ethernet {=0D + status =3D "okay";=0D +};=0D +=0D +/* SLM-1521-V2, CON9 */=0D +&cp0_eth0 {=0D + status =3D "okay";=0D + phy-mode =3D "10gbase-kr";=0D + /* Generic PHY, providing serdes lanes */=0D + phys =3D <&cp0_comphy4 0>;=0D + managed =3D "in-band-status";=0D + sfp =3D <&cp0_sfp_eth0>;=0D +};=0D +=0D +/* CON56 */=0D +&cp0_eth1 {=0D + status =3D "okay";=0D + phy =3D <&phy0>;=0D + phy-mode =3D "rgmii-id";=0D +};=0D +=0D +/* CON57 */=0D +&cp0_eth2 {=0D + status =3D "okay";=0D + phy =3D <&phy1>;=0D + phy-mode =3D "rgmii-id";=0D +};=0D +=0D +&cp0_gpio1 {=0D + status =3D "okay";=0D +};=0D +=0D +&cp0_gpio2 {=0D + status =3D "okay";=0D +};=0D +=0D +&cp0_i2c0 {=0D + status =3D "okay";=0D + pinctrl-names =3D "default";=0D + pinctrl-0 =3D <&cp0_i2c0_pins>;=0D + clock-frequency =3D <100000>;=0D +=0D + /* U36 */=0D + expander0: pca953x@21 {=0D + compatible =3D "nxp,pca9555";=0D + pinctrl-names =3D "default";=0D + gpio-controller;=0D + #gpio-cells =3D <2>;=0D + reg =3D <0x21>;=0D + status =3D "okay";=0D + };=0D +=0D + /* U42 */=0D + eeprom0: eeprom@50 {=0D + compatible =3D "atmel,24c64";=0D + reg =3D <0x50>;=0D + pagesize =3D <0x20>;=0D + };=0D +=0D + /* U38 */=0D + eeprom1: eeprom@57 {=0D + compatible =3D "atmel,24c64";=0D + reg =3D <0x57>;=0D + pagesize =3D <0x20>;=0D + };=0D +};=0D +=0D +&cp0_i2c1 {=0D + status =3D "okay";=0D + clock-frequency =3D <100000>;=0D +=0D + /* SLM-1521-V2 - U3 */=0D + i2c-mux@72 { /* verify address - depends on dpr */=0D + compatible =3D "nxp,pca9544";=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + reg =3D <0x72>;=0D + cp0_sfpp0_i2c: i2c@0 {=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + reg =3D <0>;=0D + };=0D +=0D + i2c@1 {=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + reg =3D <1>;=0D + /* U12 */=0D + cp0_module_expander1: pca9555@21 {=0D + compatible =3D "nxp,pca9555";=0D + pinctrl-names =3D "default";=0D + gpio-controller;=0D + #gpio-cells =3D <2>;=0D + reg =3D <0x21>;=0D + };=0D +=0D + };=0D + };=0D +};=0D +=0D +&cp0_mdio {=0D + status =3D "okay";=0D +=0D + phy0: ethernet-phy@0 {=0D + reg =3D <0>;=0D + };=0D +=0D + phy1: ethernet-phy@1 {=0D + reg =3D <1>;=0D + };=0D +};=0D +=0D +/* U54 */=0D +&cp0_nand_controller {=0D + pinctrl-names =3D "default";=0D + pinctrl-0 =3D <&nand_pins &nand_rb>;=0D +=0D + nand@0 {=0D + reg =3D <0>;=0D + label =3D "main-storage";=0D + nand-rb =3D <0>;=0D + nand-ecc-mode =3D "hw";=0D + nand-on-flash-bbt;=0D + nand-ecc-strength =3D <8>;=0D + nand-ecc-step-size =3D <512>;=0D +=0D + partitions {=0D + compatible =3D "fixed-partitions";=0D + #address-cells =3D <1>;=0D + #size-cells =3D <1>;=0D +=0D + partition@0 {=0D + label =3D "U-Boot";=0D + reg =3D <0 0x200000>;=0D + };=0D + partition@200000 {=0D + label =3D "Linux";=0D + reg =3D <0x200000 0xd00000>;=0D + };=0D + partition@1000000 {=0D + label =3D "Filesystem";=0D + reg =3D <0x1000000 0x3f000000>;=0D + };=0D + };=0D + };=0D +};=0D +=0D +/* SLM-1521-V2, CON6 */=0D +&cp0_pcie0 {=0D + status =3D "okay";=0D + num-lanes =3D <4>;=0D + num-viewport =3D <8>;=0D + /* Generic PHY, providing serdes lanes */=0D + phys =3D <&cp0_comphy0 0=0D + &cp0_comphy1 0=0D + &cp0_comphy2 0=0D + &cp0_comphy3 0>;=0D +};=0D +=0D +&cp0_sata0 {=0D + status =3D "okay";=0D +=0D + /* SLM-1521-V2, CON2 */=0D + sata-port@1 {=0D + status =3D "okay";=0D + /* Generic PHY, providing serdes lanes */=0D + phys =3D <&cp0_comphy5 1>;=0D + };=0D +};=0D +=0D +/* CON 28 */=0D +&cp0_sdhci0 {=0D + status =3D "okay";=0D + pinctrl-names =3D "default";=0D + pinctrl-0 =3D <&cp0_sdhci_pins=0D + &cp0_sdhci_cd_pins>;=0D + bus-width =3D <4>;=0D + cd-gpios =3D <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;=0D + no-1-8-v;=0D + vqmmc-supply =3D <&cp0_reg_sd_vccq>;=0D + vmmc-supply =3D <&cp0_reg_sd_vcc>;=0D +};=0D +=0D +/* U55 */=0D +&cp0_spi1 {=0D + status =3D "disabled";=0D + pinctrl-names =3D "default";=0D + pinctrl-0 =3D <&cp0_spi0_pins>;=0D + reg =3D <0x700680 0x50>;=0D +=0D + spi-flash@0 {=0D + #address-cells =3D <0x1>;=0D + #size-cells =3D <0x1>;=0D + compatible =3D "jedec,spi-nor";=0D + reg =3D <0x0>;=0D + /* On-board MUX does not allow higher frequencies */=0D + spi-max-frequency =3D <40000000>;=0D +=0D + partitions {=0D + compatible =3D "fixed-partitions";=0D + #address-cells =3D <1>;=0D + #size-cells =3D <1>;=0D +=0D + partition@0 {=0D + label =3D "U-Boot-0";=0D + reg =3D <0x0 0x200000>;=0D + };=0D +=0D + partition@400000 {=0D + label =3D "Filesystem-0";=0D + reg =3D <0x200000 0xe00000>;=0D + };=0D + };=0D + };=0D +};=0D +=0D +&cp0_syscon0 {=0D + cp0_pinctrl: pinctrl {=0D + compatible =3D "marvell,cp115-standalone-pinctrl";=0D +=0D + cp0_i2c0_pins: cp0-i2c-pins-0 {=0D + marvell,pins =3D "mpp37", "mpp38";=0D + marvell,function =3D "i2c0";=0D + };=0D + cp0_i2c1_pins: cp0-i2c-pins-1 {=0D + marvell,pins =3D "mpp35", "mpp36";=0D + marvell,function =3D "i2c1";=0D + };=0D + cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {=0D + marvell,pins =3D "mpp0", "mpp1", "mpp2",=0D + "mpp3", "mpp4", "mpp5",=0D + "mpp6", "mpp7", "mpp8",=0D + "mpp9", "mpp10", "mpp11";=0D + marvell,function =3D "ge0";=0D + };=0D + cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {=0D + marvell,pins =3D "mpp44", "mpp45", "mpp46",=0D + "mpp47", "mpp48", "mpp49",=0D + "mpp50", "mpp51", "mpp52",=0D + "mpp53", "mpp54", "mpp55";=0D + marvell,function =3D "ge1";=0D + };=0D + cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {=0D + marvell,pins =3D "mpp43";=0D + marvell,function =3D "gpio";=0D + };=0D + cp0_sdhci_pins: cp0-sdhi-pins-0 {=0D + marvell,pins =3D "mpp56", "mpp57", "mpp58",=0D + "mpp59", "mpp60", "mpp61";=0D + marvell,function =3D "sdio";=0D + };=0D + cp0_spi0_pins: cp0-spi-pins-0 {=0D + marvell,pins =3D "mpp13", "mpp14", "mpp15", "mpp16= ";=0D + marvell,function =3D "spi1";=0D + };=0D + nand_pins: nand-pins {=0D + marvell,pins =3D "mpp15", "mpp16", "mpp17", "mpp18= ",=0D + "mpp19", "mpp20", "mpp21", "mpp22",= =0D + "mpp23", "mpp24", "mpp25", "mpp26",= =0D + "mpp27";=0D + marvell,function =3D "dev";=0D + };=0D + nand_rb: nand-rb {=0D + marvell,pins =3D "mpp13";=0D + marvell,function =3D "nf";=0D + };=0D + };=0D +};=0D +=0D +&cp0_usb3_0 {=0D + status =3D "okay";=0D + usb-phy =3D <&cp0_usb3_0_phy0>;=0D + phy-names =3D "usb";=0D +};=0D +=0D +&cp0_usb3_1 {=0D + status =3D "okay";=0D + usb-phy =3D <&cp0_usb3_0_phy1>;=0D + phy-names =3D "usb";=0D +};=0D diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130.dtsi b/Silicon/= Marvell/OcteonTx/DeviceTree/T91/cn9130.dtsi index 97ea923..6187a34 100644 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130.dtsi +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130.dtsi @@ -1,126 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)=0D /*=0D - * Copyright (C) 2018 Marvell International Ltd.=0D + * Copyright (C) 2019 Marvell International Ltd.=0D *=0D - * SPDX-License-Identifier: GPL-2.0=0D - * https://spdx.org/licenses=0D + * Device tree for the CN9130 SoC.=0D */=0D =0D -/*=0D - * Device Tree file for the CN 9130 SoC, made of an AP807 Quad and=0D - * three CP110.=0D - */=0D -=0D -#include "armada-ap806-quad.dtsi"=0D -=0D -/ {=0D - aliases {=0D - gpio1 =3D &cp0_gpio1;=0D - gpio2 =3D &cp0_gpio2;=0D - spi1 =3D &cp0_spi0;=0D - spi2 =3D &cp0_spi1;=0D - };=0D -};=0D -=0D -/* This defines used to calculate the base address of each CP */=0D -#define CP110_PCIE_MEM_SIZE(iface) ((iface =3D=3D 0) ? 0x1ff00000 : = 0xf00000)=0D -#define CP110_PCIE_BUS_MEM_CFG (0x82000000)=0D -=0D -/* CP110-0 Settings */=0D -#define CP110_NAME cp0=0D -#define CP110_NUM 0=0D -#define CP110_BASE f2000000=0D -#define CP110_PCIE0_BASE f2600000=0D -#define CP110_PCIE1_BASE f2620000=0D -#define CP110_PCIE2_BASE f2640000=0D -#define CP110_PCIEx_CPU_MEM_BASE(iface) ((iface =3D=3D 0) ? 0xc0000000 : = \=0D - (0xe0000000 + (iface - 1) * 0x100= 0000))=0D -#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface))= =0D -=0D -#include "armada-cp110.dtsi"=0D -=0D -#undef CP110_NUM=0D -#undef CP110_NAME=0D -#undef CP110_BASE=0D -#undef CP110_PCIE0_BASE=0D -#undef CP110_PCIE1_BASE=0D -#undef CP110_PCIE2_BASE=0D +#include "armada-ap807-quad.dtsi"=0D =0D / {=0D - model =3D "Marvell CN 9130";=0D + model =3D "Marvell Armada CN9130 SoC";=0D compatible =3D "marvell,cn9130", "marvell,armada-ap807-quad",=0D - "marvell,armada-ap806";=0D + "marvell,armada-ap807";=0D };=0D =0D -&cp0_crypto {=0D - status =3D "okay";=0D -};=0D -=0D -&cp0_gpio1 {=0D - status =3D "okay";=0D -};=0D -=0D -&cp0_gpio2 {=0D - status =3D "okay";=0D -};=0D -=0D -&cp0_syscon0 {=0D - cp0_pinctrl: pinctrl {=0D - compatible =3D "marvell,armada-7k-pinctrl";=0D -=0D - cp0_devbus_pins: cp0-devbus-pins {=0D - marvell,pins =3D "mpp15", "mpp16", "mpp17",=0D - "mpp18", "mpp19", "mpp20",=0D - "mpp21", "mpp22", "mpp23",=0D - "mpp24", "mpp25", "mpp26",=0D - "mpp27";=0D - marvell,function =3D "dev";=0D - };=0D +/*=0D + * Instantiate the internal CP115=0D + */=0D =0D - cp0_i2c0_pins: cp0-i2c-pins-0 {=0D - marvell,pins =3D "mpp37", "mpp38";=0D - marvell,function =3D "i2c0";=0D - };=0D - cp0_i2c1_pins: cp0-i2c-pins-1 {=0D - marvell,pins =3D "mpp35", "mpp36";=0D - marvell,function =3D "i2c1";=0D - };=0D - cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {=0D - marvell,pins =3D "mpp0", "mpp1", "mpp2",=0D - "mpp3", "mpp4", "mpp5",=0D - "mpp6", "mpp7", "mpp8",=0D - "mpp9", "mpp10", "mpp11";=0D - marvell,function =3D "ge0";=0D - };=0D - cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {=0D - marvell,pins =3D "mpp44", "mpp45", "mpp46",=0D - "mpp47", "mpp48", "mpp49",=0D - "mpp50", "mpp51", "mpp52",=0D - "mpp53", "mpp54", "mpp55";=0D - marvell,function =3D "ge1";=0D - };=0D - cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {=0D - marvell,pins =3D "mpp43";=0D - marvell,function =3D "gpio";=0D - };=0D - cp0_sdhci_pins: cp0-sdhi-pins-0 {=0D - marvell,pins =3D "mpp56", "mpp57", "mpp58",=0D - "mpp59", "mpp60", "mpp61";=0D - marvell,function =3D "sdio";=0D - };=0D - cp0_spi0_pins: cp0-spi-pins-0 {=0D - marvell,pins =3D "mpp13", "mpp14", "mpp15", "mpp16= ";=0D - marvell,function =3D "spi1";=0D - };=0D - nand_pins: nand-pins {=0D - marvell,pins =3D=0D - "mpp15", "mpp16", "mpp17", "mpp18", "mpp19",=0D - "mpp20", "mpp21", "mpp22", "mpp23", "mpp24",=0D - "mpp25", "mpp26", "mpp27";=0D - marvell,function =3D "dev";=0D - };=0D - nand_rb: nand-rb {=0D - marvell,pins =3D "mpp13";=0D - marvell,function =3D "nf";=0D - };=0D - };=0D -};=0D +#define CP11X_NAME cp0=0D +#define CP11X_BASE f2000000=0D +#define CP11X_PCIEx_MEM_BASE(iface) ((iface =3D=3D 0) ? 0xc0000000 : \=0D + 0xe0000000 + ((iface -= 1) * 0x1000000))=0D +#define CP11X_PCIEx_MEM_SIZE(iface) ((iface =3D=3D 0) ? 0x1ff00000 : 0xf00= 000)=0D +#define CP11X_PCIE0_BASE f2600000=0D +#define CP11X_PCIE1_BASE f2620000=0D +#define CP11X_PCIE2_BASE f2640000=0D +=0D +#include "armada-cp115.dtsi"=0D +=0D +#undef CP11X_NAME=0D +#undef CP11X_BASE=0D +#undef CP11X_PCIEx_MEM_BASE=0D +#undef CP11X_PCIEx_MEM_SIZE=0D +#undef CP11X_PCIE0_BASE=0D +#undef CP11X_PCIE1_BASE=0D +#undef CP11X_PCIE2_BASE=0D diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db-A.dts b/Sili= con/Marvell/OcteonTx/DeviceTree/T91/cn9131-db-A.dts deleted file mode 100644 index f08a748..0000000 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db-A.dts +++ /dev/null @@ -1,29 +0,0 @@ -/*=0D - * Copyright (C) 2018 Marvell International Ltd.=0D - *=0D - * SPDX-License-Identifier: GPL-2.0=0D - * https://spdx.org/licenses=0D - */=0D -=0D -#include "cn9130-db-A.dts"=0D -#include "cn9131-db.dtsi"=0D -=0D -/ {=0D - model =3D "Marvell CN9131 development board (CP NOR) setup(A)";=0D - compatible =3D "marvell,cn9131-db-A", "marvell,armada-ap807-quad",= =0D - "marvell,armada-ap807";=0D -};=0D -=0D -&cp1_ethernet {=0D - status =3D "okay";=0D -};=0D -=0D -/* CON50 */=0D -&cp1_eth0 {=0D - status =3D "okay";=0D - phy-mode =3D "10gbase-kr";=0D - /* Generic PHY, providing serdes lanes */=0D - phys =3D <&cp1_comphy4 0>;=0D - managed =3D "in-band-status";=0D - sfp =3D <&cp1_sfp_eth1>;=0D -};=0D diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi b/Silic= on/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dts similarity index 66% rename from Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi rename to Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dts index 9c9dfb6..3d5a67e 100644 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dts @@ -1,35 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)=0D /*=0D - * Copyright (C) 2018 Marvell International Ltd.=0D + * Copyright (C) 2019 Marvell International Ltd.=0D *=0D - * SPDX-License-Identifier: GPL-2.0=0D - * https://spdx.org/licenses=0D + * Device tree for the CN9131-DB board.=0D */=0D =0D -#undef CP110_NUM=0D -#undef CP110_NAME=0D -#undef CP110_BASE=0D -#undef CP110_PCIE0_BASE=0D -#undef CP110_PCIE1_BASE=0D -#undef CP110_PCIE2_BASE=0D -#undef CP110_PCIEx_CPU_MEM_BASE=0D -#undef CP110_PCIEx_MEM_BASE=0D -=0D -/* CP110-1 Settings */=0D -#define CP110_NAME cp1=0D -#define CP110_NUM 1=0D -#define CP110_BASE f4000000=0D -#define CP110_PCIE0_BASE f4600000=0D -#define CP110_PCIE1_BASE f4620000=0D -#define CP110_PCIE2_BASE f4640000=0D -#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe2000000 + (iface) * 0x1000000= )=0D -#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface))= =0D -=0D -#include "armada-cp110.dtsi"=0D +#include "cn9130-db.dts"=0D =0D / {=0D - model =3D "Marvell CN9131 development board";=0D - compatible =3D "marvell,cn9131-db", "marvell,armada-ap807-quad",=0D - "marvell,armada-ap807";=0D + model =3D "Marvell Armada CN9131-DB";=0D + compatible =3D "marvell,cn9131", "marvell,cn9130",=0D + "marvell,armada-ap807-quad", "marvell,armada-ap807";= =0D =0D aliases {=0D gpio3 =3D &cp1_gpio1;=0D @@ -63,12 +44,53 @@ tx-fault-gpio =3D <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>;=0D pinctrl-names =3D "default";=0D pinctrl-0 =3D <&cp1_sfp_pins>;=0D + /*=0D + * SFP cages are unconnected on early PCBs because of an t= he I2C=0D + * lanes not being connected. Prevent the port for being=0D + * unusable by disabling the SFP node.=0D + */=0D status =3D "disabled";=0D };=0D };=0D =0D +/*=0D + * Instantiate the first slave CP115=0D + */=0D +=0D +#define CP11X_NAME cp1=0D +#define CP11X_BASE f4000000=0D +#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))=0D +#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000=0D +#define CP11X_PCIE0_BASE f4600000=0D +#define CP11X_PCIE1_BASE f4620000=0D +#define CP11X_PCIE2_BASE f4640000=0D +=0D +#include "armada-cp115.dtsi"=0D +=0D +#undef CP11X_NAME=0D +#undef CP11X_BASE=0D +#undef CP11X_PCIEx_MEM_BASE=0D +#undef CP11X_PCIEx_MEM_SIZE=0D +#undef CP11X_PCIE0_BASE=0D +#undef CP11X_PCIE1_BASE=0D +#undef CP11X_PCIE2_BASE=0D +=0D &cp1_crypto {=0D + status =3D "disabled";=0D +};=0D +=0D +&cp1_ethernet {=0D + status =3D "okay";=0D +};=0D +=0D +/* CON50 */=0D +&cp1_eth0 {=0D status =3D "okay";=0D + phy-mode =3D "10gbase-kr";=0D + /* Generic PHY, providing serdes lanes */=0D + phys =3D <&cp1_comphy4 0>;=0D + managed =3D "in-band-status";=0D + sfp =3D <&cp1_sfp_eth1>;=0D };=0D =0D &cp1_gpio1 {=0D @@ -80,9 +102,9 @@ };=0D =0D &cp1_i2c0 {=0D + status =3D "okay";=0D pinctrl-names =3D "default";=0D pinctrl-0 =3D <&cp1_i2c0_pins>;=0D - status =3D "okay";=0D clock-frequency =3D <100000>;=0D };=0D =0D @@ -101,15 +123,20 @@ =0D &cp1_sata0 {=0D status =3D "okay";=0D +=0D + /* CON32 */=0D + sata-port@1 {=0D + /* Generic PHY, providing serdes lanes */=0D + phys =3D <&cp1_comphy5 1>;=0D + };=0D };=0D =0D /* U24 */=0D &cp1_spi1 {=0D + status =3D "okay";=0D pinctrl-names =3D "default";=0D pinctrl-0 =3D <&cp1_spi0_pins>;=0D - reg =3D <0x700680 0x50>, /* control */=0D - <0x2000000 0x1000000>; /* CS0 */=0D - status =3D "okay";=0D + reg =3D <0x700680 0x50>;=0D =0D spi-flash@0 {=0D #address-cells =3D <0x1>;=0D @@ -125,12 +152,12 @@ #size-cells =3D <1>;=0D =0D partition@0 {=0D - label =3D "U-Boot";=0D + label =3D "U-Boot-1";=0D reg =3D <0x0 0x200000>;=0D };=0D =0D partition@400000 {=0D - label =3D "Filesystem";=0D + label =3D "Filesystem-1";=0D reg =3D <0x200000 0xe00000>;=0D };=0D };=0D @@ -140,7 +167,7 @@ =0D &cp1_syscon0 {=0D cp1_pinctrl: pinctrl {=0D - compatible =3D "marvell,armada-7k-pinctrl";=0D + compatible =3D "marvell,cp115-standalone-pinctrl";=0D =0D cp1_i2c0_pins: cp1-i2c-pins-0 {=0D marvell,pins =3D "mpp37", "mpp38";=0D diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts b/Sili= con/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts deleted file mode 100644 index 724d7dc..0000000 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts +++ /dev/null @@ -1,70 +0,0 @@ -/*=0D - * copyright (c) 2019 marvell international ltd.=0D - *=0D - * spdx-license-identifier: gpl-2.0=0D - * https://spdx.org/licenses=0D - */=0D -=0D -#include "cn9131-db-A.dts"=0D -#include "cn9132-db.dtsi"=0D -=0D -/ {=0D - model =3D "Model: Marvell CN9132 development board (CP NOR) setup(= A)";=0D - compatible =3D "marvell,cn9132-db-A", "marvell,armada-ap807-quad",= =0D - "marvell,armada-ap807";=0D -=0D - aliases {=0D - gpio5 =3D &cp2_gpio1;=0D - gpio6 =3D &cp2_gpio2;=0D - ethernet5 =3D &cp2_eth0;=0D - };=0D -};=0D -=0D -&cp2_ethernet {=0D - status =3D "okay";=0D -};=0D -=0D -/* SLM-1521-V2, CON9 */=0D -&cp2_eth0 {=0D - status =3D "okay";=0D - phy-mode =3D "10gbase-kr";=0D - /* Generic PHY, providing serdes lanes */=0D - phys =3D <&cp2_comphy4 0>;=0D - managed =3D "in-band-status";=0D - sfp =3D <&cp2_sfp_eth0>;=0D -};=0D -=0D -/* SLM-1521-V2, CON6 */=0D -&cp2_pcie0 {=0D - status =3D "okay";=0D - num-lanes =3D <2>;=0D - num-viewport =3D <8>;=0D - /* Generic PHY, providing serdes lanes */=0D - phys =3D <&cp2_comphy0 0=0D - &cp2_comphy1 0>;=0D -};=0D -=0D -/* SLM-1521-V2, CON8 */=0D -&cp2_pcie2 {=0D - status =3D "okay";=0D - num-lanes =3D <1>;=0D - num-viewport =3D <8>;=0D - /* Generic PHY, providing serdes lanes */=0D - phys =3D <&cp2_comphy5 2>;=0D -};=0D -=0D -&cp2_sata0 {=0D - status =3D "okay";=0D -};=0D -=0D -/* CON 2 on SLM-1683 - microSD */=0D -&cp2_sdhci0 {=0D - status =3D "okay";=0D -};=0D -=0D -/* SLM-1521-V2, CON11 */=0D -&cp2_usb3_1 {=0D - status =3D "okay";=0D - /* Generic PHY, providing serdes lanes */=0D - phys =3D <&cp2_comphy3 1>;=0D -};=0D diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi b/Silic= on/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dts similarity index 54% rename from Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi rename to Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dts index 7dc6c6e..81ff188 100644 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dts @@ -1,35 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)=0D /*=0D - * copyright (c) 2019 marvell international ltd.=0D + * Copyright (C) 2019 Marvell International Ltd.=0D *=0D - * spdx-license-identifier: gpl-2.0=0D - * https://spdx.org/licenses=0D + * Device tree for the CN9132-DB board.=0D */=0D =0D -#undef CP110_NUM=0D -#undef CP110_NAME=0D -#undef CP110_BASE=0D -#undef CP110_PCIE0_BASE=0D -#undef CP110_PCIE1_BASE=0D -#undef CP110_PCIE2_BASE=0D -#undef CP110_PCIEx_CPU_MEM_BASE=0D -#undef CP110_PCIEx_MEM_BASE=0D -=0D -/* CP110-1 Settings */=0D -#define CP110_NAME cp2=0D -#define CP110_NUM 2=0D -#define CP110_BASE f6000000=0D -#define CP110_PCIE0_BASE f6600000=0D -#define CP110_PCIE1_BASE f6620000=0D -#define CP110_PCIE2_BASE f6640000=0D -#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe5000000 + (iface) * 0x1000000= )=0D -#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface))= =0D -=0D -#include "armada-cp110.dtsi"=0D +#include "cn9131-db.dts"=0D =0D / {=0D - model =3D "DB-CN-9132";=0D - compatible =3D "marvell,cn9132", "marvell,armada-ap807-quad",=0D - "marvell,armada-ap807";=0D + model =3D "Marvell Armada CN9132-DB";=0D + compatible =3D "marvell,cn9132", "marvell,cn9131", "marvell,cn9130= ",=0D + "marvell,armada-ap807-quad", "marvell,armada-ap807";= =0D +=0D + aliases {=0D + gpio5 =3D &cp2_gpio1;=0D + gpio6 =3D &cp2_gpio2;=0D + ethernet5 =3D &cp2_eth0;=0D + };=0D =0D cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 {=0D compatible =3D "regulator-fixed";=0D @@ -71,16 +58,57 @@ cp2_sfp_eth0: sfp-eth0 {=0D compatible =3D "sff,sfp";=0D i2c-bus =3D <&cp2_sfpp0_i2c>;=0D - los-gpio =3D <&cp2_moudle_expander1 11 GPIO_ACTIVE_HIGH>;= =0D - mod-def0-gpio =3D <&cp2_moudle_expander1 10 GPIO_ACTIVE_LO= W>;=0D - tx-disable-gpio =3D <&cp2_moudle_expander1 9 GPIO_ACTIVE_H= IGH>;=0D - tx-fault-gpio =3D <&cp2_moudle_expander1 8 GPIO_ACTIVE_HIG= H>;=0D + los-gpio =3D <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>;= =0D + mod-def0-gpio =3D <&cp2_module_expander1 10 GPIO_ACTIVE_LO= W>;=0D + tx-disable-gpio =3D <&cp2_module_expander1 9 GPIO_ACTIVE_H= IGH>;=0D + tx-fault-gpio =3D <&cp2_module_expander1 8 GPIO_ACTIVE_HIG= H>;=0D + /*=0D + * SFP cages are unconnected on early PCBs because of an t= he I2C=0D + * lanes not being connected. Prevent the port for being=0D + * unusable by disabling the SFP node.=0D + */=0D status =3D "disabled";=0D };=0D };=0D =0D +/*=0D + * Instantiate the second slave CP115=0D + */=0D +=0D +#define CP11X_NAME cp2=0D +#define CP11X_BASE f6000000=0D +#define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))=0D +#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000=0D +#define CP11X_PCIE0_BASE f6600000=0D +#define CP11X_PCIE1_BASE f6620000=0D +#define CP11X_PCIE2_BASE f6640000=0D +=0D +#include "armada-cp115.dtsi"=0D +=0D +#undef CP11X_NAME=0D +#undef CP11X_BASE=0D +#undef CP11X_PCIEx_MEM_BASE=0D +#undef CP11X_PCIEx_MEM_SIZE=0D +#undef CP11X_PCIE0_BASE=0D +#undef CP11X_PCIE1_BASE=0D +#undef CP11X_PCIE2_BASE=0D +=0D &cp2_crypto {=0D + status =3D "disabled";=0D +};=0D +=0D +&cp2_ethernet {=0D + status =3D "okay";=0D +};=0D +=0D +/* SLM-1521-V2, CON9 */=0D +&cp2_eth0 {=0D status =3D "okay";=0D + phy-mode =3D "10gbase-kr";=0D + /* Generic PHY, providing serdes lanes */=0D + phys =3D <&cp2_comphy4 0>;=0D + managed =3D "in-band-status";=0D + sfp =3D <&cp2_sfp_eth0>;=0D };=0D =0D &cp2_gpio1 {=0D @@ -111,7 +139,7 @@ #size-cells =3D <0>;=0D reg =3D <1>;=0D /* U12 */=0D - cp2_moudle_expander1: pca9555@21 {=0D + cp2_module_expander1: pca9555@21 {=0D compatible =3D "nxp,pca9555";=0D pinctrl-names =3D "default";=0D gpio-controller;=0D @@ -122,7 +150,38 @@ };=0D };=0D =0D +/* SLM-1521-V2, CON6 */=0D +&cp2_pcie0 {=0D + status =3D "okay";=0D + num-lanes =3D <2>;=0D + num-viewport =3D <8>;=0D + /* Generic PHY, providing serdes lanes */=0D + phys =3D <&cp2_comphy0 0=0D + &cp2_comphy1 0>;=0D +};=0D +=0D +/* SLM-1521-V2, CON8 */=0D +&cp2_pcie2 {=0D + status =3D "okay";=0D + num-lanes =3D <1>;=0D + num-viewport =3D <8>;=0D + /* Generic PHY, providing serdes lanes */=0D + phys =3D <&cp2_comphy5 2>;=0D +};=0D +=0D +&cp2_sata0 {=0D + status =3D "okay";=0D +=0D + /* SLM-1521-V2, CON4 */=0D + sata-port@0 {=0D + /* Generic PHY, providing serdes lanes */=0D + phys =3D <&cp2_comphy2 0>;=0D + };=0D +};=0D +=0D +/* CON 2 on SLM-1683 - microSD */=0D &cp2_sdhci0 {=0D + status =3D "okay";=0D pinctrl-names =3D "default";=0D pinctrl-0 =3D <&cp2_sdhci_pins>;=0D bus-width =3D <4>;=0D @@ -132,7 +191,7 @@ =0D &cp2_syscon0 {=0D cp2_pinctrl: pinctrl {=0D - compatible =3D "marvell,armada-7k-pinctrl";=0D + compatible =3D "marvell,cp115-standalone-pinctrl";=0D =0D cp2_i2c0_pins: cp2-i2c-pins-0 {=0D marvell,pins =3D "mpp37", "mpp38";=0D @@ -152,8 +211,11 @@ phy-names =3D "usb";=0D };=0D =0D +/* SLM-1521-V2, CON11 */=0D &cp2_usb3_1 {=0D status =3D "okay";=0D usb-phy =3D <&cp2_usb3_0_phy1>;=0D phy-names =3D "usb";=0D + /* Generic PHY, providing serdes lanes */=0D + phys =3D <&cp2_comphy3 1>;=0D };=0D --=20 2.29.0