From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web09.8927.1616741273807615722 for ; Thu, 25 Mar 2021 23:47:53 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.31, mailfrom: ray.ni@intel.com) IronPort-SDR: xdTnZCdCzZoHDH5GWvKaVujh/PkQul5cD4xkP4/sqMezmqq2bb8btYXLLaZW8K5fpJxj89OPCv 0HNeuPSc7ZXQ== X-IronPort-AV: E=McAfee;i="6000,8403,9934"; a="252444637" X-IronPort-AV: E=Sophos;i="5.81,279,1610438400"; d="scan'208";a="252444637" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Mar 2021 23:47:52 -0700 IronPort-SDR: cIPJVrpLV2B1Yj+6Djb/Wr4lEhayATWxW6UUzvAMrTIELKpMlWxBu7oovv8+L3CUk1DIipPsVX 5ddacEEd/atA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,279,1610438400"; d="scan'208";a="377143108" Received: from ray-dev.ccr.corp.intel.com ([10.239.158.87]) by orsmga006.jf.intel.com with ESMTP; 25 Mar 2021 23:47:51 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Cc: Rangasai V Chaganty Subject: [PATCH] IntelSiliconPkg: Define PCDs for microcode location in flash Date: Fri, 26 Mar 2021 14:47:41 +0800 Message-Id: <20210326064741.1937-1-ray.ni@intel.com> X-Mailer: git-send-email 2.27.0.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable 3 PCDs are defined assuming that microcode is put in the end of a FV: PcdFlashFvMicrocodeBase: The base address of the microcode FV PcdFlashFvMicrocodeSize: The size of the microcode FV PcdFlashMicrocodeOffset: The microcode offset relative to the FV base address The 3 new PCDs are to replace the following existing PCDs in MinPlatformPkg and IntelFsp2WrapperPkg. The ones in MinPlatformPkg will be removed in a separate patch. The ones in IntelFsp2WrapperPkg will be re-positioned as only using inside IntelFsp2WrapperPkg\Library\SecFspWrapperPlatformSecLibSample. Defining PCDs in IntelSiliconPkg is because certain close-source silicon code depends on these PCDs but the silicon code cannot depend on MinPlatformPkg. MinPlatformPkg contains the below 3 PCDs: PcdFlashFvMicrocodeBase: Same meaning as IntelSiliconPkg.PcdFlashFvMicrocodeBase PcdFlashFvMicrocodeSize: Same meaning as IntelSiliconPkg.PcdFlashFvMicrocodeSize PcdFlashFvMicrocodeOffset: The FV offset relative to the firmware base address. Note: MinPlatformPkg doesn't contain the PCD that tells the microcode offset relative to the FV base address. IntelFsp2WrapperPkg contains the below 3 PCDs: PcdCpuMicrocodePatchAddress: Same meaning as IntelSiliconPkg.PcdFlashFvMicrocodeBase PcdCpuMicrocodePatchRegionSize: Same meaning as IntelSiliconPkg.PcdFlashFvMicrocodeSize PcdFlashMicrocodeOffset: Same meaning as IntelSiliconPkg.PcdFlashMicrocodeOffset Change-Id: I708abfa4a9309cbaedd5c4e4f483ec9f0d5e7625 Reviewed-by: Ray Ni Cc: Rangasai V Chaganty --- Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec b/Silicon/In= tel/IntelSiliconPkg/IntelSiliconPkg.dec index 4a2cbca5..6611c3af 100644 --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec @@ -3,7 +3,7 @@ #=0D # This package provides common open source Intel silicon modules.=0D #=0D -# Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.
=0D +# Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.
=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D ##=0D @@ -90,6 +90,13 @@ # @Prompt Error code for VTd error.=0D gIntelSiliconPkgTokenSpaceGuid.PcdErrorCodeVTdError|0x02008000|UINT32|0x= 00000005=0D =0D + gIntelSiliconPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase|0|UINT32|0x000000= 07=0D + gIntelSiliconPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize|0|UINT32|0x000000= 08=0D +=0D + ## This is the microcode offset relative to the FV base address.=0D + # Microcode address equals to PcdFlashFvMicrocodeBase + PcdFlashMicroco= deOffset.=0D + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeOffset|0|UINT32|0x000000= 0A=0D +=0D [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]=0D ## This is the GUID of the FFS which contains the Graphics Video BIOS Ta= ble (VBT)=0D # The VBT content is stored as a RAW section which is consumed by GOP PE= I/UEFI driver.=0D --=20 2.27.0.windows.1