From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga05.intel.com (mga05.intel.com []) by mx.groups.io with SMTP id smtpd.web10.9844.1616747994654107959 for ; Fri, 26 Mar 2021 01:40:14 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: dandan.bi@intel.com) IronPort-SDR: x4gnUtX4zfWgT8PaCN3suDsRxRPCqCQvDcpgOr8BajyvAVJCLO3nZfWHIulskxPHgQUcSSjv6a E1Ke8PMtGgOA== X-IronPort-AV: E=McAfee;i="6000,8403,9934"; a="276244883" X-IronPort-AV: E=Sophos;i="5.81,279,1610438400"; d="scan'208";a="276244883" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Mar 2021 01:40:14 -0700 IronPort-SDR: mYIAnVQUDcN11PvMMHLe9wRbSFji0841CsKJ/sLEzZbdOQZqFAELGKMEXFJGE442sMYkRswqDr qud1jkvkzzPw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,279,1610438400"; d="scan'208";a="377173937" Received: from unknown (HELO shwdeOpenPSI114.ccr.corp.intel.com) ([10.239.154.141]) by orsmga006.jf.intel.com with ESMTP; 26 Mar 2021 01:40:13 -0700 From: "Dandan Bi" To: devel@edk2.groups.io Cc: Abner Chang , Daniel Schaefer , Gilbert Chen Subject: [edk2-platforms] [patch V3 33/35] Silicon/RISC_V: Consume MdeLibs.dsc.inc for RegisterFilterLib Date: Fri, 26 Mar 2021 16:39:20 +0800 Message-Id: <20210326083922.24340-34-dandan.bi@intel.com> X-Mailer: git-send-email 2.18.0.windows.1 In-Reply-To: <20210326083922.24340-1-dandan.bi@intel.com> References: <20210326083922.24340-1-dandan.bi@intel.com> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246 MdeLibs.dsc.inc was added for some basic/default library instances provided by MdePkg and RegisterFilterLibNull Library was also added into it as the first version of MdeLibs.dsc.inc. So update platform dsc to consume MdeLibs.dsc.inc for RegisterFilterLibNull which will be consumed by IoLib and BaseLib. Cc: Abner Chang Cc: Daniel Schaefer Cc: Gilbert Chen Signed-off-by: Dandan Bi Reviewed-by: Abner Chang --- V3: Update plaftom dsc to consume the MdeLibs.dsc.inc outside the common [LibraryClasses] section since we can specify different [LibraryClasses] section for libary instances in MdeLibs.dsc.inc. --- Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc index 5f88f5e89f..5c5cfcb525 100644 --- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc +++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc @@ -34,10 +34,12 @@ [BuildOptions] # ################################################################################ [SkuIds] 0|DEFAULT +!include MdePkg/MdeLibs.dsc.inc + [LibraryClasses.common] CpuExceptionHandlerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf RiscVCpuLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.inf RiscVEdk2SbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf RiscVOpensbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf -- 2.18.0.windows.1