From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web12.703.1617153616694518513 for ; Tue, 30 Mar 2021 18:20:16 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.151, mailfrom: jiaxin.wu@intel.com) IronPort-SDR: xTfvnzqc83l4r4epuvJ37bqmFYEBvKNBMG87cI5MxFeR0MKl8b2kzQDaig2UBewbUkqjurBDQC /w7IOrU0XfxA== X-IronPort-AV: E=McAfee;i="6000,8403,9939"; a="171916580" X-IronPort-AV: E=Sophos;i="5.81,291,1610438400"; d="scan'208";a="171916580" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2021 18:20:12 -0700 IronPort-SDR: DaFWjH0nU2cPtWEx9DGxozOLQL4cVnaGjdPO1vRCrZrWuXe9xn+qR/Z3GbOpbTLIWLyaSFNQmr 7vNGAR/l+Rug== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,291,1610438400"; d="scan'208";a="393829573" Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.79]) by orsmga002.jf.intel.com with ESMTP; 30 Mar 2021 18:20:10 -0700 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu , Zhang Hongbin1 Subject: [PATCH v1] MdePkg: Support Extended Control Register(XCR) Read and Write. Date: Wed, 31 Mar 2021 09:20:07 +0800 Message-Id: <20210331012007.12824-1-Jiaxin.wu@intel.com> X-Mailer: git-send-email 2.16.2.windows.1 https://bugzilla.tianocore.org/show_bug.cgi?id=3284 This patch is to support Extended Control Register(XCR) Read and Write. Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Signed-off-by: Zhang Hongbin1 Signed-off-by: Jiaxin Wu --- MdePkg/Include/Library/BaseLib.h | 46 ++++++++++++++++++++++++++++++- MdePkg/Library/BaseLib/BaseLib.inf | 4 ++- MdePkg/Library/BaseLib/Ia32/ReadXcr.nasm | 31 +++++++++++++++++++++ MdePkg/Library/BaseLib/Ia32/WriteXcr.nasm | 34 +++++++++++++++++++++++ 4 files changed, 113 insertions(+), 2 deletions(-) create mode 100644 MdePkg/Library/BaseLib/Ia32/ReadXcr.nasm create mode 100644 MdePkg/Library/BaseLib/Ia32/WriteXcr.nasm diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h index 1171a0ffb5..c51633ad73 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -1,10 +1,10 @@ /** @file Provides string functions, linked list functions, math functions, synchronization functions, file path functions, and CPU architecture-specific functions. -Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
Copyright (c) Microsoft Corporation.
Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent @@ -7493,7 +7493,51 @@ PatchInstructionX86 ( OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd, IN UINT64 PatchValue, IN UINTN ValueSize ); +/** + Returns a 64-bit Extended Control Register(XCR). + + Reads and returns the 64-bit XCR specified by Index. No parameter checking is + performed on Index, and some Index values may cause CPU exceptions. The + caller must either guarantee that Index is valid, or the caller must set up + exception handlers to catch the exceptions. This function is only available + on IA-32 and x64. + + @param Index The 32-bit XCR index to read. + + @return The value of the XCR identified by Index. + +**/ +UINT64 +EFIAPI +AsmReadXcr ( + IN UINT32 Index + ); + +/** + Writes a 64-bit value to a Extended Control Register(XCR), and returns the + value. + + Writes the 64-bit value specified by Value to the XCR specified by Index. The + 64-bit value written to the XCR is returned. No parameter checking is + performed on Index or Value, and some of these may cause CPU exceptions. The + caller must either guarantee that Index and Value are valid, or the caller + must establish proper exception handlers. This function is only available on + IA-32 and x64. + + @param Index The 32-bit XCR index to write. + @param Value The 64-bit value to write to the XCR. + + @return Value + +**/ +UINT64 +EFIAPI +AsmWriteXcr ( + IN UINT32 Index, + IN UINT64 Value + ); + #endif // defined (MDE_CPU_IA32) || defined (MDE_CPU_X64) #endif // !defined (__BASE_LIB__) diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf index 3b85c56c3c..e62031ea11 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -1,9 +1,9 @@ ## @file # Base Library implementation. # -# Copyright (c) 2007 - 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent @@ -63,10 +63,12 @@ BaseLibInternals.h [Sources.Ia32] Ia32/WriteTr.nasm Ia32/Lfence.nasm + Ia32/ReadXcr.nasm + Ia32/WriteXcr.nasm Ia32/Wbinvd.c | MSFT Ia32/WriteMm7.c | MSFT Ia32/WriteMm6.c | MSFT Ia32/WriteMm5.c | MSFT diff --git a/MdePkg/Library/BaseLib/Ia32/ReadXcr.nasm b/MdePkg/Library/BaseLib/Ia32/ReadXcr.nasm new file mode 100644 index 0000000000..5d50d8ba01 --- /dev/null +++ b/MdePkg/Library/BaseLib/Ia32/ReadXcr.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2021, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; ReadXcr.Asm +; +; Abstract: +; +; AsmReadXcr function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINT64 +; EFIAPI +; AsmReadXcr ( +; IN UINT32 Index +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmReadXcr) +ASM_PFX(AsmReadXcr): + mov ecx, [esp + 4] + xgetbv + ret \ No newline at end of file diff --git a/MdePkg/Library/BaseLib/Ia32/WriteXcr.nasm b/MdePkg/Library/BaseLib/Ia32/WriteXcr.nasm new file mode 100644 index 0000000000..009d41864b --- /dev/null +++ b/MdePkg/Library/BaseLib/Ia32/WriteXcr.nasm @@ -0,0 +1,34 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2021, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; WriteXcr.nasm +; +; Abstract: +; +; AsmWriteXcr function +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINT64 +; EFIAPI +; AsmWriteXcr ( +; IN UINT32 Index, +; IN UINT64 Value +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmWriteXcr) +ASM_PFX(AsmWriteXcr): + mov edx, [esp + 12] + mov eax, [esp + 8] + mov ecx, [esp + 4] + xsetbv + ret \ No newline at end of file -- 2.16.2.windows.1