From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga17.intel.com (mga17.intel.com []) by mx.groups.io with SMTP id smtpd.web10.12209.1617343235829209758 for ; Thu, 01 Apr 2021 23:00:38 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: ray.ni@intel.com) IronPort-SDR: tcBaMiErrlP6RTS5ePa/FIx71djSuKvWWGbr9qWMRQmtLpYWKZO0gK15pWmJhuyjNe77JWSOf7 9GDd5EARqvRw== X-IronPort-AV: E=McAfee;i="6000,8403,9941"; a="172428353" X-IronPort-AV: E=Sophos;i="5.81,298,1610438400"; d="scan'208";a="172428353" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Apr 2021 23:00:36 -0700 IronPort-SDR: Ppp1HbFq8zOtuRdKgwZ4sMcQ5Znf9I2wfYwN4EyK4xj4I+axV5GMTVOsOTUMn3j/qEJZokluNt 8yyVr5gLSw6A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,298,1610438400"; d="scan'208";a="413030662" Received: from ray-dev.ccr.corp.intel.com ([10.239.158.87]) by fmsmga008.fm.intel.com with ESMTP; 01 Apr 2021 23:00:34 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Cc: Rangasai V Chaganty , Siyuan Fu Subject: [PATCH 3/3] IntelSiliconPkg/ShadowMicrocodePei: Consume MicrocodeLib Date: Fri, 2 Apr 2021 14:00:21 +0800 Message-Id: <20210402060021.982-4-ray.ni@intel.com> X-Mailer: git-send-email 2.27.0.windows.1 In-Reply-To: <20210402060021.982-1-ray.ni@intel.com> References: <20210402060021.982-1-ray.ni@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Signed-off-by: Ray Ni Cc: Rangasai V Chaganty Cc: Siyuan Fu --- .../ShadowMicrocode/ShadowMicrocodePei.c | 155 ++---------------- .../ShadowMicrocode/ShadowMicrocodePei.inf | 3 +- 2 files changed, 13 insertions(+), 145 deletions(-) diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMi= crocodePei.c b/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/Shadow= MicrocodePei.c index 98a7aed697..4e4b69a0ca 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocode= Pei.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocode= Pei.c @@ -1,7 +1,7 @@ /** @file=0D FIT based microcode shadow PEIM.=0D =0D -Copyright (c) 2020, Intel Corporation. All rights reserved.
=0D +Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D **/=0D @@ -13,6 +13,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include =0D #include =0D #include =0D +#include =0D #include =0D #include =0D #include =0D @@ -70,118 +71,6 @@ EFI_PEI_PPI_DESCRIPTOR mPeiShadowMicrocodePpi= List[] =3D { }=0D };=0D =0D -/**=0D - Determine if a microcode patch matchs the specific processor signature a= nd flag.=0D -=0D - @param[in] CpuIdCount Number of elements in MicrocodeCpuId a= rray.=0D - @param[in] MicrocodeCpuId A pointer to an array of EDKII_PEI_MIC= ROCODE_CPU_ID=0D - structures.=0D - @param[in] ProcessorSignature The processor signature field value=0D - supported by a microcode patch.=0D - @param[in] ProcessorFlags The prcessor flags field value support= ed by=0D - a microcode patch.=0D -=0D - @retval TRUE The specified microcode patch will be loaded.=0D - @retval FALSE The specified microcode patch will not be loaded.=0D -**/=0D -BOOLEAN=0D -IsProcessorMatchedMicrocodePatch (=0D - IN UINTN CpuIdCount,=0D - IN EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuId,=0D - IN UINT32 ProcessorSignature,=0D - IN UINT32 ProcessorFlags=0D - )=0D -{=0D - UINTN Index;=0D -=0D - for (Index =3D 0; Index < CpuIdCount; Index++) {=0D - if ((ProcessorSignature =3D=3D MicrocodeCpuId[Index].ProcessorSignatur= e) &&=0D - (ProcessorFlags & (1 << MicrocodeCpuId[Index].PlatformId)) !=3D 0)= {=0D - return TRUE;=0D - }=0D - }=0D -=0D - return FALSE;=0D -}=0D -=0D -/**=0D - Check the 'ProcessorSignature' and 'ProcessorFlags' of the microcode=0D - patch header with the CPUID and PlatformID of the processors within=0D - system to decide if it will be copied into memory.=0D -=0D - @param[in] CpuIdCount Number of elements in MicrocodeCpuId a= rray.=0D - @param[in] MicrocodeCpuId A pointer to an array of EDKII_PEI_MIC= ROCODE_CPU_ID=0D - structures.=0D - @param[in] MicrocodeEntryPoint The pointer to the microcode patch hea= der.=0D -=0D - @retval TRUE The specified microcode patch need to be loaded.=0D - @retval FALSE The specified microcode patch dosen't need to be loaded= .=0D -**/=0D -BOOLEAN=0D -IsMicrocodePatchNeedLoad (=0D - IN UINTN CpuIdCount,=0D - IN EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuId,=0D - CPU_MICROCODE_HEADER *MicrocodeEntryPoint=0D - )=0D -{=0D - BOOLEAN NeedLoad;=0D - UINTN DataSize;=0D - UINTN TotalSize;=0D - CPU_MICROCODE_EXTENDED_TABLE_HEADER *ExtendedTableHeader;=0D - UINT32 ExtendedTableCount;=0D - CPU_MICROCODE_EXTENDED_TABLE *ExtendedTable;=0D - UINTN Index;=0D -=0D - if (FeaturePcdGet (PcdShadowAllMicrocode)) {=0D - return TRUE;=0D - }=0D -=0D - //=0D - // Check the 'ProcessorSignature' and 'ProcessorFlags' in microcode patc= h header.=0D - //=0D - NeedLoad =3D IsProcessorMatchedMicrocodePatch (=0D - CpuIdCount,=0D - MicrocodeCpuId,=0D - MicrocodeEntryPoint->ProcessorSignature.Uint32,=0D - MicrocodeEntryPoint->ProcessorFlags=0D - );=0D -=0D - //=0D - // If the Extended Signature Table exists, check if the processor is in = the=0D - // support list=0D - //=0D - DataSize =3D MicrocodeEntryPoint->DataSize;=0D - TotalSize =3D (DataSize =3D=3D 0) ? 2048 : MicrocodeEntryPoint->TotalSiz= e;=0D - if ((!NeedLoad) && (DataSize !=3D 0) &&=0D - (TotalSize - DataSize > sizeof (CPU_MICROCODE_HEADER) +=0D - sizeof (CPU_MICROCODE_EXTENDED_TABLE_HEADER)= )) {=0D - ExtendedTableHeader =3D (CPU_MICROCODE_EXTENDED_TABLE_HEADER *) ((UINT= 8 *) (MicrocodeEntryPoint)=0D - + DataSize + sizeof (CPU_MICROCODE_HEADER));=0D - ExtendedTableCount =3D ExtendedTableHeader->ExtendedSignatureCount;=0D - ExtendedTable =3D (CPU_MICROCODE_EXTENDED_TABLE *) (ExtendedTabl= eHeader + 1);=0D -=0D - for (Index =3D 0; Index < ExtendedTableCount; Index ++) {=0D - //=0D - // Check the 'ProcessorSignature' and 'ProcessorFlag' of the Extende= d=0D - // Signature Table entry with the CPUID and PlatformID of the proces= sors=0D - // within system to decide if it will be copied into memory=0D - //=0D - NeedLoad =3D IsProcessorMatchedMicrocodePatch (=0D - CpuIdCount,=0D - MicrocodeCpuId,=0D - ExtendedTable->ProcessorSignature.Uint32,=0D - ExtendedTable->ProcessorFlag=0D - );=0D - if (NeedLoad) {=0D - break;=0D - }=0D - ExtendedTable ++;=0D - }=0D - }=0D -=0D - return NeedLoad;=0D -}=0D -=0D /**=0D Actual worker function that shadows the required microcode patches into = memory.=0D =0D @@ -439,6 +328,11 @@ ShadowMicrocode ( return EFI_OUT_OF_RESOURCES;=0D }=0D =0D + if (FeaturePcdGet (PcdShadowAllMicrocode)) {=0D + MicrocodeCpuId =3D NULL;=0D + CpuIdCount =3D 0;=0D + }=0D +=0D //=0D // Fill up microcode patch info buffer according to FIT table.=0D //=0D @@ -447,37 +341,10 @@ ShadowMicrocode ( for (Index =3D 0; Index < EntryNum; Index++) {=0D if (FitEntry[Index].Type =3D=3D FIT_TYPE_01_MICROCODE) {=0D MicrocodeEntryPoint =3D (CPU_MICROCODE_HEADER *) (UINTN) FitEntry[In= dex].Address;=0D -=0D - if (*(UINT32 *) MicrocodeEntryPoint =3D=3D 0xFFFFFFFF) {=0D - //=0D - // An empty slot for reserved microcode update, skip to check next= entry.=0D - //=0D - continue;=0D - }=0D -=0D - if (MicrocodeEntryPoint->HeaderVersion !=3D 0x1) {=0D - //=0D - // Not a valid microcode header, skip to check next entry.=0D - //=0D - continue;=0D - }=0D -=0D - DataSize =3D MicrocodeEntryPoint->DataSize;=0D - TotalSize =3D (DataSize =3D=3D 0) ? 2048 : MicrocodeEntryPoint->Tota= lSize;=0D - if ( (UINTN)MicrocodeEntryPoint > (MAX_ADDRESS - TotalSize) ||=0D - (DataSize & 0x3) !=3D 0 ||=0D - (TotalSize & (SIZE_1KB - 1)) !=3D 0 ||=0D - TotalSize < DataSize=0D - ) {=0D - //=0D - // Not a valid microcode header, skip to check next entry.=0D - //=0D - continue;=0D - }=0D -=0D - if (IsMicrocodePatchNeedLoad (CpuIdCount, MicrocodeCpuId, MicrocodeE= ntryPoint)) {=0D - PatchInfoBuffer[PatchCount].Address =3D (UINTN) MicrocodeEntry= Point;=0D - PatchInfoBuffer[PatchCount].Size =3D TotalSize;=0D + TotalSize =3D GetMicrocodeLength (MicrocodeEntryPoint);=0D + if (IsValidMicrocode (MicrocodeEntryPoint, TotalSize, MicrocodeCpuId= , CpuIdCount, FALSE)) {=0D + PatchInfoBuffer[PatchCount].Address =3D (UINTN) MicrocodeEntryPoin= t;=0D + PatchInfoBuffer[PatchCount].Size =3D TotalSize;=0D TotalLoadSize +=3D TotalSize;=0D PatchCount++;=0D }=0D diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMi= crocodePei.inf b/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/Shad= owMicrocodePei.inf index 581780add8..5ee225297d 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocode= Pei.inf +++ b/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocode= Pei.inf @@ -1,7 +1,7 @@ ### @file=0D # FIT based microcode shadow PEIM.=0D #=0D -# Copyright (c) 2020, Intel Corporation. All rights reserved.
=0D +# Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -25,6 +25,7 @@ BaseMemoryLib=0D HobLib=0D PeiServicesLib=0D + MicrocodeLib=0D =0D [Packages]=0D MdePkg/MdePkg.dec=0D --=20 2.27.0.windows.1