* [edk2-platforms][PATCH V1 1/8] Platform/Sgi: Helper macros for PPTT Table
2021-04-02 9:12 [edk2-platforms][PATCH V1 0/8] Platform/Sgi: Add PPTT table for SGI/RD platforms Pranav Madhu
@ 2021-04-02 9:12 ` Pranav Madhu
2021-04-13 9:18 ` [edk2-devel] " PierreGondois
2021-04-02 9:12 ` [edk2-platforms][PATCH V1 2/8] Platform/Sgi: ACPI PPTT table for SGI-575 platform Pranav Madhu
` (6 subsequent siblings)
7 siblings, 1 reply; 14+ messages in thread
From: Pranav Madhu @ 2021-04-02 9:12 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Leif Lindholm, Sami Mujawar
Add helper macros for the creation for PPTT table. These macros help
with initializing processor hierarchy node structure, cache type
structure and ID structure.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
| 163 +++++++++++++++++++-
1 file changed, 162 insertions(+), 1 deletion(-)
--git a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
index 8d715de173c9..7ceb090a78e9 100644
--- a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
+++ b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
@@ -1,6 +1,6 @@
/** @file
*
-* Copyright (c) 2018-2020, ARM Limited. All rights reserved.
+* Copyright (c) 2018-2021, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -20,6 +20,132 @@
#define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('A','R','M',' ')
#define EFI_ACPI_ARM_CREATOR_REVISION 0x00000099
+#define CORE_COUNT FixedPcdGet32 (PcdCoreCount)
+#define CLUSTER_COUNT FixedPcdGet32 (PcdClusterCount)
+
+#pragma pack(1)
+// PPTT processor core structure
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core;
+ UINT32 Offset[2];
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE DCache;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE ICache;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache;
+} RD_PPTT_CORE;
+
+// PPTT processor cluster structure
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster;
+ UINT32 Offset;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L3Cache;
+ RD_PPTT_CORE Core[CORE_COUNT];
+} RD_PPTT_CLUSTER;
+
+// PPTT processor cluster structure without cache
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster;
+ UINT32 Offset;
+ RD_PPTT_CORE Core[CORE_COUNT];
+} RD_PPTT_MINIMAL_CLUSTER;
+
+// PPTT processor package structure
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package;
+ UINT32 Offset;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc;
+ RD_PPTT_MINIMAL_CLUSTER Cluster[CLUSTER_COUNT];
+} RD_PPTT_SLC_PACKAGE;
+#pragma pack ()
+
+//
+// PPTT processor structure flags for different SoC components as defined in
+// ACPI 6.3 specification
+//
+
+// Processor structure flags for SoC package
+#define PPTT_PROCESSOR_PACKAGE_FLAGS \
+ { \
+ EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL, \
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, \
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, \
+ EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, \
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL \
+ }
+
+// Processor structure flags for cluster
+#define PPTT_PROCESSOR_CLUSTER_FLAGS \
+ { \
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, \
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, \
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, \
+ EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, \
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL \
+ }
+
+// Processor structure flags for single-thread core
+#define PPTT_PROCESSOR_CORE_FLAGS \
+ { \
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, \
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, \
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, \
+ EFI_ACPI_6_3_PPTT_NODE_IS_LEAF \
+ }
+
+// Processor structure flags for multi-thread core
+#define PPTT_PROCESSOR_CORE_THREADED_FLAGS \
+ { \
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, \
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, \
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, \
+ EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, \
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL \
+ }
+
+// Processor structure flags for CPU thread
+#define PPTT_PROCESSOR_THREAD_FLAGS \
+ { \
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, \
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, \
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_THREAD, \
+ EFI_ACPI_6_3_PPTT_NODE_IS_LEAF \
+ }
+
+// PPTT cache structure flags as defined in ACPI 6.3 Specification
+#define PPTT_CACHE_STRUCTURE_FLAGS \
+ { \
+ EFI_ACPI_6_3_PPTT_CACHE_SIZE_VALID, \
+ EFI_ACPI_6_3_PPTT_NUMBER_OF_SETS_VALID, \
+ EFI_ACPI_6_3_PPTT_ASSOCIATIVITY_VALID, \
+ EFI_ACPI_6_3_PPTT_ALLOCATION_TYPE_VALID, \
+ EFI_ACPI_6_3_PPTT_CACHE_TYPE_VALID, \
+ EFI_ACPI_6_3_PPTT_WRITE_POLICY_VALID, \
+ EFI_ACPI_6_3_PPTT_LINE_SIZE_VALID \
+ }
+
+// PPTT cache attributes for data cache
+#define PPTT_DATA_CACHE_ATTR \
+ { \
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, \
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK \
+ }
+
+// PPTT cache attributes for instruction cache
+#define PPTT_INST_CACHE_ATTR \
+ { \
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ, \
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, \
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK \
+ }
+
+// PPTT cache attributes for unified cache
+#define PPTT_UNIFIED_CACHE_ATTR \
+ { \
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, \
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK \
+ }
+
// A macro to initialise the common header part of EFI ACPI tables as defined by
// EFI_ACPI_DESCRIPTION_HEADER structure.
#define ARM_ACPI_HEADER(Signature, Type, Revision) { \
@@ -119,4 +245,39 @@
ACPIProcessorUID, Flags, ClockDomain \
}
+// EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR
+#define EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT(Length, Flag, Parent, \
+ ACPIProcessorID, NumberOfPrivateResource) \
+ { \
+ EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, /* Type 0 */ \
+ Length, /* Length */ \
+ { \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ }, \
+ Flag, /* Processor flags */ \
+ Parent, /* Ref to parent node */ \
+ ACPIProcessorID, /* UID, as per MADT */ \
+ NumberOfPrivateResource /* Resource count */ \
+ }
+
+// EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE
+#define EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT(Flag, NextLevelCache, Size, \
+ NoOfSets, Associativity, Attributes, LineSize) \
+ { \
+ EFI_ACPI_6_3_PPTT_TYPE_CACHE, /* Type 1 */ \
+ sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), /* Length */ \
+ { \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ }, \
+ Flag, /* Cache flags */ \
+ NextLevelCache, /* Ref to next level */ \
+ Size, /* Size in bytes */ \
+ NoOfSets, /* Num of sets */ \
+ Associativity, /* Num of ways */ \
+ Attributes, /* Cache attributes */ \
+ LineSize /* Line size in bytes */ \
+ }
+
#endif /* __SGI_ACPI_HEADER__ */
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [edk2-devel] [edk2-platforms][PATCH V1 1/8] Platform/Sgi: Helper macros for PPTT Table
2021-04-02 9:12 ` [edk2-platforms][PATCH V1 1/8] Platform/Sgi: Helper macros for PPTT Table Pranav Madhu
@ 2021-04-13 9:18 ` PierreGondois
2021-04-20 5:57 ` Pranav Madhu
0 siblings, 1 reply; 14+ messages in thread
From: PierreGondois @ 2021-04-13 9:18 UTC (permalink / raw)
To: devel@edk2.groups.io, Pranav Madhu
Cc: Ard Biesheuvel, Leif Lindholm, Sami Mujawar
Hi Pranav,
> diff --git a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
> b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
> index 8d715de173c9..7ceb090a78e9 100644
> --- a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
> +++ b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
> @@ -1,6 +1,6 @@
> /** @file
> *
> -* Copyright (c) 2018-2020, ARM Limited. All rights reserved.
> +* Copyright (c) 2018-2021, ARM Limited. All rights reserved.
> *
> * SPDX-License-Identifier: BSD-2-Clause-Patent
> *
> @@ -20,6 +20,132 @@
> #define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('A','R','M',' ')
> #define EFI_ACPI_ARM_CREATOR_REVISION 0x00000099
>
> +#define CORE_COUNT FixedPcdGet32 (PcdCoreCount)
> +#define CLUSTER_COUNT FixedPcdGet32 (PcdClusterCount)
> +
> +#pragma pack(1)
> +// PPTT processor core structure
> +typedef struct {
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core;
> + UINT32 Offset[2];
I think there should be 3 entries (DCache, ICache, L2Cache). Updating
this will require updating the other PPTT tables written.
Would it be also possible to rename the field 'PrivateResources' as in
the spec ?
Another question: what does 'RD_' stands for ?
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE DCache;
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE ICache;
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache;
> +} RD_PPTT_CORE;
> +
> +// PPTT processor cluster structure
> +typedef struct {
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster;
> + UINT32 Offset;
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L3Cache;
> + RD_PPTT_CORE Core[CORE_COUNT];
> +} RD_PPTT_CLUSTER;
> +
> +// PPTT processor cluster structure without cache
> +typedef struct {
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster;
> + UINT32 Offset;
I think there is no need for an offset here. Updating this will require
updating the other PPTT tables written.
> + RD_PPTT_CORE Core[CORE_COUNT];
> +} RD_PPTT_MINIMAL_CLUSTER;
> +
> +// PPTT processor package structure
> +typedef struct {
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package;
> + UINT32 Offset;
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc;
> + RD_PPTT_MINIMAL_CLUSTER Cluster[CLUSTER_COUNT];
> +} RD_PPTT_SLC_PACKAGE;
> +#pragma pack ()
> +
> +//
> +// PPTT processor structure flags for different SoC components as
> defined in
> +// ACPI 6.3 specification
> +//
> +
[...]
>
> +// EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR
> +#define EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT(Length, Flag,
> Parent, \
> + ACPIProcessorID, NumberOfPrivateResource) \
I think it should be possible to remove the 'Length' parameter and
compute it as:
sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) +
NumberOfPrivateResource * sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE) +
NumberOfPrivateResource * sizeof (UINT32)
> + { \
> + EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, /* Type 0
> */ \
> + Length, /* Length
> */ \
> + { \
> + EFI_ACPI_RESERVED_BYTE, \
> + EFI_ACPI_RESERVED_BYTE, \
> + }, \
> + Flag, /* Processor
> flags */ \
> + Parent, /* Ref to
> parent node */ \
> + ACPIProcessorID, /* UID, as per
> MADT */ \
> + NumberOfPrivateResource /* Resource
> count */ \
> + }
> +
> +// EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE
> +#define EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT(Flag, NextLevelCache,
> Size, \
> + NoOfSets, Associativity, Attributes,
> LineSize) \
> + { \
> + EFI_ACPI_6_3_PPTT_TYPE_CACHE, /* Type 1
> */ \
> + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), /* Length
> */ \
> + { \
> + EFI_ACPI_RESERVED_BYTE, \
> + EFI_ACPI_RESERVED_BYTE, \
> + }, \
> + Flag, /* Cache flags
> */ \
> + NextLevelCache, /* Ref to next
> level */ \
> + Size, /* Size in
> bytes */ \
> + NoOfSets, /* Num of sets
> */ \
> + Associativity, /* Num of ways
> */ \
> + Attributes, /* Cache
> attributes */ \
> + LineSize /* Line size in
> bytes */ \
> + }
> +
> #endif /* __SGI_ACPI_HEADER__ */
> --
> 2.17.1
Regards,
Pierre
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [edk2-devel] [edk2-platforms][PATCH V1 1/8] Platform/Sgi: Helper macros for PPTT Table
2021-04-13 9:18 ` [edk2-devel] " PierreGondois
@ 2021-04-20 5:57 ` Pranav Madhu
2021-04-21 13:29 ` PierreGondois
0 siblings, 1 reply; 14+ messages in thread
From: Pranav Madhu @ 2021-04-20 5:57 UTC (permalink / raw)
To: Pierre Gondois, devel@edk2.groups.io
Cc: Ard Biesheuvel, Leif Lindholm, Sami Mujawar, nd
Hi Pierre,
Thanks for reviewing this patch. Please find my response inline.
> -----Original Message-----
> From: Pierre Gondois <pierre.gondois@arm.com>
> Sent: Tuesday, April 13, 2021 2:48 PM
> To: devel@edk2.groups.io; Pranav Madhu <Pranav.Madhu@arm.com>
> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>; Leif Lindholm
> <leif@nuviainc.com>; Sami Mujawar <Sami.Mujawar@arm.com>
> Subject: Re: [edk2-devel] [edk2-platforms][PATCH V1 1/8] Platform/Sgi:
> Helper macros for PPTT Table
>
> Hi Pranav,
>
> > diff --git a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
> > b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
> > index 8d715de173c9..7ceb090a78e9 100644
> > --- a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
> > +++ b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
> > @@ -1,6 +1,6 @@
> > �/** @file
> > �*
> > -*� Copyright (c) 2018-2020, ARM Limited. All rights reserved.
> > +*� Copyright (c) 2018-2021, ARM Limited. All rights reserved.
> > �*
> > �*� SPDX-License-Identifier: BSD-2-Clause-Patent
> > �*
> > @@ -20,6 +20,132 @@
> > �#define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('A','R','M',' ')
> > �#define EFI_ACPI_ARM_CREATOR_REVISION 0x00000099
> >
> > +#define CORE_COUNT����� FixedPcdGet32 (PcdCoreCount)
> > +#define CLUSTER_COUNT�� FixedPcdGet32 (PcdClusterCount)
> > +
> > +#pragma pack(1)
> > +// PPTT processor core structure
> > +typedef struct {
> > +� EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR� Core; �
> >
> +UINT32��������������������ï¿
> ½
> > +����������� Offset[2];
>
> I think there should be 3 entries (DCache, ICache, L2Cache). Updating this will
> require updating the other PPTT tables written.
As per ACPI spec 6.4, chapter '5.2.29.2 Cache Type Structure - Type 1', " Only
the head of the list needs to be listed as a resource by a processor node (and
counted toward Number of Private Resources), as the cache node itself
contains a link to the next level of cache."
Here L2 cache is represented as next level of L1, so no need to count it.
>
> Would it be also possible to rename the field 'PrivateResources' as in the
> spec ?
Yes, but in actual, it is not the private resource count.
> Another question: what does 'RD_' stands for ?
RD Stands for Reference Design, it is the convention we follow.
>
> > +� EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE����� DCache; �
> > +EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE����� ICache; �
> > +EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE����� L2Cache; }
> > +RD_PPTT_CORE;
> > +
> > +// PPTT processor cluster structure
> > +typedef struct {
> > +� EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR� Cluster; �
> >
> +UINT32��������������������ï¿
> ½
> > +����������� Offset; �
> > +EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE����� L3Cache; �
> > +RD_PPTT_CORE Core[CORE_COUNT]; } RD_PPTT_CLUSTER;
> > +
> > +// PPTT processor cluster structure without cache typedef struct {
> > +� EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR� Cluster; �
> >
> +UINT32��������������������ï¿
> ½
> > +����������� Offset;
> I think there is no need for an offset here. Updating this will require updating
> the other PPTT tables written.
Right. Will update.
> > +� RD_PPTT_CORE Core[CORE_COUNT];
> > +} RD_PPTT_MINIMAL_CLUSTER;
> > +
> > +// PPTT processor package structure
> > +typedef struct {
> > +� EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR� Package; �
> >
> +UINT32��������������������ï¿
> ½
> > +����������� Offset; �
> > +EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE����� Slc; �
> > +RD_PPTT_MINIMAL_CLUSTER Cluster[CLUSTER_COUNT]; }
> > +RD_PPTT_SLC_PACKAGE; #pragma pack ()
> > +
> > +//
> > +// PPTT processor structure flags for different SoC components as
> > defined in
> > +// ACPI 6.3 specification
> > +//
> > +
> [...]
> >
> > +// EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR
> > +#define EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT(Length, Flag,
> > Parent,������ \
> > +� ACPIProcessorID, NumberOfPrivateResource) \
>
> I think it should be possible to remove the 'Length' parameter and compute it
> as:
> sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) +
> NumberOfPrivateResource * sizeof
> (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE) + NumberOfPrivateResource *
> sizeof (UINT32)
>
As per 6.4 specification, table 5.138, the Length is "Length of the local processor
structure in bytes" It is just the length of local processor, not the entire structure.
> > + { \
> > +���
> >
> +EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR,����������ï¿
> ½ï¿½
> > +���� /* Type 0
> > */������������ \
> > +���
> >
> +Length,��������������������ï¿
> > +½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ /*
> > +Length
> > */������������ \
> > + { \
> > + EFI_ACPI_RESERVED_BYTE, \
> > + EFI_ACPI_RESERVED_BYTE, \
> > + }, \
> > +���
> > +Flag,���������������������ï
> >
> +¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½
> > +/* Processor
> > flags */��� \
> > +���
> >
> +Parent,��������������������ï¿
> > +½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ /*
> > +Ref to
> > parent node */ \
> > +���
> >
> +ACPIProcessorID,�����������������ï¿
> > +½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ /* UID, as per
> > MADT */�� \
> > +���
> >
> +NumberOfPrivateResource��������������ï¿
> ½ï
> > +¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ /* Resource
> > count */���� \
> > +� }
> > +
> > +// EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE
> > +#define EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT(Flag,
> NextLevelCache,
> > Size,���� \
> > +� NoOfSets, Associativity, Attributes,
> > LineSize)��������������������ï
> > ¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ \
> > + { \
> > +���
> >
> +EFI_ACPI_6_3_PPTT_TYPE_CACHE,������������ï
> ¿½ï
> > +¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ /* Type 1
> > */������������ \
> > +��� sizeof
> > +(EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE),������ /* Length
> > */������������ \
> > + { \
> > + EFI_ACPI_RESERVED_BYTE, \
> > + EFI_ACPI_RESERVED_BYTE, \
> > + }, \
> > +���
> > +Flag,���������������������ï
> >
> +¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½
> > +/* Cache flags
> > */������� \
> > +���
> >
> +NextLevelCache,�����������������ï¿
> ½
> > +���������������� /* Ref to next
> > level */� \
> > +���
> > +Size,���������������������ï
> >
> +¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½
> > +/* Size in
> > bytes */����� \
> > +���
> >
> +NoOfSets,�������������������ï¿
> ½
> > +�������������������� /* Num
> > +of sets
> > */������� \
> > +���
> > +Associativity,������������������ï
> > +¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ /* Num of ways
> > */������� \
> > +���
> > +Attributes,�������������������ï
> > +¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ /* Cache
> > attributes */�� \
> > +���
> >
> +LineSize��������������������ï
> > +¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ /*
> > +Line size in
> > bytes */ \
> > +� }
> > +
> > �#endif /* __SGI_ACPI_HEADER__ */
> > --
> > 2.17.1
>
> Regards,
>
> Pierre
>
Regards,
Pranav.
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [edk2-devel] [edk2-platforms][PATCH V1 1/8] Platform/Sgi: Helper macros for PPTT Table
2021-04-20 5:57 ` Pranav Madhu
@ 2021-04-21 13:29 ` PierreGondois
0 siblings, 0 replies; 14+ messages in thread
From: PierreGondois @ 2021-04-21 13:29 UTC (permalink / raw)
To: Pranav Madhu, devel@edk2.groups.io
Cc: Ard Biesheuvel, Leif Lindholm, Sami Mujawar, nd
Hi Pranav,
@@ -20,6 +20,132 @@
>>> �#define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('A','R','M',' ')
>>> �#define EFI_ACPI_ARM_CREATOR_REVISION 0x00000099
>>>
>>> +#define CORE_COUNT����� FixedPcdGet32 (PcdCoreCount)
>>> +#define CLUSTER_COUNT�� FixedPcdGet32 (PcdClusterCount)
>>> +
>>> +#pragma pack(1)
>>> +// PPTT processor core structure
>>> +typedef struct {
>>> +� EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR� Core; �
>>>
>> +UINT32��������������������ï¿
>> ½
>>> +����������� Offset[2];
>> I think there should be 3 entries (DCache, ICache, L2Cache). Updating this will
>> require updating the other PPTT tables written.
> As per ACPI spec 6.4, chapter '5.2.29.2 Cache Type Structure - Type 1', " Only
> the head of the list needs to be listed as a resource by a processor node (and
> counted toward Number of Private Resources), as the cache node itself
> contains a link to the next level of cache."
> Here L2 cache is represented as next level of L1, so no need to count it.
Yes indeed you are right.
>> Would it be also possible to rename the field 'PrivateResources' as in the
>> spec ?
> Yes, but in actual, it is not the private resource count.
This was nit picking, 'Offset' also works for me, and other PPTT tables
are calling this field as 'Offset'.
>
>> Another question: what does 'RD_' stands for ?
> RD Stands for Reference Design, it is the convention we follow.
>
>>> +� EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE����� DCache; �
>>> +EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE����� ICache; �
>>> +EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE����� L2Cache; }
>>> +RD_PPTT_CORE;
>>> +
>>> +// PPTT processor cluster structure
>>> +typedef struct {
>>> +� EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR� Cluster; �
>>>
>> +UINT32��������������������ï¿
>> ½
>>> +����������� Offset; �
>>> +EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE����� L3Cache; �
>>> +RD_PPTT_CORE Core[CORE_COUNT]; } RD_PPTT_CLUSTER;
>>> +
>>> +// PPTT processor cluster structure without cache typedef struct {
>>> +� EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR� Cluster; �
>>>
>> +UINT32��������������������ï¿
>> ½
>>> +����������� Offset;
>> I think there is no need for an offset here. Updating this will require updating
>> the other PPTT tables written.
> Right. Will update.
>
>>> +� RD_PPTT_CORE Core[CORE_COUNT];
>>> +} RD_PPTT_MINIMAL_CLUSTER;
>>> +
>>> +// PPTT processor package structure
>>> +typedef struct {
>>> +� EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR� Package; �
>>>
>> +UINT32��������������������ï¿
>> ½
>>> +����������� Offset; �
>>> +EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE����� Slc; �
>>> +RD_PPTT_MINIMAL_CLUSTER Cluster[CLUSTER_COUNT]; }
>>> +RD_PPTT_SLC_PACKAGE; #pragma pack ()
>>> +
>>> +//
>>> +// PPTT processor structure flags for different SoC components as
>>> defined in
>>> +// ACPI 6.3 specification
>>> +//
>>> +
>> [...]
>>> +// EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR
>>> +#define EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT(Length, Flag,
>>> Parent,������ \
>>> +� ACPIProcessorID, NumberOfPrivateResource) \
>> I think it should be possible to remove the 'Length' parameter and compute it
>> as:
>> sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) +
>> NumberOfPrivateResource * sizeof
>> (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE) + NumberOfPrivateResource *
>> sizeof (UINT32)
>>
> As per 6.4 specification, table 5.138, the Length is "Length of the local processor
> structure in bytes" It is just the length of local processor, not the entire structure.
Yes indeed you are right.
Thanks for the answer,
Pierre
^ permalink raw reply [flat|nested] 14+ messages in thread
* [edk2-platforms][PATCH V1 2/8] Platform/Sgi: ACPI PPTT table for SGI-575 platform
2021-04-02 9:12 [edk2-platforms][PATCH V1 0/8] Platform/Sgi: Add PPTT table for SGI/RD platforms Pranav Madhu
2021-04-02 9:12 ` [edk2-platforms][PATCH V1 1/8] Platform/Sgi: Helper macros for PPTT Table Pranav Madhu
@ 2021-04-02 9:12 ` Pranav Madhu
2021-04-02 9:12 ` [edk2-platforms][PATCH V1 3/8] Platform/Sgi: ACPI PPTT table for RD-N1-Edge platform Pranav Madhu
` (5 subsequent siblings)
7 siblings, 0 replies; 14+ messages in thread
From: Pranav Madhu @ 2021-04-02 9:12 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Leif Lindholm, Sami Mujawar
From: Pranav Madhu <Pranav.Madhu@arm.com>
The SGI-575 platform includes two clusters with four single-thread CPUs.
Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache
and 512KB L2 cache. Each cluster includes a 2MB L3 cache. Add PPTT table
for SGI-575 platform with this information.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
.../SgiPkg/AcpiTables/Sgi575AcpiTables.inf | 3 +-
.../ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc | 161 ++++++++++++++++++
2 files changed, 163 insertions(+), 1 deletion(-)
create mode 100644 Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc
diff --git a/Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf
index 2121fd39f2f0..b1ee16e98ea3 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf
@@ -1,7 +1,7 @@
## @file
# ACPI table data and ASL sources required to boot the platform.
#
-# Copyright (c) 2018, ARM Ltd. All rights reserved.
+# Copyright (c) 2018 - 2021, ARM Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -22,6 +22,7 @@
Mcfg.aslc
Sgi575/Dsdt.asl
Sgi575/Madt.aslc
+ Sgi575/Pptt.aslc
Spcr.aslc
Ssdt.asl
diff --git a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc
new file mode 100644
index 000000000000..043482ee3b9a
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc
@@ -0,0 +1,161 @@
+/** @file
+* Processor Properties Topology Table (PPTT) for SGI-575 platform
+*
+* This file describes the topological structure of the processor block on the
+* SGI-575 platform in the form as defined by ACPI PPTT table. The SGI-575
+* platform includes two clusters with four single-thread CPUS. Each of the CPUs
+* include 64KB L1 Data cache, 64KB L1 Instruction cache and 512KB L2 cache.
+* Each cluster includes a 2MB L3 cache.
+*
+* Copyright (c) 2021, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+
+#define PPTT_CORE_INIT(pid, cid, coreId) \
+ { \
+ /* Parameters for CPU Core */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ __builtin_offsetof (RD_PPTT_CORE, DCache), /* Length */ \
+ PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid]), /* Parent */ \
+ ((pid << 3) | (cid << 2) | coreId), /* ACPI Id */ \
+ 2 /* Num of private resource */\
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ { \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[coreId].DCache), \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[coreId].ICache) \
+ }, \
+ \
+ /* L1 Data Cache Parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[coreId].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_64KB, /* Size */ \
+ 64, /* Num of sets */ \
+ 16, /* Associativity */ \
+ PPTT_DATA_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L1 Instruction Cache Parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[coreId].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_64KB, /* Size */ \
+ 256, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_INST_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L2 Cache Parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_512KB, /* Size */ \
+ 1024, /* Num of sets */ \
+ 8, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ }
+
+#define PPTT_CLUSTER_INIT(pid, cid) \
+ { \
+ /* Parameters for Cluster */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ __builtin_offsetof (RD_PPTT_CLUSTER, L3Cache), \
+ /* Length */ \
+ PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package), /* Parent */ \
+ 0, /* ACPI Id */ \
+ 1 /* Num of private resource */ \
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].L3Cache), \
+ \
+ /* L3 Cache Parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_2MB, /* Size */ \
+ 2048, /* Num of sets */ \
+ 16, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* Initialize child cores */ \
+ { \
+ PPTT_CORE_INIT (pid, cid, 0), \
+ PPTT_CORE_INIT (pid, cid, 1), \
+ PPTT_CORE_INIT (pid, cid, 2), \
+ PPTT_CORE_INIT (pid, cid, 3) \
+ } \
+ }
+
+#pragma pack(1)
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package;
+ RD_PPTT_CLUSTER Cluster[CLUSTER_COUNT];
+} SGI575_PPTT_PACKAGE;
+
+/*
+ * Processor Properties Topology Table
+ */
+typedef struct {
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ SGI575_PPTT_PACKAGE Package;
+} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+#pragma pack ()
+
+STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ )
+ },
+
+ {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (
+ __builtin_offsetof (SGI575_PPTT_PACKAGE, Cluster[0]),
+ PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 0
+ ),
+ {
+ PPTT_CLUSTER_INIT (0, 0),
+ PPTT_CLUSTER_INIT (0, 1)
+ }
+ }
+};
+
+/*
+ * Reference the table being generated to prevent the optimizer from removing
+ * the data structure from the executable
+ */
+VOID* CONST ReferenceAcpiTable = &Pptt;
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [edk2-platforms][PATCH V1 3/8] Platform/Sgi: ACPI PPTT table for RD-N1-Edge platform
2021-04-02 9:12 [edk2-platforms][PATCH V1 0/8] Platform/Sgi: Add PPTT table for SGI/RD platforms Pranav Madhu
2021-04-02 9:12 ` [edk2-platforms][PATCH V1 1/8] Platform/Sgi: Helper macros for PPTT Table Pranav Madhu
2021-04-02 9:12 ` [edk2-platforms][PATCH V1 2/8] Platform/Sgi: ACPI PPTT table for SGI-575 platform Pranav Madhu
@ 2021-04-02 9:12 ` Pranav Madhu
2021-04-02 9:12 ` [edk2-platforms][PATCH V1 4/8] Platform/Sgi: ACPI PPTT table for RD-N1-Edge dual-chip Pranav Madhu
` (4 subsequent siblings)
7 siblings, 0 replies; 14+ messages in thread
From: Pranav Madhu @ 2021-04-02 9:12 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Leif Lindholm, Sami Mujawar
The RD-N1-Edge platform includes two clusters with four single-thread
CPUS. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction
cache and 512KB L2 cache. Each cluster includes a 2MB L3 cache. The
platform also includes a system level cache of 8MB. Add PPTT table for
RD-N1-Edge platform with this information.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
.../SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf | 3 +-
.../ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc | 173 ++++++++++++++++++
2 files changed, 175 insertions(+), 1 deletion(-)
create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
index 22e33239070b..eecb64186473 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
@@ -1,7 +1,7 @@
## @file
# ACPI table data and ASL sources required to boot the platform.
#
-# Copyright (c) 2018-2020, ARM Ltd. All rights reserved.
+# Copyright (c) 2018-2021, ARM Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -23,6 +23,7 @@
Mcfg.aslc
RdN1Edge/Dsdt.asl
RdN1Edge/Madt.aslc
+ RdN1Edge/Pptt.aslc
Spcr.aslc
Ssdt.asl
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc
new file mode 100644
index 000000000000..e5bc7305444d
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc
@@ -0,0 +1,173 @@
+/** @file
+* Processor Properties Topology Table (PPTT) for RD-N1-Edge single-chip platform
+*
+* This file describes the topological structure of the processor block on the
+* RD-N1-Edge single-chip platform in the form as defined by ACPI PPTT table. The
+* RD-N1-Edge platform includes two clusters with four single-thread CPUS. Each
+* of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 512KB L2
+* cache. Each cluster includes a 2MB L3 cache. The platform also includes a
+* system level cache of 8MB.
+*
+* Copyright (c) 2021, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+
+#define PPTT_CORE_INIT(pid, cid, coreId) \
+ { \
+ /* Parameters for CPU Core */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ __builtin_offsetof (RD_PPTT_CORE, DCache), /* Length */ \
+ PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid]), /* Parent */ \
+ ((pid << 3) | (cid << 2) | coreId), /* ACPI Id */ \
+ 2 /* Num of private resource */\
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ { \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[coreId].DCache), \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[coreId].ICache) \
+ }, \
+ \
+ /* L1 Data Cache Parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[coreId].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_64KB, /* Size */ \
+ 256, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_DATA_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L1 Instruction Cache Parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[coreId].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_64KB, /* Size */ \
+ 256, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_INST_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L2 Cache Parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_512KB, /* Size */ \
+ 1024, /* Num of sets */ \
+ 8, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ }
+
+#define PPTT_CLUSTER_INIT(pid, cid) \
+ { \
+ /* Parameters for Cluster */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ __builtin_offsetof (RD_PPTT_CLUSTER, L3Cache), /* Length */ \
+ PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package), /* Parent */ \
+ 0, /* ACPI Id */ \
+ 1 /* Num of private resource */ \
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].L3Cache), \
+ \
+ /* L3 Cache Parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_2MB, /* Size */ \
+ 2048, /* Num of sets */ \
+ 16, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ { \
+ PPTT_CORE_INIT (pid, cid, 0), \
+ PPTT_CORE_INIT (pid, cid, 1), \
+ PPTT_CORE_INIT (pid, cid, 2), \
+ PPTT_CORE_INIT (pid, cid, 3) \
+ } \
+ }
+
+#pragma pack(1)
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package;
+ UINT32 Offset;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc;
+ RD_PPTT_CLUSTER Cluster[CLUSTER_COUNT];
+} RDN1EDGE_PPTT_PACKAGE ;
+
+/*
+ * Processor Properties Topology Table
+ */
+typedef struct {
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ RDN1EDGE_PPTT_PACKAGE Package;
+} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+#pragma pack ()
+
+STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ )
+ },
+
+ {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (
+ __builtin_offsetof (RDN1EDGE_PPTT_PACKAGE , Slc),
+ PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 1),
+
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ Package.Slc),
+
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT (
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */
+ 0, /* Next level of cache */
+ SIZE_8MB, /* Size */
+ 8192, /* Num of sets */
+ 16, /* Associativity */
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */
+ 64 /* Line size */
+ ),
+ {
+ PPTT_CLUSTER_INIT (0, 0),
+ PPTT_CLUSTER_INIT (0, 1),
+ }
+ }
+};
+
+/*
+ * Reference the table being generated to prevent the optimizer from removing
+ * the data structure from the executable
+ */
+VOID* CONST ReferenceAcpiTable = &Pptt;
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [edk2-platforms][PATCH V1 4/8] Platform/Sgi: ACPI PPTT table for RD-N1-Edge dual-chip
2021-04-02 9:12 [edk2-platforms][PATCH V1 0/8] Platform/Sgi: Add PPTT table for SGI/RD platforms Pranav Madhu
` (2 preceding siblings ...)
2021-04-02 9:12 ` [edk2-platforms][PATCH V1 3/8] Platform/Sgi: ACPI PPTT table for RD-N1-Edge platform Pranav Madhu
@ 2021-04-02 9:12 ` Pranav Madhu
2021-04-02 9:12 ` [edk2-platforms][PATCH V1 5/8] Platform/Sgi: ACPI PPTT table for RD-E1-Edge platform Pranav Madhu
` (3 subsequent siblings)
7 siblings, 0 replies; 14+ messages in thread
From: Pranav Madhu @ 2021-04-02 9:12 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Leif Lindholm, Sami Mujawar
The RD-N1-Edge dual-chip platform includes two RD-N1-Edge single-chip
platforms connected over cache coherent interconnect. Each of the
RD-N1-Edge single-chip platform includes two clusters with four
single-thread CPUs. Each of the CPUs include 64KB L1 Data cache, 64KB
L1 Instruction cache and 512KB L2 cache. Each cluster includes a 2MB
L3 cache. The platform also includes a system level cache of 8MB per
chip. Add PPTT table for RD-N1-Edge dual-chip platform with this
information.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
.../AcpiTables/RdN1EdgeX2AcpiTables.inf | 3 +-
.../SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc | 191 ++++++++++++++++++
2 files changed, 193 insertions(+), 1 deletion(-)
create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
index ba400de0454b..ebb77979606e 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
@@ -1,7 +1,7 @@
## @file
# ACPI table data and ASL sources required to boot the platform.
#
-# Copyright (c) 2020, ARM Ltd. All rights reserved.
+# Copyright (c) 2021, ARM Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -23,6 +23,7 @@
Mcfg.aslc
RdN1Edge/Dsdt.asl
RdN1EdgeX2/Madt.aslc
+ RdN1EdgeX2/Pptt.aslc
RdN1EdgeX2/Srat.aslc
Spcr.aslc
Ssdt.asl
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc
new file mode 100644
index 000000000000..3cdcd7714c1f
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc
@@ -0,0 +1,191 @@
+/** @file
+* Processor Properties Topology Table (PPTT) for RD-N1-Edge dual-chip platform
+*
+* This file describes the topological structure of the processor block on the
+* RD-N1-Edge dual-chip platform in the form as defined by ACPI PPTT table. The
+* RD-N1-Edge dual-chip platform includes two RD-N1-Edge single-chip platforms
+* connected over cache coherent interconnect. Each of the RD-N1-Edge single-chip
+* platform includes two clusters with four single-thread CPUS. Each of the CPUs
+* include 64KB L1 Data cache, 64KB L1 Instruction cache and 512KB L2 cache. Each
+* cluster includes a 2MB L3 cache. Each instance of the chip includes a system
+* level cache of 8MB.
+*
+* Copyright (c) 2021, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+
+#define CHIP_COUNT FixedPcdGet32 (PcdChipCount)
+
+#define PPTT_CORE_INIT(pid, cid, coreId) \
+ { \
+ /* Parameters for CPU Core */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ __builtin_offsetof (RD_PPTT_CORE, DCache), /* Length */ \
+ PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[pid].Cluster[cid]), /* Parent */ \
+ ((pid << 3) | (cid << 2) | coreId), /* ACPI Id */ \
+ 2 /* Num of private resource */\
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ { \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[pid].Cluster[cid].Core[coreId].DCache), \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[pid].Cluster[cid].Core[coreId].ICache) \
+ }, \
+ \
+ /* L1 Data Cache Parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[pid].Cluster[cid].Core[coreId].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_64KB, /* Size */ \
+ 256, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_DATA_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L1 Instruction Cache Parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[pid].Cluster[cid].Core[coreId].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_64KB, /* Size */ \
+ 256, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_INST_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L2 Cache Parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_512KB, /* Size */ \
+ 1024, /* Num of sets */ \
+ 8, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ }
+
+#define PPTT_CLUSTER_INIT(pid, cid) \
+ { \
+ /* Parameters for Cluster */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ __builtin_offsetof (RD_PPTT_CLUSTER, L3Cache), /* Length */ \
+ PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[pid]), /* Parent */ \
+ 0, /* ACPI Id */ \
+ 1 /* Num of private resource */ \
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[pid].Cluster[cid].L3Cache), \
+ \
+ /* L3 Cache Parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_2MB, /* Size */ \
+ 2048, /* Num of sets */ \
+ 16, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ { \
+ PPTT_CORE_INIT (pid, cid, 0), \
+ PPTT_CORE_INIT (pid, cid, 1), \
+ PPTT_CORE_INIT (pid, cid, 2), \
+ PPTT_CORE_INIT (pid, cid, 3) \
+ } \
+ }
+
+#define PPTT_PACKAGE_INIT(pid) \
+ { \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ __builtin_offsetof (RDN1EDGEX2_PPTT_PACKAGE , Slc), /* Length */ \
+ PPTT_PROCESSOR_PACKAGE_FLAGS, /* Flag */ \
+ 0, /* Parent */ \
+ 0, /* ACPI Id */ \
+ 1 /* Num of private resource */ \
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[pid].Slc), \
+ \
+ /* SLC Parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_8MB, /* Size */ \
+ 8192, /* Num of sets */ \
+ 16, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ { \
+ PPTT_CLUSTER_INIT (pid, 0), \
+ PPTT_CLUSTER_INIT (pid, 1), \
+ } \
+ }
+
+#pragma pack(1)
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package;
+ UINT32 Offset;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc;
+ RD_PPTT_CLUSTER Cluster[CLUSTER_COUNT];
+} RDN1EDGEX2_PPTT_PACKAGE;
+
+/*
+ * Processor Properties Topology Table
+ */
+typedef struct {
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ RDN1EDGEX2_PPTT_PACKAGE Package[CHIP_COUNT];
+} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+#pragma pack ()
+
+STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ )
+ },
+
+ {
+ PPTT_PACKAGE_INIT (0),
+ PPTT_PACKAGE_INIT (1)
+ }
+};
+
+/*
+ * Reference the table being generated to prevent the optimizer from removing
+ * the data structure from the executable
+ */
+VOID* CONST ReferenceAcpiTable = &Pptt;
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [edk2-platforms][PATCH V1 5/8] Platform/Sgi: ACPI PPTT table for RD-E1-Edge platform
2021-04-02 9:12 [edk2-platforms][PATCH V1 0/8] Platform/Sgi: Add PPTT table for SGI/RD platforms Pranav Madhu
` (3 preceding siblings ...)
2021-04-02 9:12 ` [edk2-platforms][PATCH V1 4/8] Platform/Sgi: ACPI PPTT table for RD-N1-Edge dual-chip Pranav Madhu
@ 2021-04-02 9:12 ` Pranav Madhu
2021-04-13 9:34 ` [edk2-devel] " PierreGondois
2021-04-02 9:12 ` [edk2-platforms][PATCH V1 6/8] Platform/Sgi: ACPI PPTT Table for RD-V1 platform Pranav Madhu
` (2 subsequent siblings)
7 siblings, 1 reply; 14+ messages in thread
From: Pranav Madhu @ 2021-04-02 9:12 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Leif Lindholm, Sami Mujawar
The RD-E1-Edge platform includes two clusters with eight multi-thread
CPUs. Each of the CPUs include 32KB L1 Data cache, 32KB L1 Instruction
cache and 256KB L2 cache. Each cluster includes a 2MB L3 cache. The
platform also includes a system level cache of 8MB. Add PPTT table for
RD-E1-Edge platform with this information.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
.../SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf | 3 +-
.../ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc | 230 ++++++++++++++++++
2 files changed, 232 insertions(+), 1 deletion(-)
create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
index 2dd2275665a2..04ef2bfcaa26 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
@@ -1,7 +1,7 @@
## @file
# ACPI table data and ASL sources required to boot the platform.
#
-# Copyright (c) 2018-2020, ARM Ltd. All rights reserved.
+# Copyright (c) 2018-2021, ARM Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -23,6 +23,7 @@
Mcfg.aslc
RdE1Edge/Dsdt.asl
RdE1Edge/Madt.aslc
+ RdE1Edge/Pptt.aslc
Spcr.aslc
Ssdt.asl
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc
new file mode 100644
index 000000000000..da0fa3e3f628
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc
@@ -0,0 +1,230 @@
+/** @file
+* Processor Properties Topology Table (PPTT) for RD-E1-Edge platform
+*
+* This file describes the topological structure of the processor block on the
+* RD-E1-Edge platform in the form as defined by ACPI PPTT table. The RD-E1-Edge
+* platform includes two clusters with eight dual-thread CPUS. Each of the CPUs
+* include 32KB L1 Data cache, 32KB L1 Instruction cache and 256KB L2 cache.
+* Each cluster includes a 2MB L3 cache. The platform also includes a system
+* level cache of 8MB.
+*
+* Copyright (c) 2021, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+
+#define THREAD_PER_CORE 2
+
+#define PPTT_THREAD_INIT(pid, cid, coreId, tid) \
+ { \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ sizeof (RDE1EDGE_PPTT_THREAD), /* Length */ \
+ PPTT_PROCESSOR_THREAD_FLAGS, /* Flag */ \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[coreId]), /* Parent */ \
+ ((pid << 5) | (cid << 4) | (coreId << 1) | tid), \
+ /* ACPI Id */ \
+ 0 /* Num of private resource */ \
+ ) \
+ }
+
+#define PPTT_CORE_INIT(pid, cid, coreId) \
+ { \
+ /* Parameters for CPU Core */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ __builtin_offsetof (RDE1EDGE_PPTT_CORE, DCache), /* Length */ \
+ PPTT_PROCESSOR_CORE_THREADED_FLAGS, /* Flag */ \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid]), /* Parent */ \
+ 0, /* ACPI Id */ \
+ 2 /* Num of private resource */\
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ { \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[coreId].DCache), \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[coreId].ICache) \
+ }, \
+ \
+ /* L1 Data cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[coreId].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_32KB, /* Size */ \
+ 128, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_DATA_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L1 Instruction cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[coreId].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_32KB, /* Size */ \
+ 128, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_INST_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L2 cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_256KB, /* Size */ \
+ 1024, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* Thread Initialization */ \
+ { \
+ PPTT_THREAD_INIT (pid, cid, coreId, 0), \
+ PPTT_THREAD_INIT (pid, cid, coreId, 1) \
+ } \
+ }
+
+#define PPTT_CLUSTER_INIT(pid, cid) \
+ { \
+ /* Parameters for Cluster */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ __builtin_offsetof (RDE1EDGE_PPTT_CLUSTER, L3Cache), /* Length */ \
+ PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package), /* Parent */ \
+ 0, /* ACPI Id */ \
+ 1 /* Num of private resource */ \
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].L3Cache), \
+ \
+ /* L3 cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_2MB, /* Size */ \
+ 2048, /* Num of sets */ \
+ 16, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* Core Initialization */ \
+ { \
+ PPTT_CORE_INIT (pid, cid, 0), \
+ PPTT_CORE_INIT (pid, cid, 1), \
+ PPTT_CORE_INIT (pid, cid, 2), \
+ PPTT_CORE_INIT (pid, cid, 3), \
+ PPTT_CORE_INIT (pid, cid, 4), \
+ PPTT_CORE_INIT (pid, cid, 5), \
+ PPTT_CORE_INIT (pid, cid, 6), \
+ PPTT_CORE_INIT (pid, cid, 7) \
+ } \
+ }
+
+#define PPTT_PACKAGE_INIT(pid) \
+ { \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ __builtin_offsetof (RDE1EDGE_PPTT_PACKAGE, Slc), \
+ PPTT_PROCESSOR_PACKAGE_FLAGS, \
+ 0, \
+ 0, \
+ 1 \
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Slc), \
+ \
+ /* SLC parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_8MB, /* Size */ \
+ 8192, /* Num of sets */ \
+ 16, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ { \
+ PPTT_CLUSTER_INIT (pid, 0), \
+ PPTT_CLUSTER_INIT (pid, 1), \
+ } \
+ }
+
+#pragma pack(1)
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Thread;
+} RDE1EDGE_PPTT_THREAD;
+
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core;
+ UINT32 Offset[2];
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE DCache;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE ICache;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache;
+ RDE1EDGE_PPTT_THREAD Thread[THREAD_PER_CORE];
+} RDE1EDGE_PPTT_CORE;
+
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster;
+ UINT32 Offset;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L3Cache;
+ RDE1EDGE_PPTT_CORE Core[CORE_COUNT / THREAD_PER_CORE];
+} RDE1EDGE_PPTT_CLUSTER;
+
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package;
+ UINT32 Offset;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc;
+ RDE1EDGE_PPTT_CLUSTER Cluster[CLUSTER_COUNT];
+} RDE1EDGE_PPTT_PACKAGE;
+
+/*
+ * Processor Properties Topology Table
+ */
+typedef struct {
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ RDE1EDGE_PPTT_PACKAGE Package;
+} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+#pragma pack ()
+
+STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ )
+ },
+
+ PPTT_PACKAGE_INIT (0)
+};
+
+/*
+ * Reference the table being generated to prevent the optimizer from removing
+ * the data structure from the executable
+ */
+VOID* CONST ReferenceAcpiTable = &Pptt;
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [edk2-devel] [edk2-platforms][PATCH V1 5/8] Platform/Sgi: ACPI PPTT table for RD-E1-Edge platform
2021-04-02 9:12 ` [edk2-platforms][PATCH V1 5/8] Platform/Sgi: ACPI PPTT table for RD-E1-Edge platform Pranav Madhu
@ 2021-04-13 9:34 ` PierreGondois
2021-04-20 6:02 ` Pranav Madhu
0 siblings, 1 reply; 14+ messages in thread
From: PierreGondois @ 2021-04-13 9:34 UTC (permalink / raw)
To: devel@edk2.groups.io, Pranav Madhu
Cc: Ard Biesheuvel, Leif Lindholm, Sami Mujawar
Hi Pranav,
> + }
> +
> +#define PPTT_CORE_INIT(pid, cid,
> coreId) \
> + { \
> + /* Parameters for CPU Core
> */ \
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT
> ( \
> + __builtin_offsetof (RDE1EDGE_PPTT_CORE, DCache), /* Length
> */ \
> + PPTT_PROCESSOR_CORE_THREADED_FLAGS, /* Flag
> */ \
> + __builtin_offsetof
> (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
> + Package.Cluster[cid]), /* Parent
> */ \
> + 0, /* ACPI Id
> */ \
> + 2 /* Num of private
> resource */\
> + ), \
> + \
> + /* Offsets of the private resources
> */ \
> + { \
> + __builtin_offsetof
> (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
> + Package.Cluster[cid].Core[coreId].DCache), \
> + __builtin_offsetof
> (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
> + Package.Cluster[cid].Core[coreId].ICache) \
> + }, \
Would it be possible to use the edk2/MdePkg/Include/Base.h:OFFSET_OF()
macro to handle the different compilers ?
This modification could be applied to all the other PPTT tables in the set.
> + \
> + /* L1 Data cache parameters
> */ \
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT
> ( \
> + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag
> */ \
> + __builtin_offsetof
> (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
> + Package.Cluster[cid].Core[coreId].L2Cache), \
> + /* Next level of cache
> */ \
> + SIZE_32KB, /* Size
> */ \
> + 128, /* Num of sets
> */ \
> + 4, /* Associativity
> */ \
> + PPTT_DATA_CACHE_ATTR, /* Attributes
> */ \
> + 64 /* Line size
> */ \
> + ), \
> + \
[...]
> +
> +#pragma pack(1)
> +typedef struct {
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Thread;
> +} RDE1EDGE_PPTT_THREAD;
> +
> +typedef struct {
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core;
> + UINT32 Offset[2];
Similarly to the the first patch, I think there should be 3 elements
(and if possible renamed to 'PrivateResources').
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE DCache;
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE ICache;
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache;
> + RDE1EDGE_PPTT_THREAD Thread[THREAD_PER_CORE];
> +} RDE1EDGE_PPTT_CORE;
> +
> +typedef struct {
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster;
> + UINT32 Offset;
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L3Cache;
> + RDE1EDGE_PPTT_CORE Core[CORE_COUNT /
> THREAD_PER_CORE];
> +} RDE1EDGE_PPTT_CLUSTER;
> +
Regards,
Pierre
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [edk2-devel] [edk2-platforms][PATCH V1 5/8] Platform/Sgi: ACPI PPTT table for RD-E1-Edge platform
2021-04-13 9:34 ` [edk2-devel] " PierreGondois
@ 2021-04-20 6:02 ` Pranav Madhu
0 siblings, 0 replies; 14+ messages in thread
From: Pranav Madhu @ 2021-04-20 6:02 UTC (permalink / raw)
To: Pierre Gondois, devel@edk2.groups.io
Cc: Ard Biesheuvel, Leif Lindholm, Sami Mujawar, nd
Hi Pierre,
Thanks for reviewing this patch.
>
> Hi Pranav,
> > +� }
> > +
> > +#define PPTT_CORE_INIT(pid, cid,
> >
> coreId)���������������������
> > ����������������� \
> > + { \
> > +��� /* Parameters for CPU Core
> >
> */����������������������ï¿
> > ½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ \
> > +��� EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT
> >
> (�����������������������
> > ������� \
> > +����� __builtin_offsetof (RDE1EDGE_PPTT_CORE, DCache), /*
> > +Length
> > */���������� \
> > +�����
> > +PPTT_PROCESSOR_CORE_THREADED_FLAGS,��������
> /* Flag
> > */������������������ \
> > +����� __builtin_offsetof
> > (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,��� \
> > +�������
> > +Package.Cluster[cid]),���������������ï¿
> > +½ï¿½ï¿½ï¿½ /* Parent
> > */���������������� \
> > +�����
> >
> +0,����������������������ï
> > +¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ /* ACPI Id
> > */��������������� \
> > +�����
> >
> +2����������������������ï¿
> > +½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ /* Num
> of
> > +private
> > resource */\
> > + ), \
> > + \
> > +��� /* Offsets of the private resources
> >
> */����������������������ï¿
> > ½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ \
> > + { \
> > +����� __builtin_offsetof
> > (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,��� \
> > + Package.Cluster[cid].Core[coreId].DCache), \ �����
> > +__builtin_offsetof
> > (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,��� \
> > + Package.Cluster[cid].Core[coreId].ICache) \ }, \
>
> Would it be possible to use the edk2/MdePkg/Include/Base.h:OFFSET_OF()
> macro to handle the different compilers ?
Yes, will update
>
> This modification could be applied to all the other PPTT tables in the set.
>
> > + \
> > +��� /* L1 Data cache parameters
> >
> */����������������������ï¿
> > ½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ \
> > +��� EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT
> >
> (�����������������������
> > ����������� \
> > +�����
> > +PPTT_CACHE_STRUCTURE_FLAGS,���������� /*
> Flag
> >
> */����������������������ï¿
> > ½ï¿½ \
> > +����� __builtin_offsetof
> > (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,��� \
> > + Package.Cluster[cid].Core[coreId].L2Cache), \
> >
> +�����������������������
> > +�������������������� /* Next
> > +level of cache
> > */��������� \
> > +�����
> >
> +SIZE_32KB,�������������������ï¿
> > +½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ /* Size
> >
> */����������������������ï¿
> > ½ï¿½ \
> > +�����
> >
> +128,���������������������ï¿
> > +½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ /* Num of sets
> > */����������������� \
> > +�����
> >
> +4,����������������������ï
> > +¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ /* Associativity
> > */��������������� \
> > +�����
> >
> +PPTT_DATA_CACHE_ATTR,��������������ï¿
> ½ï¿½
> > +/* Attributes
> > */������������������ \
> > +�����
> >
> +64����������������������ï
> > +¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ /* Line size
> > */������������������� \
> > + ), \
> > + \
> [...]
> > +
> > +#pragma pack(1)
> > +typedef struct {
> > +� EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Thread; }
> > +RDE1EDGE_PPTT_THREAD;
> > +
> > +typedef struct {
> > +� EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR� Core; �
> >
> +UINT32��������������������ï¿
> ½
> > +����������� Offset[2];
> Similarly to the the first patch, I think there should be 3 elements (and if
> possible renamed to 'PrivateResources').
> > +� EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE����� DCache; �
> > +EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE����� ICache; �
> > +EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE����� L2Cache; �
> > +RDE1EDGE_PPTT_THREAD Thread[THREAD_PER_CORE]; }
> RDE1EDGE_PPTT_CORE;
> > +
> > +typedef struct {
> > +� EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR� Cluster; �
> >
> +UINT32��������������������ï¿
> ½
> > +����������� Offset; �
> > +EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE����� L3Cache; �
> >
> +RDE1EDGE_PPTT_CORE���������������ï¿
> ½ï¿½
> > +��� Core[CORE_COUNT /
> > THREAD_PER_CORE];
> > +} RDE1EDGE_PPTT_CLUSTER;
> > +
>
> Regards,
>
> Pierre
Regards,
Pranav
^ permalink raw reply [flat|nested] 14+ messages in thread
* [edk2-platforms][PATCH V1 6/8] Platform/Sgi: ACPI PPTT Table for RD-V1 platform
2021-04-02 9:12 [edk2-platforms][PATCH V1 0/8] Platform/Sgi: Add PPTT table for SGI/RD platforms Pranav Madhu
` (4 preceding siblings ...)
2021-04-02 9:12 ` [edk2-platforms][PATCH V1 5/8] Platform/Sgi: ACPI PPTT table for RD-E1-Edge platform Pranav Madhu
@ 2021-04-02 9:12 ` Pranav Madhu
2021-04-02 9:12 ` [edk2-platforms][PATCH V1 7/8] Platform/Sgi: ACPI PPTT Table for RD-V1 quad-chip platform Pranav Madhu
2021-04-02 9:12 ` [edk2-platforms][PATCH V1 8/8] Platform/Sgi: ACPI PPTT table for RD-N2 platform Pranav Madhu
7 siblings, 0 replies; 14+ messages in thread
From: Pranav Madhu @ 2021-04-02 9:12 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Leif Lindholm, Sami Mujawar
The RD-V1 platform includes sixteen single-thread CPUs. Each of the
CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB
L2 cache. The platform also includes a system level cache of 16MB.
Add PPTT table for RD-V1 platform with this information.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
.../ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf | 3 +-
Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc | 168 ++++++++++++++++++
2 files changed, 170 insertions(+), 1 deletion(-)
create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf
index a21dcfafef1a..a3e558cf1535 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf
@@ -1,7 +1,7 @@
## @file
# ACPI table data and ASL sources required to boot the platform.
#
-# Copyright (c) 2020, Arm Ltd. All rights reserved.
+# Copyright (c) 2020-2021, Arm Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -23,6 +23,7 @@
Mcfg.aslc
RdV1/Dsdt.asl
RdV1/Madt.aslc
+ RdV1/Pptt.aslc
Spcr.aslc
Ssdt.asl
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc
new file mode 100644
index 000000000000..8d95d834af4d
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc
@@ -0,0 +1,168 @@
+/** @file
+* Processor Properties Topology Table (PPTT) for RD-V1 single-chip platform
+*
+* This file describes the topological structure of the processor block on the
+* RD-V1 single-chip platform in the form as defined by ACPI PPTT table. The
+* RD-V1 single-chip platform includes sixteen single-thread CPUS. Each of the
+* CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB L2 cache.
+* The platform also includes a system level cache of 16MB.
+*
+* Copyright (c) 2021, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+
+#define PPTT_CORE_INIT(pid, cid, coreId) \
+ { \
+ /* Parameters for CPU Core */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ __builtin_offsetof (RD_PPTT_CORE, DCache), /* Length */ \
+ PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid]), /* Parent */ \
+ ((pid << 4) | cid), /* ACPI Id */ \
+ 2 /* Num of private resource */\
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ { \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[coreId].DCache), \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[coreId].ICache) \
+ }, \
+ \
+ /* L1 Data cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[coreId].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_64KB, /* Size */ \
+ 256, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_DATA_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L1 Instruction cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[coreId].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_64KB, /* Size */ \
+ 256, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_INST_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L2 cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_1MB, /* Size */ \
+ 2048, /* Num of sets */ \
+ 8, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ }
+
+#define PPTT_CLUSTER_INIT(pid, cid) \
+ { \
+ /* Parameters for Cluster */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ __builtin_offsetof (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ \
+ PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package), /* Parent */ \
+ 0, /* ACPI Id */ \
+ 0 /* Num of private resource */ \
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core), \
+ \
+ /* Core initilization */ \
+ { \
+ PPTT_CORE_INIT (pid, cid, 0) \
+ } \
+ }
+
+#pragma pack(1)
+/*
+ * Processor Properties Topology Table
+ */
+typedef struct {
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ RD_PPTT_SLC_PACKAGE Package;
+} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+#pragma pack ()
+
+STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ )
+ },
+
+ {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (
+ __builtin_offsetof (RD_PPTT_SLC_PACKAGE, Slc),
+ PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 1),
+
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ Package.Slc),
+
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT (
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */
+ 0, /* Next level of cache */
+ SIZE_16MB, /* Size */
+ 16384, /* Num of sets */
+ 16, /* Associativity */
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */
+ 64 /* Line size */
+ ),
+
+ {
+ PPTT_CLUSTER_INIT (0, 0),
+ PPTT_CLUSTER_INIT (0, 1),
+ PPTT_CLUSTER_INIT (0, 2),
+ PPTT_CLUSTER_INIT (0, 3),
+ PPTT_CLUSTER_INIT (0, 4),
+ PPTT_CLUSTER_INIT (0, 5),
+ PPTT_CLUSTER_INIT (0, 6),
+ PPTT_CLUSTER_INIT (0, 7),
+ PPTT_CLUSTER_INIT (0, 8),
+ PPTT_CLUSTER_INIT (0, 9),
+ PPTT_CLUSTER_INIT (0, 10),
+ PPTT_CLUSTER_INIT (0, 11),
+ PPTT_CLUSTER_INIT (0, 12),
+ PPTT_CLUSTER_INIT (0, 13),
+ PPTT_CLUSTER_INIT (0, 14),
+ PPTT_CLUSTER_INIT (0, 15)
+ }
+ }
+};
+
+/*
+ * Reference the table being generated to prevent the optimizer from removing
+ * the data structure from the executable
+ */
+VOID* CONST ReferenceAcpiTable = &Pptt;
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [edk2-platforms][PATCH V1 7/8] Platform/Sgi: ACPI PPTT Table for RD-V1 quad-chip platform
2021-04-02 9:12 [edk2-platforms][PATCH V1 0/8] Platform/Sgi: Add PPTT table for SGI/RD platforms Pranav Madhu
` (5 preceding siblings ...)
2021-04-02 9:12 ` [edk2-platforms][PATCH V1 6/8] Platform/Sgi: ACPI PPTT Table for RD-V1 platform Pranav Madhu
@ 2021-04-02 9:12 ` Pranav Madhu
2021-04-02 9:12 ` [edk2-platforms][PATCH V1 8/8] Platform/Sgi: ACPI PPTT table for RD-N2 platform Pranav Madhu
7 siblings, 0 replies; 14+ messages in thread
From: Pranav Madhu @ 2021-04-02 9:12 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Leif Lindholm, Sami Mujawar
The RD-V1 quad-chip platform consists of four chips connected over cache
coherent interconnect. Each chip on the platform includes four single-
thread CPUS. Each of the CPUs include 64KB L1 Data cache, 64KB L1
Instruction cache and 1MB L2 cache. The platform also includes a system
level cache of 16MB per chip. Add PPTT table for RD-V1 quad-chip
platform with this information.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
.../SgiPkg/AcpiTables/RdV1McAcpiTables.inf | 3 +-
.../ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc | 172 ++++++++++++++++++
2 files changed, 174 insertions(+), 1 deletion(-)
create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf
index 08351b1e98e6..40fd6ae00270 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf
@@ -1,7 +1,7 @@
## @file
# ACPI table data and ASL sources required to boot the platform.
#
-# Copyright (c) 2020, Arm Ltd. All rights reserved.
+# Copyright (c) 2020-2021, Arm Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -23,6 +23,7 @@
Mcfg.aslc
RdV1Mc/Dsdt.asl
RdV1Mc/Madt.aslc
+ RdV1Mc/Pptt.aslc
RdV1Mc/Srat.aslc
Spcr.aslc
Ssdt.asl
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc
new file mode 100644
index 000000000000..f5c7b0f61d94
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc
@@ -0,0 +1,172 @@
+/** @file
+* Processor Properties Topology Table (PPTT) for RD-V1 quad-chip platform
+*
+* This file describes the topological structure of the processor block on the
+* RD-V1 quad-chip platform in the form as defined by ACPI PPTT table. The RD-V1
+* quad-chip platform is composed of four identical chips connected over cache
+* coherent interconnect. Each of the chip on the platform includes four single
+* thread CPUS. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction
+* cache and 1MB L2 cache. The platform also includes a system level cache of
+* 16MB per chip.
+*
+* Copyright (c) 2021, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+
+#define CHIP_COUNT FixedPcdGet32 (PcdChipCount)
+
+#define PPTT_CORE_INIT(pid, cid, coreId) \
+ { \
+ /* Parameters for CPU Core */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ __builtin_offsetof (RD_PPTT_CORE, DCache), /* Length */ \
+ PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[pid].Cluster[cid]), /* Parent */ \
+ ((pid << 2) | cid), /* ACPI Id */ \
+ 2 /* Num of private resource */\
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ { \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[pid].Cluster[cid].Core[coreId].DCache), \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[pid].Cluster[cid].Core[coreId].ICache) \
+ }, \
+ \
+ /* L1 Data cache Parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[pid].Cluster[cid].Core[coreId].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_64KB, /* Size */ \
+ 256, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_DATA_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L1 Instruction cache Parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[pid].Cluster[cid].Core[coreId].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_64KB, /* Size */ \
+ 256, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_INST_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L2 Cache Parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_1MB, /* Size */ \
+ 2048, /* Num of sets */ \
+ 8, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ }
+
+#define PPTT_CLUSTER_INIT(pid, cid) \
+ { \
+ /* Parameters for Cluster */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ __builtin_offsetof (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ \
+ PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[pid]), /* Parent */ \
+ 0, /* ACPI Id */ \
+ 0 /* Num of private resource */ \
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[pid].Cluster[cid].Core), \
+ \
+ { \
+ PPTT_CORE_INIT (pid, cid, 0) \
+ } \
+ }
+
+#define PPTT_PACKAGE_INIT(pid) \
+ { \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ __builtin_offsetof (RD_PPTT_SLC_PACKAGE, Slc), /* Length */ \
+ PPTT_PROCESSOR_PACKAGE_FLAGS, /* Flag */ \
+ 0, /* Parent */ \
+ 0, /* ACPI Id */ \
+ 1 /* Num of private resource */\
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[pid].Slc), \
+ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_16MB, /* Size */ \
+ 16384, /* Num of sets */ \
+ 16, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ { \
+ PPTT_CLUSTER_INIT (pid, 0), \
+ PPTT_CLUSTER_INIT (pid, 1), \
+ PPTT_CLUSTER_INIT (pid, 2), \
+ PPTT_CLUSTER_INIT (pid, 3), \
+ } \
+ }
+
+#pragma pack(1)
+/*
+ * Processor Properties Topology Table
+ */
+typedef struct {
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ RD_PPTT_SLC_PACKAGE Package[CHIP_COUNT];
+} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+#pragma pack ()
+
+STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ )
+ },
+
+ {
+ PPTT_PACKAGE_INIT (0),
+ PPTT_PACKAGE_INIT (1),
+ PPTT_PACKAGE_INIT (2),
+ PPTT_PACKAGE_INIT (3)
+ }
+};
+
+/*
+ * Reference the table being generated to prevent the optimizer from removing
+ * the data structure from the executable
+ */
+VOID* CONST ReferenceAcpiTable = &Pptt;
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [edk2-platforms][PATCH V1 8/8] Platform/Sgi: ACPI PPTT table for RD-N2 platform
2021-04-02 9:12 [edk2-platforms][PATCH V1 0/8] Platform/Sgi: Add PPTT table for SGI/RD platforms Pranav Madhu
` (6 preceding siblings ...)
2021-04-02 9:12 ` [edk2-platforms][PATCH V1 7/8] Platform/Sgi: ACPI PPTT Table for RD-V1 quad-chip platform Pranav Madhu
@ 2021-04-02 9:12 ` Pranav Madhu
7 siblings, 0 replies; 14+ messages in thread
From: Pranav Madhu @ 2021-04-02 9:12 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Leif Lindholm, Sami Mujawar
The RD-N2 platform includes sixteen single-thread CPUS. Each of the
CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB L2
cache. The platform also includes a system level cache of 32MB. Add PPTT
table for RD-N2 platform with this information.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
.../ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 3 +-
Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc | 166 ++++++++++++++++++
2 files changed, 168 insertions(+), 1 deletion(-)
create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
index 2ec3e42473a9..c1282a3422ab 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
@@ -1,7 +1,7 @@
## @file
# ACPI table data and ASL sources required to boot the platform.
#
-# Copyright (c) 2020, Arm Ltd. All rights reserved.
+# Copyright (c) 2020-2021, Arm Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -22,6 +22,7 @@
Mcfg.aslc
RdN2/Dsdt.asl
RdN2/Madt.aslc
+ RdN2/Pptt.aslc
Spcr.aslc
Ssdt.asl
SsdtRos.asl
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc
new file mode 100644
index 000000000000..1073c8b1d4f5
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc
@@ -0,0 +1,166 @@
+/** @file
+* Processor Properties Topology Table (PPTT) for RD-N2 platform
+*
+* This file describes the topological structure of the processor block on the
+* RD-N2 platform in the form as defined by ACPI PPTT table. The RD-N2 platform
+* includes sixteen single-thread CPUS. Each of the CPUs include 64KB L1 Data
+* cache, 64KB L1 Instruction cache and 1MB L2 cache. The platform also includes
+* system level cache of 32MB.
+*
+* Copyright (c) 2021, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+
+#define PPTT_CORE_INIT(pid, cid, coreId) \
+ { \
+ /* Parameters for CPU Core */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ __builtin_offsetof (RD_PPTT_CORE, DCache), /* Length */ \
+ PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid]), /* Parent */ \
+ ((pid << 4) | cid), /* ACPI Id */ \
+ 2 /* Num of private resource */\
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ { \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[coreId].DCache), \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[coreId].ICache) \
+ }, \
+ \
+ /* L1 Data cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[coreId].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_64KB, /* Size */ \
+ 256, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_DATA_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L1 Instruction cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[coreId].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_64KB, /* Size */ \
+ 256, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_INST_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L2 cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_1MB, /* Size */ \
+ 2048, /* Num of sets */ \
+ 8, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ }
+
+#define PPTT_CLUSTER_INIT(pid, cid) \
+ { \
+ /* Parameters for Cluster */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ __builtin_offsetof (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ \
+ PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package), /* Parent */ \
+ 0, /* ACPI Id */ \
+ 0 /* Num of private resource */ \
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core), \
+ \
+ { \
+ PPTT_CORE_INIT (pid, cid, 0) \
+ } \
+ }
+
+#pragma pack(1)
+/*
+ * Processor Properties Topology Table
+ */
+typedef struct {
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ RD_PPTT_SLC_PACKAGE Package;
+} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+#pragma pack ()
+
+STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ )
+ },
+
+ {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (
+ __builtin_offsetof (RD_PPTT_SLC_PACKAGE, Slc),
+ PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 1),
+
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ Package.Slc),
+
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT (
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */
+ 0, /* Next level of cache */
+ SIZE_32MB, /* Size */
+ 32768, /* Num of sets */
+ 16, /* Associativity */
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */
+ 64), /* Line size */
+
+ {
+ PPTT_CLUSTER_INIT (0, 0),
+ PPTT_CLUSTER_INIT (0, 1),
+ PPTT_CLUSTER_INIT (0, 2),
+ PPTT_CLUSTER_INIT (0, 3),
+ PPTT_CLUSTER_INIT (0, 4),
+ PPTT_CLUSTER_INIT (0, 5),
+ PPTT_CLUSTER_INIT (0, 6),
+ PPTT_CLUSTER_INIT (0, 7),
+ PPTT_CLUSTER_INIT (0, 8),
+ PPTT_CLUSTER_INIT (0, 9),
+ PPTT_CLUSTER_INIT (0, 10),
+ PPTT_CLUSTER_INIT (0, 11),
+ PPTT_CLUSTER_INIT (0, 12),
+ PPTT_CLUSTER_INIT (0, 13),
+ PPTT_CLUSTER_INIT (0, 14),
+ PPTT_CLUSTER_INIT (0, 15)
+ }
+ }
+};
+
+/*
+ * Reference the table being generated to prevent the optimizer from removing
+ * the data structure from the executable
+ */
+VOID* CONST ReferenceAcpiTable = &Pptt;
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread