From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web09.4944.1617868134188890739 for ; Thu, 08 Apr 2021 00:48:54 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.43, mailfrom: yun.lou@intel.com) IronPort-SDR: Jsfr8A/VqQUp/dE5whLV5IIHHJIwD1CU1jUfPydUyZEP/w6hs1/XppGANM/Oq5eXUaHYH8LURZ qB+4E5/4d8Jw== X-IronPort-AV: E=McAfee;i="6000,8403,9947"; a="278753059" X-IronPort-AV: E=Sophos;i="5.82,205,1613462400"; d="scan'208";a="278753059" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Apr 2021 00:48:53 -0700 IronPort-SDR: bRFvpvkCMMUHldCybh0qkW5fJEtQgUmsVRjg0Px3VtxPuqkMDhEsvfDwx2XDvaDwzAPQ7+gDID PlmuK3ul7n8w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,205,1613462400"; d="scan'208";a="519752909" Received: from shwdeopenlab102.ccr.corp.intel.com ([10.239.183.74]) by fmsmga001.fm.intel.com with ESMTP; 08 Apr 2021 00:48:51 -0700 From: "Jason Lou" To: devel@edk2.groups.io Cc: Jason , Michael D Kinney , Liming Gao , Zhiguang Liu , Ray Ni Subject: [PATCH v2] MdePkg/Cpuid.h: Define new element in CPUID Leaf(07h) data structure. Date: Thu, 8 Apr 2021 15:48:47 +0800 Message-Id: <20210408074847.14681-1-yun.lou@intel.com> X-Mailer: git-send-email 2.28.0.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3309 Define new element(Hybird) in CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (07h) data structure. Signed-off-by: Jason Lou Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Ray Ni --- MdePkg/Include/Register/Intel/Cpuid.h | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/MdePkg/Include/Register/Intel/Cpuid.h b/MdePkg/Include/Registe= r/Intel/Cpuid.h index 19af99b6af..737d41d928 100644 --- a/MdePkg/Include/Register/Intel/Cpuid.h +++ b/MdePkg/Include/Register/Intel/Cpuid.h @@ -6,7 +6,7 @@ If a register returned is a single 32-bit value, then a data structure i= s=0D not provided for that register.=0D =0D - Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
=0D + Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @par Specification Reference:=0D @@ -1550,9 +1550,17 @@ typedef union { ///=0D UINT32 AVX512_4FMAPS:1;=0D ///=0D - /// [Bit 25:4] Reserved.=0D + /// [Bit 14:4] Reserved.=0D ///=0D - UINT32 Reserved2:22;=0D + UINT32 Reserved2:11;=0D + ///=0D + /// [Bit 15] Hybrid. If 1, the processor is identified as a hybrid par= t.=0D + ///=0D + UINT32 Hybrid:1;=0D + ///=0D + /// [Bit 25:16] Reserved.=0D + ///=0D + UINT32 Reserved3:10;=0D ///=0D /// [Bit 26] Enumerates support for indirect branch restricted specula= tion=0D /// (IBRS) and the indirect branch pre-dictor barrier (IBPB). Processo= rs=0D @@ -1581,7 +1589,7 @@ typedef union { ///=0D /// [Bit 30] Reserved.=0D ///=0D - UINT32 Reserved3:1;=0D + UINT32 Reserved4:1;=0D ///=0D /// [Bit 31] Enumerates support for Speculative Store Bypass Disable (= SSBD).=0D /// Processors that set this bit sup-port the IA32_SPEC_CTRL MSR. They= allow=0D --=20 2.28.0.windows.1