From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web12.5179.1617869245250643460 for ; Thu, 08 Apr 2021 01:07:25 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.65, mailfrom: ray.ni@intel.com) IronPort-SDR: AeIB2j+O90iInZlchJnDIIs6gCJepcu/h3dFOsHio8lZLKDwbbZZ7ChF79C/erGlVRA49BSi3y ZbRbjhDKd6ZQ== X-IronPort-AV: E=McAfee;i="6000,8403,9947"; a="193530548" X-IronPort-AV: E=Sophos;i="5.82,205,1613462400"; d="scan'208";a="193530548" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Apr 2021 01:07:24 -0700 IronPort-SDR: TLijP7gJuMUqN/4NSdxj+1cYkrd/4FYd0GIWDHbmburpzqdJ7Y4BB9sr7Vi8iIFlIT9yzVIDok +IH3Suh4khIg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,205,1613462400"; d="scan'208";a="422129401" Received: from ray-dev.ccr.corp.intel.com ([10.239.158.87]) by orsmga008.jf.intel.com with ESMTP; 08 Apr 2021 01:07:22 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Liming Gao , Eric Dong Subject: [PATCH] MinPlatformPkg: Add PcdFlashMicrocodeOffset Date: Thu, 8 Apr 2021 16:07:11 +0800 Message-Id: <20210408080711.1789-1-ray.ni@intel.com> X-Mailer: git-send-email 2.27.0.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Add PcdFlashMicrocodeOffset in MinPlatformPkg.dec and update SecFspWrapperPlatformSecLib library to use the microcode location PCDs defined in MinPlatformPkg. Signed-off-by: Ray Ni Cc: Chasel Chiu Cc: Nate DeSimone Cc: Liming Gao Cc: Eric Dong --- .../SecFspWrapperPlatformSecLib.inf | 8 ++++---- .../Library/SecFspWrapperPlatformSecLib/SecRamInitData.c | 6 +++--- Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec | 3 ++- 3 files changed, 9 insertions(+), 8 deletions(-) diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/SecFspWrapperPlatformSecLib.inf b/Platform/Intel/MinPlatform= Pkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSec= Lib.inf index 4f3fa9fa34..68ce5d81cd 100644 --- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/SecFspWrapperPlatformSecLib.inf +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/SecFspWrapperPlatformSecLib.inf @@ -1,7 +1,7 @@ ## @file=0D # Provide FSP wrapper platform sec related function.=0D #=0D -# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
= =0D +# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
= =0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -88,9 +88,9 @@ gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable ## C= ONSUMES=0D =0D [FixedPcd]=0D - gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress ## C= ONSUMES=0D - gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ## C= ONSUMES=0D - gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset ## C= ONSUMES=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase ## C= ONSUMES=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize ## C= ONSUMES=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashMicrocodeOffset ## C= ONSUMES=0D gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress ## C= ONSUMES=0D gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize ## C= ONSUMES=0D gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## C= ONSUMES=0D diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/SecRamInitData.c b/Platform/Intel/MinPlatformPkg/FspWrapper/= Library/SecFspWrapperPlatformSecLib/SecRamInitData.c index b356327b4c..b4e10cca1f 100644 --- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/SecRamInitData.c +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/SecRamInitData.c @@ -1,7 +1,7 @@ /** @file=0D Provide TempRamInitParams data.=0D =0D -Copyright (c) 2017, Intel Corporation. All rights reserved.
=0D +Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D **/=0D @@ -24,8 +24,8 @@ GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD_CORE_DATA Fs= ptUpdDataPtr =3D { }=0D },=0D {=0D - ((UINT32)FixedPcdGet64 (PcdCpuMicrocodePatchAddress) + FixedPcdGet32 (= PcdFlashMicrocodeOffset)),=0D - ((UINT32)FixedPcdGet64 (PcdCpuMicrocodePatchRegionSize) - FixedPcdGet3= 2 (PcdFlashMicrocodeOffset)),=0D + FixedPcdGet32 (PcdFlashFvMicrocodeBase) + FixedPcdGet32 (PcdFlashMicro= codeOffset),=0D + FixedPcdGet32 (PcdFlashFvMicrocodeSize) - FixedPcdGet32 (PcdFlashMicro= codeOffset),=0D 0, // Set CodeRegionBase as 0, so that caching will be 4GB-(C= odeRegionSize > LLCSize ? LLCSize : CodeRegionSize) will be used.=0D FixedPcdGet32 (PcdFlashCodeCacheSize),=0D { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,=0D diff --git a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec b/Platform/In= tel/MinPlatformPkg/MinPlatformPkg.dec index 2b246cf0ac..1c9ae665a6 100644 --- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec +++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec @@ -6,7 +6,7 @@ # INF files to generate AutoGen.c and AutoGen.h files=0D # for the build infrastructure.=0D #=0D -# Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.
=0D +# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -165,6 +165,7 @@ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase|0xFFE60000|UINT32|= 0x30000004=0D gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize|0x000A0000|UINT32|= 0x30000005=0D gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset|0x00660000|UINT3= 2|0x30000006=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashMicrocodeOffset|0x60|UINT32|0x3000= 0007=0D =0D gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|0x00000000|UINT32|= 0x20000004=0D gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize|0x00000000|UINT32|= 0x20000005=0D --=20 2.27.0.windows.1