From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web09.7579.1618367670644399683 for ; Tue, 13 Apr 2021 19:34:30 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.93, mailfrom: yun.lou@intel.com) IronPort-SDR: 0OZfOJM7irUDKaE+B+W3p2lr4/3J30rPjdKfhmyQgtu/nV2MbPwnMWXSsPeOppGWKTNn/BYFc6 1v1TNctNXrYg== X-IronPort-AV: E=McAfee;i="6200,9189,9953"; a="191363303" X-IronPort-AV: E=Sophos;i="5.82,221,1613462400"; d="scan'208";a="191363303" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2021 19:34:29 -0700 IronPort-SDR: KsI16nYwY0khPrYd7uInUYMsRfmMevhR3o73SJ+wjNc2aq1WTp9Y78SS84W71nCqBqPCFq9luq PYEbX3wZCOtA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,221,1613462400"; d="scan'208";a="399000911" Received: from shwdeopenlab102.ccr.corp.intel.com ([10.239.183.74]) by orsmga002.jf.intel.com with ESMTP; 13 Apr 2021 19:34:28 -0700 From: "Jason Lou" To: devel@edk2.groups.io Cc: Jason , Ray Ni Subject: [PATCH v1] IntelFsp2WrapperPkg: Remove microcode PCDs Date: Wed, 14 Apr 2021 10:34:08 +0800 Message-Id: <20210414023408.15262-1-yun.lou@intel.com> X-Mailer: git-send-email 2.28.0.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3334 IntelFsp2WrapperPkg defines following PCDs: PcdCpuMicrocodePatchAddress PcdCpuMicrocodePatchRegionSize PcdFlashMicrocodeOffset But the meanings of PcdCpuMicrocodePatchAddress and PcdCpuMicrocodePatchRegionSize are different from the ones that have The same name in UefiCpuPkg. To avoid confusion, remove the three PCDs defined in IntelFsp2WrapperPkg. Signed-off-by: Jason Lou Cc: Ray Ni --- IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamInitDa= ta.c | 6 +++--- IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec = | 8 +------- IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecFspWrappe= rPlatformSecLibSample.inf | 7 +++---- 3 files changed, 7 insertions(+), 14 deletions(-) diff --git a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/= SecRamInitData.c b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibS= ample/SecRamInitData.c index 96b47e23da..e57b5b57be 100644 --- a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamI= nitData.c +++ b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamI= nitData.c @@ -1,7 +1,7 @@ /** @file=0D Sample to provide TempRamInitParams data.=0D =0D - Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
=0D + Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D **/=0D @@ -52,8 +52,8 @@ GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD_CORE_DATA Fs= ptUpdDataPtr =3D { }=0D },=0D {=0D - ((UINT32)FixedPcdGet64 (PcdCpuMicrocodePatchAddress) + FixedPcdGet32 (= PcdFlashMicrocodeOffset)),=0D - ((UINT32)FixedPcdGet64 (PcdCpuMicrocodePatchRegionSize) - FixedPcdGet3= 2 (PcdFlashMicrocodeOffset)),=0D + FixedPcdGet32 (PcdCpuMicrocodePatchAddress),=0D + FixedPcdGet32 (PcdCpuMicrocodePatchRegionSize),=0D FixedPcdGet32 (PcdFlashCodeCacheAddress),=0D FixedPcdGet32 (PcdFlashCodeCacheSize),=0D }=0D diff --git a/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec b/IntelFsp2Wrapper= Pkg/IntelFsp2WrapperPkg.dec index 6852bf1271..a3b9363779 100644 --- a/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec +++ b/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec @@ -1,7 +1,7 @@ ## @file=0D # Provides drivers and definitions to support fsp in EDKII bios.=0D #=0D -# Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
=0D +# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D ##=0D @@ -56,12 +56,6 @@ ## Provides the size of the BIOS Flash Device.=0D gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize|0x00200000|UINT32|= 0x10000002=0D =0D - ## Indicates the base address of the first Microcode Patch in the Microc= ode Region=0D - gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|0= x10000005=0D - gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0|UINT6= 4|0x10000006=0D - ## Indicates the offset of the Cpu Microcode.=0D - gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset|0x90|UINT32|0x10= 000007=0D -=0D ## Indicate the PEI memory size platform want to report=0D gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x1800000|UINT32|0x4000= 0004=0D ## Indicate the PEI memory size platform want to report=0D diff --git a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/= SecFspWrapperPlatformSecLibSample.inf b/IntelFsp2WrapperPkg/Library/SecFspW= rapperPlatformSecLibSample/SecFspWrapperPlatformSecLibSample.inf index d7f8301bef..027b127724 100644 --- a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecFspW= rapperPlatformSecLibSample.inf +++ b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecFspW= rapperPlatformSecLibSample.inf @@ -1,7 +1,7 @@ ## @file=0D # Sample to provide FSP wrapper platform sec related function.=0D #=0D -# Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
= =0D +# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
= =0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -76,8 +76,7 @@ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## CONSU= MES=0D =0D [FixedPcd]=0D - gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress ## CONSU= MES=0D - gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ## CONSU= MES=0D - gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset ## CONSU= MES=0D + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress ## CONSU= MES=0D + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ## CONSU= MES=0D gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress ## CONSU= MES=0D gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize ## CONSU= MES=0D --=20 2.28.0.windows.1