From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f50.google.com (mail-pj1-f50.google.com [209.85.216.50]) by mx.groups.io with SMTP id smtpd.web08.7778.1618369174551310002 for ; Tue, 13 Apr 2021 19:59:34 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@gmail.com header.s=20161025 header.b=QAIDpWk8; spf=pass (domain: gmail.com, ip: 209.85.216.50, mailfrom: kuqin12@gmail.com) Received: by mail-pj1-f50.google.com with SMTP id cu16so7508493pjb.4 for ; Tue, 13 Apr 2021 19:59:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kRw48Z/eIsAP74JafGkFQhIQHmAjD6tb0CkgXZMpbX4=; b=QAIDpWk8OvWLjl7rnYA/C3h1T0n6NgpwuNzOKZTu2F/NdvthrjK/BQWV+4+nwZUj7u 148BuHqUJm3meUZwCpJ1hGAj5QSMwmFQNpf8RAyeoC/dF00tYVtaWMnBEPg7Elp5VRJ5 kyJhn/S6cd6xEWpq+kZshZ9s6uhY2S5Xz9yQL1oKGUhPlHQJGOqLBnorxB96OySAPMJp O275mm7X1Y5H+/FTwh65oBNRLixfcK1J0Z0cfrqb2zgyo+xGA/h2iCMRHD7JATFnv+ur 2hTBAdAM/tKyP4R51pjIQTqwXNPqW5WqDsNqv+Bw2VAqpXV+dosavL8FO0JBvLdqaiKi DuTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kRw48Z/eIsAP74JafGkFQhIQHmAjD6tb0CkgXZMpbX4=; b=ibMpy+2Ey1vUaQ2Z4AvxdUjYjZPeUNKXT6mW7JEvNA6cI//2IVtKwz+83xP8zt5HQ/ ItwTHIq0jXivJDE5Bx5j16gGV1OgvONEH7a1iGI/azm4u12qcZ+9Y/CB4W0K4ssRayvZ ++3FJM0LUjBFZCJpw+1yQRHgBhiLpGi8X3Zm4Igew8ozUXf5CL+Ab+Sx2kfr5TkIqVnY NrW2nDZTx+sCg2w5JFFDYVXCF1+olaAv7ZqZmvBHPh6xCQxcmoPu/xZH5b0vygFohYj2 ikwI1gCHqJvXHMZqoDyT6uUd3i24hAn8kisFBmBl4GodMdBi8iWtpiFnZPbDYrqEnrpw +GyQ== X-Gm-Message-State: AOAM530QzPrwuWqLJ28FkVPfuwTIxlhYluV/TKbNDBixuUOvbzqnPmJP eRLkAC7JZhkBatkfeO5/2Q4K5HfU6Jk= X-Google-Smtp-Source: ABdhPJwbZT+v1ZLTmdqV3X3TCCgItNJLbS8eJx3xKHfHAamWDDI7/z3B6zf1CbJIKGIRfpHT0EbaCA== X-Received: by 2002:a17:90a:34c5:: with SMTP id m5mr1003252pjf.147.1618369173923; Tue, 13 Apr 2021 19:59:33 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([50.35.88.161]) by smtp.gmail.com with ESMTPSA id q19sm15292442pgv.38.2021.04.13.19.59.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Apr 2021 19:59:33 -0700 (PDT) From: "Kun Qin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Laszlo Ersek , Rahul Kumar Subject: [PATCH v1 1/1] UefiCpuPkg: PiSmmCpuDxeSmm: Not to Change Bitwidth During Static Paging Date: Tue, 13 Apr 2021 19:59:22 -0700 Message-Id: <20210414025922.850-2-kuqin12@gmail.com> X-Mailer: git-send-email 2.31.0.windows.1 In-Reply-To: <20210414025922.850-1-kuqin12@gmail.com> References: <20210414025922.850-1-kuqin12@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3300 Current implementation of SetStaticPageTable routine in PiSmmCpuDxeSmm driver will check a global variable mPhysicalAddressBits, and eventually cap any value larger than 39 at 39. This global variable is used in ConvertMemoryPageAttributes, which backs SmmSetMemoryAttributes and SmmClearMemoryAttributes. Thus for a processor that supports more than 39 bits width, trying to mark page table regions higher than 39-bit will always return EFI_UNSUPPROTED. This change replaced the changed bitwidth to a stack based variable. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Cc: Rahul Kumar Signed-off-by: Kun Qin --- UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 25 +++++++++++--------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c index 6902584b1fbd..0caee8a27abe 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c @@ -226,6 +226,7 @@ SetStaticPageTable ( UINTN IndexOfPml4Entries; UINTN IndexOfPdpEntries; UINTN IndexOfPageDirectoryEntries; + UINT64 PhysicalAddressBits; UINT64 *PageMapLevel5Entry; UINT64 *PageMapLevel4Entry; UINT64 *PageMap; @@ -237,26 +238,28 @@ SetStaticPageTable ( // IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses // when 5-Level Paging is disabled. // - ASSERT (mPhysicalAddressBits <= 52); - if (!m5LevelPagingNeeded && mPhysicalAddressBits > 48) { - mPhysicalAddressBits = 48; + PhysicalAddressBits = mPhysicalAddressBits; + + ASSERT (PhysicalAddressBits <= 52); + if (!m5LevelPagingNeeded && PhysicalAddressBits > 48) { + PhysicalAddressBits = 48; } NumberOfPml5EntriesNeeded = 1; - if (mPhysicalAddressBits > 48) { - NumberOfPml5EntriesNeeded = (UINTN) LShiftU64 (1, mPhysicalAddressBits - 48); - mPhysicalAddressBits = 48; + if (PhysicalAddressBits > 48) { + NumberOfPml5EntriesNeeded = (UINTN) LShiftU64 (1, PhysicalAddressBits - 48); + PhysicalAddressBits = 48; } NumberOfPml4EntriesNeeded = 1; - if (mPhysicalAddressBits > 39) { - NumberOfPml4EntriesNeeded = (UINTN) LShiftU64 (1, mPhysicalAddressBits - 39); - mPhysicalAddressBits = 39; + if (PhysicalAddressBits > 39) { + NumberOfPml4EntriesNeeded = (UINTN) LShiftU64 (1, PhysicalAddressBits - 39); + PhysicalAddressBits = 39; } NumberOfPdpEntriesNeeded = 1; - ASSERT (mPhysicalAddressBits > 30); - NumberOfPdpEntriesNeeded = (UINTN) LShiftU64 (1, mPhysicalAddressBits - 30); + ASSERT (PhysicalAddressBits > 30); + NumberOfPdpEntriesNeeded = (UINTN) LShiftU64 (1, PhysicalAddressBits - 30); // // By architecture only one PageMapLevel4 exists - so lets allocate storage for it. -- 2.31.0.windows.1