From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pl1-f173.google.com (mail-pl1-f173.google.com [209.85.214.173]) by mx.groups.io with SMTP id smtpd.web11.19498.1618431960441338472 for ; Wed, 14 Apr 2021 13:26:00 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@gmail.com header.s=20161025 header.b=nnp7NdJk; spf=pass (domain: gmail.com, ip: 209.85.214.173, mailfrom: kuqin12@gmail.com) Received: by mail-pl1-f173.google.com with SMTP id w8so8457295plg.9 for ; Wed, 14 Apr 2021 13:26:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OgDn6AbZBXArd0x45Qim8Tb5A2zvQD86UUNuxg9Fi5M=; b=nnp7NdJkuZh/ANNIylTZd7WOqO/d/EPGLuZqSvttfMR+5YqavQKywqZPmvVpP3cDGC tpRoCaRPTYinUPNOKJgpQjGwAbYUDhqBIqFrMJLQq/GUvERn2mUE+Yvb77YKMLdWHwRM veXFEaFu02qyVIDdgMRX8BA0kS5Y9v7GnSnkkpvmY2avRNRtwL2ZcLVFQBLzAmh3liBD Q04cH1f40yhqAyFt0jl8e6n1zGWv0KGjAPoKtDbJ1gFiSUBjkfAunGGy/lXhLfcOMg8a mjnAytj3OOPGicxXPnziEYXmY4+avSKlwyI7ND6uGFlbvdiN5BMvSJhIydIST5CxC7U9 961A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OgDn6AbZBXArd0x45Qim8Tb5A2zvQD86UUNuxg9Fi5M=; b=HsUA4QkWJr/bI6yQ165D8DHg+skc/jlwqwAtTjWzZF+zd1tlZyoySKSVPqlvFXLw0J vnx7M0DNPetdEFLvj0uzm5/L1anzSjUUfKSN72YM9hdZqCyOsfm5d9JlgRSbV4CbmKkO yBfDTFCMptLgDBVzwkiTp9nECTstBNK7H5rWLBODJb0wa3b102FTLufiNSPeG+qQJczh M+hFnT3bSj73e/N8aHxYd4Rfpiy1+12bTzcdvqz2AKmuY1K5DGcavwcT9LZqSkmHC1R8 tD/YxeCKzKHE1RcjQJieiLCjSP8OlzcJqeIysqlGLpb5tgZyTNtombBCyyNV6uPMuQ4B aCng== X-Gm-Message-State: AOAM5335IekwBV7RFi2BURY4bZ+tKN5sUvR5LnYmobRr/5eM3aNW9mrB m6NkUQjAqXd5P6gyOgiLK7kloVmWKTs= X-Google-Smtp-Source: ABdhPJyMc2nlZgIwovLNwUiDoEJq3xaIzl3zyLoQ/OhRQ3BK3hOG7+KBrA7KJS+YzLhqBaf2vSqvbQ== X-Received: by 2002:a17:90a:3183:: with SMTP id j3mr3712047pjb.228.1618431959687; Wed, 14 Apr 2021 13:25:59 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([50.35.88.161]) by smtp.gmail.com with ESMTPSA id q19sm336524pgv.38.2021.04.14.13.25.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Apr 2021 13:25:59 -0700 (PDT) From: "Kun Qin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Laszlo Ersek , Rahul Kumar Subject: [PATCH v2 1/1] UefiCpuPkg: PiSmmCpuDxeSmm: Not to Change Bitwidth During Static Paging Date: Wed, 14 Apr 2021 13:25:47 -0700 Message-Id: <20210414202547.394-2-kuqin12@gmail.com> X-Mailer: git-send-email 2.31.0.windows.1 In-Reply-To: <20210414202547.394-1-kuqin12@gmail.com> References: <20210414202547.394-1-kuqin12@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3300 Current implementation of SetStaticPageTable routine in PiSmmCpuDxeSmm driver will check a global variable mPhysicalAddressBits, and eventually cap any value larger than 39 at 39. This global variable is used in ConvertMemoryPageAttributes, which backs SmmSetMemoryAttributes and SmmClearMemoryAttributes. Thus for a processor that supports more than 39 bits width, trying to mark page table regions higher than 39-bit will always return EFI_UNSUPPROTED. This change updated the interface of SetStaticPageTable function to take PhysicalAddressBits as an input parameter, in order to avoid changing/ accessing the global variable. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Cc: Rahul Kumar Fixes: 4eee0cc7cc0db74489b99c19eba056b53eda6358 Signed-off-by: Kun Qin --- Notes: v2: - SetStaticPageTable interface update [Ray] - Commit message updates, variable type change [Laszlo] UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 30 +++++++++++--------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c index 6902584b1fbd..d6f8dd94d303 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c @@ -211,11 +211,13 @@ CalculateMaximumSupportAddress ( /** Set static page table. - @param[in] PageTable Address of page table. + @param[in] PageTable Address of page table. + @param[in] PhysicalAddressBits The maximum physical address bits supported. **/ VOID SetStaticPageTable ( - IN UINTN PageTable + IN UINTN PageTable, + IN UINT8 PhysicalAddressBits ) { UINT64 PageAddress; @@ -237,26 +239,26 @@ SetStaticPageTable ( // IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses // when 5-Level Paging is disabled. // - ASSERT (mPhysicalAddressBits <= 52); - if (!m5LevelPagingNeeded && mPhysicalAddressBits > 48) { - mPhysicalAddressBits = 48; + ASSERT (PhysicalAddressBits <= 52); + if (!m5LevelPagingNeeded && PhysicalAddressBits > 48) { + PhysicalAddressBits = 48; } NumberOfPml5EntriesNeeded = 1; - if (mPhysicalAddressBits > 48) { - NumberOfPml5EntriesNeeded = (UINTN) LShiftU64 (1, mPhysicalAddressBits - 48); - mPhysicalAddressBits = 48; + if (PhysicalAddressBits > 48) { + NumberOfPml5EntriesNeeded = (UINTN) LShiftU64 (1, PhysicalAddressBits - 48); + PhysicalAddressBits = 48; } NumberOfPml4EntriesNeeded = 1; - if (mPhysicalAddressBits > 39) { - NumberOfPml4EntriesNeeded = (UINTN) LShiftU64 (1, mPhysicalAddressBits - 39); - mPhysicalAddressBits = 39; + if (PhysicalAddressBits > 39) { + NumberOfPml4EntriesNeeded = (UINTN) LShiftU64 (1, PhysicalAddressBits - 39); + PhysicalAddressBits = 39; } NumberOfPdpEntriesNeeded = 1; - ASSERT (mPhysicalAddressBits > 30); - NumberOfPdpEntriesNeeded = (UINTN) LShiftU64 (1, mPhysicalAddressBits - 30); + ASSERT (PhysicalAddressBits > 30); + NumberOfPdpEntriesNeeded = (UINTN) LShiftU64 (1, PhysicalAddressBits - 30); // // By architecture only one PageMapLevel4 exists - so lets allocate storage for it. @@ -438,7 +440,7 @@ SmmInitPageTable ( // When access to non-SMRAM memory is restricted, create page table // that covers all memory space. // - SetStaticPageTable ((UINTN)PTEntry); + SetStaticPageTable ((UINTN)PTEntry, mPhysicalAddressBits); } else { // // Add pages to page pool -- 2.31.0.windows.1