From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mx.groups.io with SMTP id smtpd.web09.3806.1618540369748418875 for ; Thu, 15 Apr 2021 19:32:49 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="body hash did not verify" header.i=@linux.microsoft.com header.s=default header.b=TpIokXX5; spf=pass (domain: linux.microsoft.com, ip: 13.77.154.182, mailfrom: mikuback@linux.microsoft.com) Received: from localhost.localdomain (unknown [167.220.2.74]) by linux.microsoft.com (Postfix) with ESMTPSA id 7F12020B8001; Thu, 15 Apr 2021 19:32:49 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 7F12020B8001 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1618540369; bh=Pxdm734t99RO0iiP2vA5N7PsSlG9SVE4Ee+wZ9F9owk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TpIokXX55BRE9w0yJL/y2LFDVHkRselrwA7FA16E7IkRO4S87ZESpsV/2hxx9gWqy Dzp3Gr3MDtGCmUxCSI8izEuvpJgbu7LZVNgkv5Z40azll9WXIX9rgyFXkyAGfmQsRB CSDrE8xJ2uuINzJJ1SNxfLXilpmJKRLbPWHQOqeU= From: "Michael Kubacki" To: devel@edk2.groups.io Cc: Sai Chaganty , Nate DeSimone , Heng Luo Subject: [edk2-platforms][PATCH v1 14/35] TigerlakeOpenBoardPkg: Use IntelSiliconPkg BIOS area and ucode PCDs Date: Thu, 15 Apr 2021 19:31:31 -0700 Message-Id: <20210416023152.771-15-mikuback@linux.microsoft.com> X-Mailer: git-send-email 2.28.0.windows.1 In-Reply-To: <20210416023152.771-1-mikuback@linux.microsoft.com> References: <20210416023152.771-1-mikuback@linux.microsoft.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Michael Kubacki REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3307 Updates PCDs to use the IntelSiliconPkg PCD tokenspace now that the PCDs are declared in IntelSiliconPkg.dec. Cc: Sai Chaganty Cc: Nate DeSimone Cc: Heng Luo Signed-off-by: Michael Kubacki --- Platform/Intel/TigerlakeOpenBoardPkg/BiosInfo/BiosInfo.inf = | 8 ++--- Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Include/Fdf/FlashMapI= nclude.fdf | 4 +-- Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.fdf = | 38 ++++++++++---------- 3 files changed, 25 insertions(+), 25 deletions(-) diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/BiosInfo/BiosInfo.inf b= /Platform/Intel/TigerlakeOpenBoardPkg/BiosInfo/BiosInfo.inf index 66c8814c97bb..56da991ab544 100644 --- a/Platform/Intel/TigerlakeOpenBoardPkg/BiosInfo/BiosInfo.inf +++ b/Platform/Intel/TigerlakeOpenBoardPkg/BiosInfo/BiosInfo.inf @@ -39,8 +39,8 @@ [Packages] BoardModulePkg/BoardModulePkg.dec =20 [Pcd] - gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress ## CON= SUMES - gSiPkgTokenSpaceGuid.PcdBiosSize ## CON= SUMES + gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress ## CON= SUMES + gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize ## CON= SUMES gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase ## CON= SUMES gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize ## CON= SUMES gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase ## CON= SUMES @@ -61,8 +61,8 @@ [Pcd] gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize ## CON= SUMES gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase ## CON= SUMES gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize ## CON= SUMES - gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ## CON= SUMES - gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ## CON= SUMES + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ## CON= SUMES + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ## CON= SUMES gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase ## CON= SUMES gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize ## CON= SUMES gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase ## CON= SUMES diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Include/F= df/FlashMapInclude.fdf b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeUR= vp/Include/Fdf/FlashMapInclude.fdf index b21ae6401f12..24e2a963ba64 100644 --- a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Include/Fdf/Flas= hMapInclude.fdf +++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Include/Fdf/Flas= hMapInclude.fdf @@ -37,8 +37,8 @@ ## Build script checks the requirement. SET gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesOffset =3D= 0x00800000 # Flash addr (0xFFC00000) SET gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesSize =3D= 0x00080000 # Keep 0x80000 or larger -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D= 0x00880000 # Flash addr (0xFFC80000) -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D= 0x00070000 # Keep 0x70000 or larger, change MicrocodeFv.fdf in case tha= t this value change +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D= 0x00880000 # Flash addr (0xFFC80000) +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D= 0x00070000 # Keep 0x70000 or larger, change MicrocodeFv.fdf in case tha= t this value change SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset =3D= 0x008F0000 # Flash addr (0xFFC00000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize =3D= 0x00080000 # SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset =3D= 0x00970000 # Flash addr (0xFFD70000) diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoard= Pkg.fdf b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg= .fdf index 0f645ed63e13..6b37e9a19c84 100644 --- a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.fdf +++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.fdf @@ -29,8 +29,8 @@ [FD.TigerlakeURvp] # assigned with PCD values. Instead, it uses the definitions for its var= iety, which # are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and FLASH_NUM_BLOCKS. # -BaseAddress =3D $(FLASH_BASE) | gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAd= dress #The base address of the FLASH Device. -Size =3D $(FLASH_SIZE) | gSiPkgTokenSpaceGuid.PcdBiosSize = #The size in bytes of the FLASH Device +BaseAddress =3D $(FLASH_BASE) | gIntelSiliconPkgTokenSpaceGuid.PcdBios= AreaBaseAddress #The base address of the FLASH Device. +Size =3D $(FLASH_SIZE) | gIntelSiliconPkgTokenSpaceGuid.PcdBios= Size #The size in bytes of the FLASH Device ErasePolarity =3D 1 BlockSize =3D $(FLASH_BLOCK_SIZE) NumBlocks =3D $(FLASH_NUM_BLOCKS) @@ -41,25 +41,25 @@ [FD.TigerlakeURvp] # Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase, because ma= cro expression is not supported. # So, PlatformSecLib uses PcdFlashAreaBaseAddress + PcdNemCodeCacheBase = to get the real CodeCache base address. SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase =3D $(gMinPlatformPkgTokenS= paceGuid.PcdFlashFvPreMemoryOffset) -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D $(gSiPkgTokenSpaceG= uid.PcdBiosAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvO= ffset) +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D $(gIntelS= iliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gIntelSiliconPkgToken= SpaceGuid.PcdFlashMicrocodeFvOffset) SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeOffset =3D 0x1000 -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D $(gSiPkgTokenSpaceG= uid.PcdBiosAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvO= ffset) -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D $(gSiPkgTokenSpaceG= uid.PcdFlashMicrocodeFvSize) -SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gSiPkgTo= kenSpaceGuid.PcdFlashMicrocodeFvBase) + $(gSiPkgTokenSpaceGuid.PcdFlashMi= crocodeOffset) -SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(gSiPk= gTokenSpaceGuid.PcdFlashMicrocodeFvSize) - $(gSiPkgTokenSpaceGuid.PcdFlas= hMicrocodeOffset) +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D $(gIntelS= iliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gIntelSiliconPkgToken= SpaceGuid.PcdFlashMicrocodeFvOffset) +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D $(gIntelS= iliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gIntelSi= liconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + $(gSiPkgTokenSpaceGuid.= PcdFlashMicrocodeOffset) +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(gInte= lSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - $(gSiPkgTokenSpaceGu= id.PcdFlashMicrocodeOffset) SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gU= efiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress) SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $= (gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize) SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset =3D $(gSiPkg= TokenSpaceGuid.PcdFlashMicrocodeOffset) -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =3D gSiPkgT= okenSpaceGuid.PcdBiosAreaBaseAddress -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =3D gSiPkgT= okenSpaceGuid.PcdBiosSize -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D $(gSiPkgToken= SpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFl= ashFvFspTOffset) -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D $(gSiPkgToken= SpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFl= ashFvFspMOffset) -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D $(gSiPkgToken= SpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFl= ashFvFspSOffset) -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D gSiPkgT= okenSpaceGuid.PcdFlashMicrocodeFvBase -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D gSiPkgT= okenSpaceGuid.PcdFlashMicrocodeFvSize -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D gSiPkgT= okenSpaceGuid.PcdFlashMicrocodeFvOffset -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D gSiPkgT= okenSpaceGuid.PcdBiosAreaBaseAddress -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D gSiPkgT= okenSpaceGuid.PcdBiosSize +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =3D gIntelS= iliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =3D gIntelS= iliconPkgTokenSpaceGuid.PcdBiosSize +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D $(gIntelSilic= onPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpace= Guid.PcdFlashFvFspTOffset) +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D $(gIntelSilic= onPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpace= Guid.PcdFlashFvFspMOffset) +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D $(gIntelSilic= onPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpace= Guid.PcdFlashFvFspSOffset) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D gIntelS= iliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D gIntelS= iliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D gIntelS= iliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D gIntelS= iliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D gIntelS= iliconPkgTokenSpaceGuid.PcdBiosSize ########################################################################= ######## # # Following are lists of FD Region layout which correspond to the locati= ons of different @@ -155,8 +155,8 @@ [FD.TigerlakeURvp] gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesBase|gBoardModuleTo= kenSpaceGuid.PcdFlashFvFirmwareBinariesSize FV =3D FvFwBinaries =20 -gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGuid.PcdF= lashMicrocodeFvSize -gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid.PcdFla= shMicrocodeFvSize +gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gIntelSiliconPk= gTokenSpaceGuid.PcdFlashMicrocodeFvSize +gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gIntelSiliconPkgT= okenSpaceGuid.PcdFlashMicrocodeFvSize #Microcode FV =3D FvMicrocode =20 --=20 2.28.0.windows.1