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[193.106.246.138]) by smtp.gmail.com with ESMTPSA id h17sm1071346lfu.153.2021.04.16.13.43.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Apr 2021 13:43:09 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, mw@semihalf.com, jaz@semihalf.com, kostap@marvell.com, upstream@semihalf.com Subject: [edk2-non-osi PATCH] Marvell: Update device trees Date: Fri, 16 Apr 2021 22:42:26 +0200 Message-Id: <20210416204226.354914-1-mw@semihalf.com> X-Mailer: git-send-email 2.29.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable The recent device tree modifications for the platforms based on the Marvell SoCs were merged in their initial revision. Perform a desired update from the final version. Changes included: * Align DT sources to the upcoming Linux v5.12 * Revert ahci nodes changes for Armada7k8k and OcteonTx * Remove unused ICU-related defines and armada-ap807.dtsi from Armada7k8k DT sources * Enable 10G ports on Cn913xDB Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dtsi | 3 +- Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807.dtsi | 33 --------= ------------ Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap80x.dtsi | 3 ++ Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp11x.dtsi | 23 ++++++++= ------ Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807.dtsi | 4 ++- Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap80x.dtsi | 3 ++ Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11x.dtsi | 18 ++++++++= --- Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dts | 3 +- Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dts | 2 +- Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dts | 2 +- 10 files changed, 43 insertions(+), 51 deletions(-) delete mode 100644 Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807.dtsi diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dtsi b= /Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dtsi index 970e875..4935e05 100644 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dtsi +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dtsi @@ -175,7 +175,8 @@ };=0D =0D &cp0_pcie0 {=0D - compatible =3D "marvell,armada8k-pcie-ecam", "pci-host-ecam-generi= c";=0D + compatible =3D "marvell,armada8k-pcie-ecam", "snps,dw-pcie-ecam",= =0D + "pci-host-ecam-generic";=0D reg =3D <0 0xe0000000 0 0xff00000>;=0D bus-range =3D <0 0xfe>;=0D pinctrl-names =3D "default";=0D diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807.dtsi b/Sili= con/Marvell/Armada7k8k/DeviceTree/armada-ap807.dtsi deleted file mode 100644 index b42dc3a..0000000 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap807.dtsi +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT)=0D -/*=0D - * Device Tree file for Marvell Armada AP807=0D - *=0D - * Copyright (C) 2019 Marvell Technology Group Ltd.=0D - */=0D -=0D -#define AP_NAME ap807=0D -#include "armada-ap80x.dtsi"=0D -=0D -/ {=0D - model =3D "Marvell Armada AP807";=0D - compatible =3D "marvell,armada-ap807";=0D -};=0D -=0D -&ap_syscon0 {=0D - ap_clk: clock {=0D - compatible =3D "marvell,ap807-clock";=0D - #clock-cells =3D <1>;=0D - };=0D -};=0D -=0D -&ap_syscon1 {=0D - cpu_clk: clock-cpu {=0D - compatible =3D "marvell,ap807-cpu-clock";=0D - clocks =3D <&ap_clk 0>, <&ap_clk 1>;=0D - #clock-cells =3D <1>;=0D - };=0D -};=0D -=0D -&ap_sdhci0 {=0D - compatible =3D "marvell,armada-ap807-sdhci";=0D -};=0D diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap80x.dtsi b/Sili= con/Marvell/Armada7k8k/DeviceTree/armada-ap80x.dtsi index c2a7cef..805d782 100644 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap80x.dtsi +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-ap80x.dtsi @@ -290,6 +290,9 @@ gpio-controller;=0D #gpio-cells =3D <2>;=0D gpio-ranges =3D <&ap_pinctrl 0 0 2= 0>;=0D + marvell,pwm-offset =3D <0x10c0>;=0D + #pwm-cells =3D <2>;=0D + clocks =3D <&ap_clk 3>;=0D };=0D };=0D =0D diff --git a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp11x.dtsi b/Sili= con/Marvell/Armada7k8k/DeviceTree/armada-cp11x.dtsi index 7f26842..c309aaa 100644 --- a/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp11x.dtsi +++ b/Silicon/Marvell/Armada7k8k/DeviceTree/armada-cp11x.dtsi @@ -5,11 +5,6 @@ * Device Tree file for Marvell Armada CP11x.=0D */=0D =0D -#define ICU_GRP_NSR 0x0=0D -#define ICU_GRP_SR 0x1=0D -#define ICU_GRP_SEI 0x4=0D -#define ICU_GRP_REI 0x5=0D -=0D #include "armada-common.dtsi"=0D =0D #define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) += CP11X_PCIEx_MEM_SIZE(iface))=0D @@ -61,7 +56,7 @@ =0D CP11X_LABEL(ethernet): ethernet@0 {=0D compatible =3D "marvell,armada-7k-pp22";=0D - reg =3D <0x0 0x100000>, <0x129000 0xb000>;=0D + reg =3D <0x0 0x100000>, <0x129000 0xb000>, <0x2200= 00 0x800>;=0D clocks =3D <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL= (ppv2_clk)>,=0D <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL(c= ore_clk)>,=0D <&CP11X_LABEL(core_clk)>;=0D @@ -238,12 +233,17 @@ gpio-controller;=0D #gpio-cells =3D <2>;=0D gpio-ranges =3D <&CP11X_LABEL(pinctrl) 0 0= 32>;=0D + marvell,pwm-offset =3D <0x1f0>;=0D + #pwm-cells =3D <2>;=0D interrupt-controller;=0D interrupts =3D <86 IRQ_TYPE_LEVEL_HIGH>,=0D <85 IRQ_TYPE_LEVEL_HIGH>,=0D <84 IRQ_TYPE_LEVEL_HIGH>,=0D <83 IRQ_TYPE_LEVEL_HIGH>;=0D #interrupt-cells =3D <2>;=0D + clock-names =3D "core", "axi";=0D + clocks =3D <&CP11X_LABEL(slow_io_clk)>,=0D + <&CP11X_LABEL(x2core_clk)>;=0D status =3D "disabled";=0D };=0D =0D @@ -254,12 +254,17 @@ gpio-controller;=0D #gpio-cells =3D <2>;=0D gpio-ranges =3D <&CP11X_LABEL(pinctrl) 0 3= 2 31>;=0D + marvell,pwm-offset =3D <0x1f0>;=0D + #pwm-cells =3D <2>;=0D interrupt-controller;=0D interrupts =3D <82 IRQ_TYPE_LEVEL_HIGH>,=0D <81 IRQ_TYPE_LEVEL_HIGH>,=0D <80 IRQ_TYPE_LEVEL_HIGH>,=0D <79 IRQ_TYPE_LEVEL_HIGH>;=0D #interrupt-cells =3D <2>;=0D + clock-names =3D "core", "axi";=0D + clocks =3D <&CP11X_LABEL(slow_io_clk)>,=0D + <&CP11X_LABEL(x2core_clk)>;=0D status =3D "disabled";=0D };=0D };=0D @@ -304,9 +309,11 @@ };=0D =0D CP11X_LABEL(sata0): sata@540000 {=0D - compatible =3D "marvell,armada-8k-ahci";=0D + compatible =3D "marvell,armada-8k-ahci",=0D + "generic-ahci";=0D reg =3D <0x540000 0x30000>;=0D dma-coherent;=0D + interrupts =3D <107 IRQ_TYPE_LEVEL_HIGH>;=0D clocks =3D <&CP11X_LABEL(core_clk)>,=0D <&CP11X_LABEL(core_clk)>;=0D #address-cells =3D <1>;=0D @@ -314,12 +321,10 @@ status =3D "disabled";=0D =0D sata-port@0 {=0D - interrupts =3D <109 IRQ_TYPE_LEVEL_HIGH>;= =0D reg =3D <0>;=0D };=0D =0D sata-port@1 {=0D - interrupts =3D <107 IRQ_TYPE_LEVEL_HIGH>;= =0D reg =3D <1>;=0D };=0D };=0D diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807.dtsi b/Si= licon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807.dtsi index b42dc3a..0b36eb8 100644 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807.dtsi +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap807.dtsi @@ -29,5 +29,7 @@ };=0D =0D &ap_sdhci0 {=0D - compatible =3D "marvell,armada-ap807-sdhci";=0D + compatible =3D "marvell,armada-ap807-sdhci",=0D + "marvell,armada-ap806-sdhci"; /* Backward compatibili= ty */=0D };=0D +=0D diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap80x.dtsi b/Si= licon/Marvell/OcteonTx/DeviceTree/T91/armada-ap80x.dtsi index c2a7cef..805d782 100644 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap80x.dtsi +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap80x.dtsi @@ -290,6 +290,9 @@ gpio-controller;=0D #gpio-cells =3D <2>;=0D gpio-ranges =3D <&ap_pinctrl 0 0 2= 0>;=0D + marvell,pwm-offset =3D <0x10c0>;=0D + #pwm-cells =3D <2>;=0D + clocks =3D <&ap_clk 3>;=0D };=0D };=0D =0D diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11x.dtsi b/Si= licon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11x.dtsi index 05b7627..c309aaa 100644 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11x.dtsi +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp11x.dtsi @@ -56,7 +56,7 @@ =0D CP11X_LABEL(ethernet): ethernet@0 {=0D compatible =3D "marvell,armada-7k-pp22";=0D - reg =3D <0x0 0x100000>, <0x129000 0xb000>;=0D + reg =3D <0x0 0x100000>, <0x129000 0xb000>, <0x2200= 00 0x800>;=0D clocks =3D <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL= (ppv2_clk)>,=0D <&CP11X_LABEL(ppv2_clk)>, <&CP11X_LABEL(c= ore_clk)>,=0D <&CP11X_LABEL(core_clk)>;=0D @@ -233,12 +233,17 @@ gpio-controller;=0D #gpio-cells =3D <2>;=0D gpio-ranges =3D <&CP11X_LABEL(pinctrl) 0 0= 32>;=0D + marvell,pwm-offset =3D <0x1f0>;=0D + #pwm-cells =3D <2>;=0D interrupt-controller;=0D interrupts =3D <86 IRQ_TYPE_LEVEL_HIGH>,=0D <85 IRQ_TYPE_LEVEL_HIGH>,=0D <84 IRQ_TYPE_LEVEL_HIGH>,=0D <83 IRQ_TYPE_LEVEL_HIGH>;=0D #interrupt-cells =3D <2>;=0D + clock-names =3D "core", "axi";=0D + clocks =3D <&CP11X_LABEL(slow_io_clk)>,=0D + <&CP11X_LABEL(x2core_clk)>;=0D status =3D "disabled";=0D };=0D =0D @@ -249,12 +254,17 @@ gpio-controller;=0D #gpio-cells =3D <2>;=0D gpio-ranges =3D <&CP11X_LABEL(pinctrl) 0 3= 2 31>;=0D + marvell,pwm-offset =3D <0x1f0>;=0D + #pwm-cells =3D <2>;=0D interrupt-controller;=0D interrupts =3D <82 IRQ_TYPE_LEVEL_HIGH>,=0D <81 IRQ_TYPE_LEVEL_HIGH>,=0D <80 IRQ_TYPE_LEVEL_HIGH>,=0D <79 IRQ_TYPE_LEVEL_HIGH>;=0D #interrupt-cells =3D <2>;=0D + clock-names =3D "core", "axi";=0D + clocks =3D <&CP11X_LABEL(slow_io_clk)>,=0D + <&CP11X_LABEL(x2core_clk)>;=0D status =3D "disabled";=0D };=0D };=0D @@ -299,9 +309,11 @@ };=0D =0D CP11X_LABEL(sata0): sata@540000 {=0D - compatible =3D "marvell,armada-8k-ahci";=0D + compatible =3D "marvell,armada-8k-ahci",=0D + "generic-ahci";=0D reg =3D <0x540000 0x30000>;=0D dma-coherent;=0D + interrupts =3D <107 IRQ_TYPE_LEVEL_HIGH>;=0D clocks =3D <&CP11X_LABEL(core_clk)>,=0D <&CP11X_LABEL(core_clk)>;=0D #address-cells =3D <1>;=0D @@ -309,12 +321,10 @@ status =3D "disabled";=0D =0D sata-port@0 {=0D - interrupts =3D <109 IRQ_TYPE_LEVEL_HIGH>;= =0D reg =3D <0>;=0D };=0D =0D sata-port@1 {=0D - interrupts =3D <107 IRQ_TYPE_LEVEL_HIGH>;= =0D reg =3D <1>;=0D };=0D };=0D diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dts b/Silico= n/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dts index 747bf88..7f54f36 100644 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dts +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dts @@ -127,7 +127,7 @@ =0D /* SLM-1521-V2, CON9 */=0D &cp0_eth0 {=0D - status =3D "disabled";=0D + status =3D "okay";=0D phy-mode =3D "10gbase-kr";=0D /* Generic PHY, providing serdes lanes */=0D phys =3D <&cp0_comphy4 0>;=0D @@ -306,6 +306,7 @@ =0D /* U55 */=0D &cp0_spi1 {=0D + status =3D "disabled";=0D pinctrl-names =3D "default";=0D pinctrl-0 =3D <&cp0_spi0_pins>;=0D reg =3D <0x700680 0x50>;=0D diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dts b/Silico= n/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dts index a321810..3d5a67e 100644 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dts +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dts @@ -85,7 +85,7 @@ =0D /* CON50 */=0D &cp1_eth0 {=0D - status =3D "disabled";=0D + status =3D "okay";=0D phy-mode =3D "10gbase-kr";=0D /* Generic PHY, providing serdes lanes */=0D phys =3D <&cp1_comphy4 0>;=0D diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dts b/Silico= n/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dts index 8cb08ca..81ff188 100644 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dts +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dts @@ -103,7 +103,7 @@ =0D /* SLM-1521-V2, CON9 */=0D &cp2_eth0 {=0D - status =3D "disabled";=0D + status =3D "okay";=0D phy-mode =3D "10gbase-kr";=0D /* Generic PHY, providing serdes lanes */=0D phys =3D <&cp2_comphy4 0>;=0D --=20 2.29.0