From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-lf1-f45.google.com (mail-lf1-f45.google.com [209.85.167.45]) by mx.groups.io with SMTP id smtpd.web10.2797.1618607096106220462 for ; Fri, 16 Apr 2021 14:04:56 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=xmjPlTH4; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.167.45, mailfrom: mw@semihalf.com) Received: by mail-lf1-f45.google.com with SMTP id j18so46834659lfg.5 for ; Fri, 16 Apr 2021 14:04:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dgwWMy9BwPfxNq0FRCoaSDXaieW6oi2hURXt0wbLdiI=; b=xmjPlTH4UWdUK3hO8Xx5QWM3McURcSk/W1JXvou/MpDnnDqr2DSNLl0ESw2Q4qbdMv 4an0r9zK5TQSnvY9j1kmHi6LTV9XKNqBV12teS6DwVxb+wkkYyLzw+Szln/2fhWneGqu eqmfYQdypUxIU1eGwNqyQyuGI7DRDZOePGWBBMlgzsGV4wJOIy9+sGHWUagI7TTjEVLt 7cX81222O/AEmaW8w6UP9b7ViPC311g8t74lGugqWmWuDB8B0EKi8wIlfttYCuPpY2kn XN12oVNZJwCf/hfNhV68SiVj+xxtgAPd3Iz2d9op2r6iV+k6PkJkZuMw+659WxywbNXO ubRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dgwWMy9BwPfxNq0FRCoaSDXaieW6oi2hURXt0wbLdiI=; b=n9XiAY7jFMiLbMFtNMhc85oGhSYrLGLS00jFcCPcGLiOeno4ME2W08upqvM3Oqsrnj aHGkU/aGQV8S0ISZqfdrp3wYdVZzJgKbvuVKSEw+vF8q37cXCgamov9jZ3gBKfyyiwXr iEssOgajBzC+MO2lKFn609/plTIYN1MAF+KcyD2CTq14T7WhpV9x/uyUVNZPc8NE06pX z7WzlvvzcvPrxnMumql8l1DF53WMdcZ3KEctu4jTGFce1TnqkMxyIIWDgFlLDwKTM8wX lfvSPhAv0ShSXDvfGS7NOM2p6GZFzvOYALD39JR7fE5pWRHBj++mv+xE03b9ru6fjsQx LdVQ== X-Gm-Message-State: AOAM530V2xNuNsKU/+7sYKgYml+RVnxQgukeSC4+h3kYSD4LYZ2x10bk pspUKzZ+6l/eaZgSAx6eVOODZYdbOMr/GA== X-Google-Smtp-Source: ABdhPJwvRc/4AtDRyCYdd1tKI4vN7mLMxQr/SN22sDaZ3r5J1FRf1SCkjowOkQyHYXi3u1KmTEEzSA== X-Received: by 2002:a19:c38c:: with SMTP id t134mr4300214lff.29.1618606472405; Fri, 16 Apr 2021 13:54:32 -0700 (PDT) Return-Path: Received: from gilgamesh.semihalf.com (host-193.106.246.138.static.3s.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id k42sm1075161lfv.294.2021.04.16.13.54.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Apr 2021 13:54:31 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, mw@semihalf.com, jaz@semihalf.com, kostap@marvell.com, upstream@semihalf.com Subject: [edk2-platforms PATCH 4/4] Marvell/Cn9132Db: Enable ACPI support Date: Fri, 16 Apr 2021 22:54:14 +0200 Message-Id: <20210416205414.355203-5-mw@semihalf.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210416205414.355203-1-mw@semihalf.com> References: <20210416205414.355203-1-mw@semihalf.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Because of the limitation in a number of available intterrupts that can be mapped in a current version of the IcuLib, the ACPI support for Cn9132 variant remained disabled. Such hard limitation is not needed though and enable ACPI boot, however with a the interfaces present only on the first two CP115 HW blocks. Signed-off-by: Marcin Wojtas --- Platform/Marvell/Cn913xDb/Cn913xDbA.dsc | 2 ++ Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc | 6 ++++-- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc b/Platform/Marvell/Cn9= 13xDb/Cn913xDbA.dsc index 67355f3988..ff91d10142 100644 --- a/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc +++ b/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc @@ -54,6 +54,8 @@ !ifndef $(CN9132)=0D [Components.AARCH64]=0D Silicon/Marvell/OcteonTx/AcpiTables/T91/$(PLATFORM_NAME).inf=0D +!else=0D + Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf=0D !endif=0D =0D [LibraryClasses.common]=0D diff --git a/Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc b/Platform/Marvell= /Cn913xDb/Cn913xDbA.fdf.inc index 78bdb79bed..c2fb71fa8c 100644 --- a/Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc +++ b/Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc @@ -12,9 +12,11 @@ # DTB=0D INF RuleOverride =3D DTB Silicon/Marvell/OcteonTx/DeviceTree/T91/$(PLATF= ORM_NAME).inf=0D =0D -!ifndef $(CN9132)=0D -!if $(ARCH) =3D=3D AARCH64=0D # ACPI support=0D +!if $(ARCH) =3D=3D AARCH64=0D +!ifndef $(CN9132)=0D INF RuleOverride =3D ACPITABLE Silicon/Marvell/OcteonTx/AcpiTables/T91/$= (PLATFORM_NAME).inf=0D +!else=0D + INF RuleOverride =3D ACPITABLE Silicon/Marvell/OcteonTx/AcpiTables/T91/C= n9131DbA.inf=0D !endif=0D !endif=0D --=20 2.29.0