From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-ej1-f44.google.com (mail-ej1-f44.google.com [209.85.218.44]) by mx.groups.io with SMTP id smtpd.web08.6350.1618822171544058045 for ; Mon, 19 Apr 2021 01:49:31 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=Xe0ocfGt; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.218.44, mailfrom: mw@semihalf.com) Received: by mail-ej1-f44.google.com with SMTP id v6so50357049ejo.6 for ; Mon, 19 Apr 2021 01:49:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SNgr7yJg3WgvUvATxR4lMU+BzFRCpUIUpajUpIrLGvo=; b=Xe0ocfGtqivaNVewqRo2cFwqdF+IZV/LWYGKEoK0l5i/+h6qbgSuI6yJAqH0Cug9qu NyUITfdkPrqtHAwKDzOHhLTD3ZEdhkg/36iitGM+ap3HKt6cYB3njFx1Fcgyci4/6LaE 1oTDwnrSvnfUCZ+BLpxlSTSKVpWxEtf8HXhFoYNItojXtCjLRE1q2xlsXlo/C2xTwkhX TloKLLS3dw5D4S2dgQyr53LeNn8jl3kUJM3b6B3D8l8tYewun26agJpvAcf7KVsmrdj7 8D4gJBmWgOZXhuiq5PaE1YXtuNARwHjvAOkCI1oWcY+zIWLZy9xdzl+hOklbp8BnZ8Nj NXEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SNgr7yJg3WgvUvATxR4lMU+BzFRCpUIUpajUpIrLGvo=; b=FFlaR4X3ooTBPGKX4AAjZCX697sLE6Tx3SHbxfTAqGR67IIpvKfvHr/Ge6gHxUxmp+ aCSjyCc84ZqAqmyJoF2h8qDqPFWsUBAqGkYSM6REVJxzmfXii1/PmND1Etxoim2SSDCY d6J3gipQHwcIkd3Sr3hKF73CSc4b+zTprwxqNoMWCJx3c99qhMLRFFywvfACTpFbIW1T /uvOsW0fk3Ry5maq2ZukYBOdh1juJRr+oE47V7ZAk4dayJxoAcdNHbWAwkZ98TQNkufe P1VKDvQ3pEhvyjrzhzykwK02lMy3TKwPU/fMPov1GFYldQipciEbnBJ21K5W0D1RRhNK umTw== X-Gm-Message-State: AOAM531MZxSUJjIkvsJvLCawy43/fr7YkuMCcp2Cj87HljuQg/n3VJhJ GYR22PsNEUVoXjxIPGw7P/m7GMu4y5Jbig== X-Google-Smtp-Source: ABdhPJx1fykA3KZjK1iF+yBKwWmPDkCtJTEg780JOGGGvKg+a9eF4J3lwA8fiwZGaoK/M5PJPZa5zw== X-Received: by 2002:a17:906:7f0e:: with SMTP id d14mr20462747ejr.487.1618822170144; Mon, 19 Apr 2021 01:49:30 -0700 (PDT) Return-Path: Received: from gilgamesh.semihalf.com (host-193.106.246.138.static.3s.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id z17sm12351102edx.36.2021.04.19.01.49.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 01:49:29 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, mw@semihalf.com, jaz@semihalf.com, kostap@marvell.com, upstream@semihalf.com Subject: [edk2-platforms PATCH 2/6] Marvell/Armada80x0Db: Introduce SD/MMC ACPI description Date: Mon, 19 Apr 2021 10:48:57 +0200 Message-Id: <20210419084901.380576-3-mw@semihalf.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210419084901.380576-1-mw@semihalf.com> References: <20210419084901.380576-1-mw@semihalf.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable This patch adds a new description of the board's SD/MMC interfaces in DSDT table that can work with the newly introduced support in Linux. Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl | 59 +++++++++= +++++++++++ 1 file changed, 59 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl b/= Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl index faf1846c22..62ba62c7d2 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl @@ -87,6 +87,65 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMAD= A8K", 3) })=0D }=0D =0D + Device (MMC0)=0D + {=0D + Name (_HID, "MRVL0002") // _HID: Hardware ID=0D + Name (_UID, 0x00) // _UID: Unique ID=0D + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D +=0D + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D + {=0D + Memory32Fixed (ReadWrite,=0D + 0xF06E0000, // Address Base (MMIO)=0D + 0x00000300, // Address Length=0D + )=0D + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, )=0D + {=0D + 48=0D + }=0D + })=0D + Name (_DSD, Package () {=0D + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D + Package () {=0D + Package () { "clock-frequency", 400000000 },=0D + Package () { "bus-width", 8 },=0D + Package () { "marvell,xenon-phy-slow-mode", 0x1 },=0D + Package () { "no-sd", 0x1 },=0D + Package () { "no-sdio", 0x1 },=0D + Package () { "non-removable", 0x1 },=0D + }=0D + })=0D + }=0D +=0D + Device (MMC1)=0D + {=0D + Name (_HID, "MRVL0004") // _HID: Hardware ID=0D + Name (_UID, 0x01) // _UID: Unique ID=0D + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D +=0D + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D + {=0D + Memory32Fixed (ReadWrite,=0D + 0xF2780000, // Address Base (MMIO)=0D + 0x00000300, // Address Length=0D + )=0D + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, )=0D + {=0D + CP_GIC_SPI_CP0_SDMMC=0D + }=0D + })=0D + Name (_DSD, Package () {=0D + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D + Package () {=0D + Package () { "clock-frequency", 400000000 },=0D + Package () { "bus-width", 4 },=0D + Package () { "no-sd", 0x1 },=0D + Package () { "no-sdio", 0x1 },=0D + Package () { "non-removable", 0x1 },=0D + }=0D + })=0D + }=0D +=0D Device (XHC0)=0D {=0D Name (_HID, "PNP0D10") // _HID: Hardware ID=0D --=20 2.29.0