From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-ej1-f48.google.com (mail-ej1-f48.google.com [209.85.218.48]) by mx.groups.io with SMTP id smtpd.web11.6213.1618822172494606860 for ; Mon, 19 Apr 2021 01:49:32 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=R7+jzrIb; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.218.48, mailfrom: mw@semihalf.com) Received: by mail-ej1-f48.google.com with SMTP id g5so44938723ejx.0 for ; Mon, 19 Apr 2021 01:49:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yqP4Bxrx67FeDWaOq/78Vn44siO3TbtDsnNY8MH3kak=; b=R7+jzrIbHLqkRrgq0MNwI5b8fPYgKr+kVlieD7CCPdtXyaXEMUYXYYGhJxgrQrbdkt IBO+oJl0Qz9FSxXo+GuvjVGhHuYfiS2F5RhysQ6Mg6H6xqPdGBDIEUQqQXkLeQVabMB9 u/yiD8TNwwBySy0xtcfjPfqiy88hTxzl6wG/dDzNx+aJ6NIiZfQh3q2TGZ0vMZ4nK5rh PsCSuxNUuDrrod6i8HILu5I5yfGi0TkpSwLBDEx2wv7jGu8iYZVWgPJcaS3md93tTrm8 1ifjkiVLE7s9X3bF8pADaHnfmR6CyshuvBWbzWhr0UkSiCXem7/q1oGV89GNtgNS0oUj T80A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yqP4Bxrx67FeDWaOq/78Vn44siO3TbtDsnNY8MH3kak=; b=sNAsMGN/5/LPxkkmgFISaL04qkVTwnxtQfkjEB+GaafkDL1jdT5Ns8d7GWzo+pIpqS SSWD8cy5m4kuVLDLqoEh06uc5g5Ls4qBgjuQyGnFLsO3mpO+eo5+vhEqS6h+wv8r4tg+ oZj2I//sx9BjWi6KO3T+WudhtnMOo1ZwwfukYY67fUwPN3u+sDFrfjoksHaJAkIR8yTF /3o7eROtf/MA5GxXnMIM72m/eV+dzuLiCusiWqpthPuV6pi+hP1ucHjky7+WRuBAs6ON 9y8CsawR+AUFsu56NfTSCUDPSfwUhw2I1qD+/ENbHzhP1nedodwoLadDDinGcCTjNYY0 Ciww== X-Gm-Message-State: AOAM531MxphwMgeR8YkHr6SA6fyPg9ZEGB3aMJGclm1rjKzEqL2Euhy/ VWZ5PzSlTA3c8uW0pHL8cYVKXAaLq6t20g== X-Google-Smtp-Source: ABdhPJzoAecJV/bo1REdvZL0TgzPtnxHPv3HsUKluk2JjSrFIyzZGMAIP3C0NM0j7U2ddFW7fjwiqA== X-Received: by 2002:a17:907:210a:: with SMTP id qn10mr21535634ejb.414.1618822171032; Mon, 19 Apr 2021 01:49:31 -0700 (PDT) Return-Path: Received: from gilgamesh.semihalf.com (host-193.106.246.138.static.3s.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id z17sm12351102edx.36.2021.04.19.01.49.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 01:49:30 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, mw@semihalf.com, jaz@semihalf.com, kostap@marvell.com, upstream@semihalf.com Subject: [edk2-platforms PATCH 3/6] Marvell/Armada70x0Db: Update CP0 MMC settings Date: Mon, 19 Apr 2021 10:48:58 +0200 Message-Id: <20210419084901.380576-4-mw@semihalf.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210419084901.380576-1-mw@semihalf.com> References: <20210419084901.380576-1-mw@semihalf.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable This patch enables switching to 1.8V power supply on the VCCQ rail of the CP0 MMC interface, which allows to operate at HS200 in EDK2 and when booting with ACPI. Signed-off-by: Marcin Wojtas --- Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/NonDiscoverableInitLi= b.h | 1 + Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0DbBoardDe= scLib.c | 2 +- Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/NonDiscoverableInitLi= b.c | 79 +++++++++++++++----- 3 files changed, 61 insertions(+), 21 deletions(-) diff --git a/Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/NonDiscov= erableInitLib.h b/Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/NonD= iscoverableInitLib.h index 73a71ad3c4..85af61ec3f 100644 --- a/Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/NonDiscoverableI= nitLib.h +++ b/Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/NonDiscoverableI= nitLib.h @@ -13,5 +13,6 @@ #define ARMADA_70x0_DB_VBUS0_LIMIT_PIN 4=0D #define ARMADA_70x0_DB_VBUS1_PIN 1=0D #define ARMADA_70x0_DB_VBUS1_LIMIT_PIN 5=0D +#define ARMADA_70x0_DB_SDMMC_CP0_VCCQ_PIN 15=0D =0D #endif=0D diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada7= 0x0DbBoardDescLib.c b/Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLi= b/Armada70x0DbBoardDescLib.c index ae13e0a845..b0b6855bbb 100644 --- a/Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0DbBo= ardDescLib.c +++ b/Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0DbBo= ardDescLib.c @@ -104,7 +104,7 @@ MV_BOARD_SDMMC_DESC mSdMmcDescTemplate[] =3D { { /* SD/MMC 0xF2780000 */=0D 0, /* SOC will be filled by MvBoardDescDxe */=0D 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */=0D - FALSE, /* Xenon1v8Enabled */=0D + TRUE, /* Xenon1v8Enabled */=0D FALSE, /* Xenon8BitBusEnabled */=0D FALSE, /* XenonSlowModeEnabled */=0D 0x19, /* XenonTuningStepDivisor */=0D diff --git a/Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/NonDiscov= erableInitLib.c b/Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/NonD= iscoverableInitLib.c index 92a14bb4f0..4d790103a4 100644 --- a/Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/NonDiscoverableI= nitLib.c +++ b/Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/NonDiscoverableI= nitLib.c @@ -21,6 +21,37 @@ =0D #include "NonDiscoverableInitLib.h"=0D =0D +STATIC=0D +EFI_STATUS=0D +EFIAPI=0D +ConfigurePins (=0D + IN CONST MV_GPIO_PIN *VbusPin,=0D + IN UINTN PinCount,=0D + IN MV_GPIO_DRIVER_TYPE DriverType=0D + )=0D +{=0D + EMBEDDED_GPIO_MODE Mode;=0D + EMBEDDED_GPIO_PIN Gpio;=0D + EMBEDDED_GPIO *GpioProtocol;=0D + EFI_STATUS Status;=0D + UINTN Index;=0D +=0D + Status =3D MvGpioGetProtocol (DriverType, &GpioProtocol);=0D + if (EFI_ERROR (Status)) {=0D + DEBUG ((DEBUG_ERROR, "%a: Unable to find GPIO protocol\n", __FUNCTION_= _));=0D + return Status;=0D + }=0D +=0D + for (Index =3D 0; Index < PinCount; Index++) {=0D + Mode =3D VbusPin->ActiveHigh ? GPIO_MODE_OUTPUT_1 : GPIO_MODE_OUTPUT_0= ;=0D + Gpio =3D GPIO (VbusPin->ControllerId, VbusPin->PinNumber);=0D + GpioProtocol->Set (GpioProtocol, Gpio, Mode);=0D + VbusPin++;=0D + }=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D STATIC CONST MV_GPIO_PIN mXhciVbusPins[] =3D {=0D {=0D MV_GPIO_DRIVER_TYPE_PCA95XX,=0D @@ -55,28 +86,30 @@ XhciInit ( IN NON_DISCOVERABLE_DEVICE *This=0D )=0D {=0D - CONST MV_GPIO_PIN *VbusPin;=0D - EMBEDDED_GPIO_MODE Mode;=0D - EMBEDDED_GPIO_PIN Gpio;=0D - EMBEDDED_GPIO *GpioProtocol;=0D - EFI_STATUS Status;=0D - UINTN Index;=0D -=0D - Status =3D MvGpioGetProtocol (MV_GPIO_DRIVER_TYPE_PCA95XX, &GpioProtocol= );=0D - if (EFI_ERROR (Status)) {=0D - DEBUG ((DEBUG_ERROR, "%a: Unable to find GPIO protocol\n", __FUNCTION_= _));=0D - return Status;=0D - }=0D + return ConfigurePins (mXhciVbusPins,=0D + ARRAY_SIZE (mXhciVbusPins),=0D + MV_GPIO_DRIVER_TYPE_PCA95XX);=0D +}=0D =0D - VbusPin =3D mXhciVbusPins;=0D - for (Index =3D 0; Index < ARRAY_SIZE (mXhciVbusPins); Index++) {=0D - Mode =3D VbusPin->ActiveHigh ? GPIO_MODE_OUTPUT_1 : GPIO_MODE_OUTPUT_0= ;=0D - Gpio =3D GPIO (VbusPin->ControllerId, VbusPin->PinNumber);=0D - GpioProtocol->Set (GpioProtocol, Gpio, Mode);=0D - VbusPin++;=0D - }=0D +STATIC CONST MV_GPIO_PIN mCp0SdMmcPins[] =3D {=0D + {=0D + MV_GPIO_DRIVER_TYPE_PCA95XX,=0D + ARMADA_70x0_DB_IO_EXPANDER0,=0D + ARMADA_70x0_DB_SDMMC_CP0_VCCQ_PIN,=0D + TRUE,=0D + },=0D +};=0D =0D - return EFI_SUCCESS;=0D +STATIC=0D +EFI_STATUS=0D +EFIAPI=0D +Cp0SdMmcInit (=0D + IN NON_DISCOVERABLE_DEVICE *This=0D + )=0D +{=0D + return ConfigurePins (mCp0SdMmcPins,=0D + ARRAY_SIZE (mCp0SdMmcPins),=0D + MV_GPIO_DRIVER_TYPE_PCA95XX);=0D }=0D =0D NON_DISCOVERABLE_DEVICE_INIT=0D @@ -90,5 +123,11 @@ NonDiscoverableDeviceInitializerGet ( return XhciInit;=0D }=0D =0D + if (Type =3D=3D NonDiscoverableDeviceTypeSdhci) {=0D + switch (Index) {=0D + case 1:=0D + return Cp0SdMmcInit;=0D + }=0D + }=0D return NULL;=0D }=0D --=20 2.29.0