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[193.106.246.138]) by smtp.gmail.com with ESMTPSA id z17sm12351102edx.36.2021.04.19.01.49.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 01:49:32 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, mw@semihalf.com, jaz@semihalf.com, kostap@marvell.com, upstream@semihalf.com Subject: [edk2-platforms PATCH 5/6] Marvell/Cn913xDb: Update AP807 MMC settings Date: Mon, 19 Apr 2021 10:49:00 +0200 Message-Id: <20210419084901.380576-6-mw@semihalf.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210419084901.380576-1-mw@semihalf.com> References: <20210419084901.380576-1-mw@semihalf.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable This patch enables switching to 1.8V power supply on the VCCQ rail of the AP807 MMC interface, which allows to operate at HS400 when booting with ACPI. Since there are issues with this mode in EDK2 Xenon SD/MMC driver apply a workaround, that limits the mode to HS200 by forcing bus width to 4. Signed-off-by: Marcin Wojtas --- Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h = | 1 + Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c = | 8 +++++-- Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c = | 23 ++++++++++++++++++++ 3 files changed, 30 insertions(+), 2 deletions(-) diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverab= leInitLib.h b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscovera= bleInitLib.h index a641420ef7..00449d4390 100644 --- a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitL= ib.h +++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitL= ib.h @@ -13,6 +13,7 @@ #define CN9130_DB_VBUS0_LIMIT_PIN 4=0D #define CN9130_DB_VBUS1_PIN 1=0D #define CN9130_DB_VBUS1_LIMIT_PIN 5=0D +#define CN9130_DB_AP_MMC_VCCQ_PIN 8=0D #define CN9130_DB_SDMMC_VCC_PIN 14=0D #define CN9130_DB_SDMMC_VCCQ_PIN 15=0D #define CN9131_DB_VBUS0_PIN 3=0D diff --git a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDe= scLib.c b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescL= ib.c index 2b46d141cd..2755600f53 100644 --- a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c +++ b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c @@ -95,8 +95,12 @@ MV_BOARD_SDMMC_DESC mSdMmcDescTemplate[] =3D { { /* eMMC 0xF06E0000 */=0D 0, /* SOC will be filled by MvBoardDescDxe */=0D 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */=0D - FALSE, /* Xenon1v8Enabled */=0D - TRUE, /* Xenon8BitBusEnabled */=0D + TRUE, /* Xenon1v8Enabled */=0D + /*=0D + * Force 4-bit bus width - work-around for non=0D + * functional HS400 mode.=0D + */=0D + FALSE, /* Xenon8BitBusEnabled */=0D FALSE, /* XenonSlowModeEnabled */=0D 0x40, /* XenonTuningStepDivisor */=0D EmbeddedSlot /* SlotType */=0D diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverab= leInitLib.c b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscovera= bleInitLib.c index 42dc54a892..965d8efe57 100644 --- a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitL= ib.c +++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitL= ib.c @@ -157,6 +157,27 @@ Cp2XhciInit ( MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER);=0D }=0D =0D +STATIC CONST MV_GPIO_PIN mApSdMmcPins[] =3D {=0D + {=0D + MV_GPIO_DRIVER_TYPE_PCA95XX,=0D + CN9130_DB_IO_EXPANDER0,=0D + CN9130_DB_AP_MMC_VCCQ_PIN,=0D + TRUE,=0D + },=0D +};=0D +=0D +STATIC=0D +EFI_STATUS=0D +EFIAPI=0D +ApSdMmcInit (=0D + IN NON_DISCOVERABLE_DEVICE *This=0D + )=0D +{=0D + return ConfigurePins (mApSdMmcPins,=0D + ARRAY_SIZE (mApSdMmcPins),=0D + MV_GPIO_DRIVER_TYPE_PCA95XX);=0D +}=0D +=0D STATIC CONST MV_GPIO_PIN mCp0SdMmcPins[] =3D {=0D {=0D MV_GPIO_DRIVER_TYPE_PCA95XX,=0D @@ -206,6 +227,8 @@ NonDiscoverableDeviceInitializerGet ( =0D if (Type =3D=3D NonDiscoverableDeviceTypeSdhci) {=0D switch (Index) {=0D + case 0:=0D + return ApSdMmcInit;=0D case 1:=0D return Cp0SdMmcInit;=0D }=0D --=20 2.29.0