From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mx.groups.io with SMTP id smtpd.web12.2236.1619361706641437487 for ; Sun, 25 Apr 2021 07:41:47 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.88, mailfrom: yun.lou@intel.com) IronPort-SDR: dCc++20fdYt6CfChwrVtBqJ4W9kH6IbU40XRGdTxHKzzJ8K2QgsU6pqH17vQ8L/8PN+89/T7G5 XABmVb1KPq2g== X-IronPort-AV: E=McAfee;i="6200,9189,9965"; a="216931738" X-IronPort-AV: E=Sophos;i="5.82,250,1613462400"; d="scan'208";a="216931738" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Apr 2021 07:41:46 -0700 IronPort-SDR: cUzQdkrsNqYWK3+AFd3QOBD525liBgo/wxjkV8HMnEKwNuNo6B72ZF+wF+duhhXJJFKAbulmbN 2mOsXdCdh34A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,250,1613462400"; d="scan'208";a="429053654" Received: from shwdeopenlab102.ccr.corp.intel.com ([10.239.183.74]) by orsmga008.jf.intel.com with ESMTP; 25 Apr 2021 07:41:43 -0700 From: "Jason Lou" To: devel@edk2.groups.io Cc: Jason Lou , Chasel Chiu , Nate DeSimone , Star Zeng , Ray Ni Subject: [PATCH v1] Intel/KabylakeOpenBoardPkg: Simplify microcode related PCD usage Date: Sun, 25 Apr 2021 22:41:35 +0800 Message-Id: <20210425144137.16411-2-yun.lou@intel.com> X-Mailer: git-send-email 2.28.0.windows.1 In-Reply-To: <20210425144137.16411-1-yun.lou@intel.com> References: <20210425144137.16411-1-yun.lou@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Jason Lou REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3334 There are following PCDs in IntelFsp2WrapperPkg for microcode location: * IntelFsp2WrapperPkg: PcdCpuMicrocodePatchAddress PcdCpuMicrocodePatchRegionSize PcdFlashMicrocodeOffset The change simplify the platform code to use following PCDs instead: * MinPlatformPkg PcdFlashFvMicrocodeOffset PcdFlashFvMicrocodeBase =3D $(BIOS_BASE) + PcdFlashFvMicrocodeOffset PcdFlashFvMicrocodeSize PcdMicrocodeOffsetInFv Signed-off-by: Jason Lou Cc: Chasel Chiu Cc: Nate DeSimone Cc: Star Zeng Cc: Ray Ni --- Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf | 6 ++--= -- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf | 6 ++--= -- 2 files changed, 4 insertions(+), 8 deletions(-) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fd= f b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf index 196f04c68d..bcd1ade72b 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf @@ -1,7 +1,7 @@ ## @file=0D # System 76 GalagoPro3 board flash file.=0D #=0D -# Copyright (c) 2019, Intel Corporation. All rights reserved.
=0D +# Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.
=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -45,9 +45,7 @@ SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D $(gS= iPkgTokenSpaceGuid.PcdFla SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D $(gSiPkgTokenSpaceGui= d.PcdFlashMicrocodeFvSize)=0D SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gSiPkgToke= nSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60=0D SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(gSiPkgT= okenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60=0D -SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gSiP= kgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlash= MicrocodeFvOffset)=0D -SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(g= SiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)=0D -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset =3D 0x60=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv =3D 0x60=0D SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D gSiPkgTok= enSpaceGuid.PcdFlashMicrocodeFvBase=0D SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D gSiPkgTok= enSpaceGuid.PcdFlashMicrocodeFvSize=0D SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D gSiPkgTok= enSpaceGuid.PcdFlashMicrocodeFvOffset=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.= fdf b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf index f2cfff1c7b..6cdf4e2f9f 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf @@ -1,7 +1,7 @@ ## @file=0D # FDF file of Platform.=0D #=0D -# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D +# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -45,9 +45,7 @@ SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D $(gS= iPkgTokenSpaceGuid.PcdFla SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D $(gSiPkgTokenSpaceGui= d.PcdFlashMicrocodeFvSize)=0D SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gSiPkgToke= nSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60=0D SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(gSiPkgT= okenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60=0D -SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gSiP= kgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlash= MicrocodeFvOffset)=0D -SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(g= SiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)=0D -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset =3D 0x60=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv =3D 0x60=0D SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D gSiPkgTok= enSpaceGuid.PcdFlashMicrocodeFvBase=0D SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D gSiPkgTok= enSpaceGuid.PcdFlashMicrocodeFvSize=0D SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D gSiPkgTok= enSpaceGuid.PcdFlashMicrocodeFvOffset=0D --=20 2.28.0.windows.1