From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga01.intel.com (mga01.intel.com []) by mx.groups.io with SMTP id smtpd.web11.2187.1619361707983443525 for ; Sun, 25 Apr 2021 07:41:50 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: yun.lou@intel.com) IronPort-SDR: 0PRk/jS5kcCh9N1yedbm6aAZ+M+GFzWAaLL2JGUVohFSpzE/mzzgEca7B+yF2BeSi1A107IV0E qYHW8jIxjlhw== X-IronPort-AV: E=McAfee;i="6200,9189,9965"; a="216931747" X-IronPort-AV: E=Sophos;i="5.82,250,1613462400"; d="scan'208";a="216931747" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Apr 2021 07:41:49 -0700 IronPort-SDR: U5FEbwVhrsO4TFv1BcOnPC20Zi9Qq+NiOerHUFhByjLJEVMr1F3bVYyVkd96r1s63zLx3setOX OYQPgZaQGiPA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,250,1613462400"; d="scan'208";a="429053667" Received: from shwdeopenlab102.ccr.corp.intel.com ([10.239.183.74]) by orsmga008.jf.intel.com with ESMTP; 25 Apr 2021 07:41:47 -0700 From: "Jason Lou" To: devel@edk2.groups.io Cc: Jason Lou , Chasel Chiu , Nate DeSimone , Star Zeng , Ray Ni Subject: [PATCH v1] Intel/WhiskeylakeOpenBoardPkg: Simplify microcode related PCD usage Date: Sun, 25 Apr 2021 22:41:37 +0800 Message-Id: <20210425144137.16411-4-yun.lou@intel.com> X-Mailer: git-send-email 2.28.0.windows.1 In-Reply-To: <20210425144137.16411-1-yun.lou@intel.com> References: <20210425144137.16411-1-yun.lou@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Jason Lou REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3334 There are following PCDs in IntelFsp2WrapperPkg for microcode location: * IntelFsp2WrapperPkg: PcdCpuMicrocodePatchAddress PcdCpuMicrocodePatchRegionSize PcdFlashMicrocodeOffset The change simplify the platform code to use following PCDs instead: * MinPlatformPkg PcdFlashFvMicrocodeOffset PcdFlashFvMicrocodeBase =3D $(BIOS_BASE) + PcdFlashFvMicrocodeOffset PcdFlashFvMicrocodeSize PcdMicrocodeOffsetInFv Signed-off-by: Jason Lou Cc: Chasel Chiu Cc: Nate DeSimone Cc: Star Zeng Cc: Ray Ni --- Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspW= rapperPlatformSecLib/SecRamInitData.c | 6 +++--- Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspW= rapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf | 8 ++++---- Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf = | 6 ++---- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.fdf = | 6 ++---- 4 files changed, 11 insertions(+), 15 deletions(-) diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Lib= rary/SecFspWrapperPlatformSecLib/SecRamInitData.c b/Platform/Intel/Whiskeyl= akeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/Sec= RamInitData.c index 8442e5fbff..41a37f5da5 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Se= cFspWrapperPlatformSecLib/SecRamInitData.c +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Se= cFspWrapperPlatformSecLib/SecRamInitData.c @@ -1,7 +1,7 @@ /** @file=0D Provide TempRamInitParams data.=0D =0D -Copyright (c) 2020, Intel Corporation. All rights reserved.
=0D +Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D **/=0D @@ -24,8 +24,8 @@ GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD FsptUpdDataP= tr =3D { },=0D // FSPT_CORE_UPD=0D {=0D - ((UINT32) FixedPcdGet64 (PcdCpuMicrocodePatchAddress) + FixedPcdGet32 = (PcdFlashMicrocodeOffset)),=0D - ((UINT32) FixedPcdGet64 (PcdCpuMicrocodePatchRegionSize) - FixedPcdGet= 32 (PcdFlashMicrocodeOffset)),=0D + FixedPcdGet32 (PcdFlashFvMicrocodeBase) + FixedPcdGet32 (PcdMicrocodeO= ffsetInFv),=0D + FixedPcdGet32 (PcdFlashFvMicrocodeSize) - FixedPcdGet32 (PcdMicrocodeO= ffsetInFv),=0D 0, // Set CodeRegionBase as 0, so that caching will be 4GB-(C= odeRegionSize > LLCSize ? LLCSize : CodeRegionSize) will be used.=0D FixedPcdGet32 (PcdFlashCodeCacheSize),=0D { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,=0D diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Lib= rary/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf b/Platform= /Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPla= tformSecLib/SecFspWrapperPlatformSecLib.inf index b17226d43b..e7319cf9e7 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Se= cFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Se= cFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf @@ -1,7 +1,7 @@ ## @file=0D # Provide FSP wrapper platform sec related function.=0D #=0D -# Copyright (c) 2020, Intel Corporation. All rights reserved.
=0D +# Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
= =0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -92,9 +92,9 @@ [FixedPcd]=0D gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## C= ONSUMES=0D gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate ## C= ONSUMES=0D - gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress ## C= ONSUMES=0D - gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ## C= ONSUMES=0D - gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset ## C= ONSUMES=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase ## C= ONSUMES=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize ## C= ONSUMES=0D + gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv ## C= ONSUMES=0D gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress ## C= ONSUMES=0D gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize ## C= ONSUMES=0D gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## C= ONSUMES=0D diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.f= df b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf index 0d99114961..22fbfc99f0 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf @@ -2,7 +2,7 @@ # FDF file for the UpXtreme.=0D #=0D #=0D -# Copyright (c) 2020, Intel Corporation. All rights reserved.
=0D +# Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
= =0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -47,9 +47,7 @@ SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D $(gS= iPkgTokenSpaceGuid.PcdBio SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D $(gSiPkgTokenSpaceGui= d.PcdFlashMicrocodeFvSize)=0D SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gSiPkgToke= nSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60=0D SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(gSiPkgT= okenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60=0D -SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gSiP= kgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashM= icrocodeFvOffset)=0D -SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(g= SiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)=0D -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset =3D 0x60=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv =3D 0x60=0D SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D gSiPkgTok= enSpaceGuid.PcdFlashMicrocodeFvBase=0D SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D gSiPkgTok= enSpaceGuid.PcdFlashMicrocodeFvSize=0D SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D gSiPkgTok= enSpaceGuid.PcdFlashMicrocodeFvOffset=0D diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoa= rdPkg.fdf b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoar= dPkg.fdf index ad32268a82..1ab8c13792 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.f= df +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.f= df @@ -2,7 +2,7 @@ # FDF file of Platform.=0D #=0D #=0D -# Copyright (c) 2019, Intel Corporation. All rights reserved.
=0D +# Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.
= =0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -47,9 +47,7 @@ SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D $(gS= iPkgTokenSpaceGuid.PcdBio SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D $(gSiPkgTokenSpaceGui= d.PcdFlashMicrocodeFvSize)=0D SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gSiPkgToke= nSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60=0D SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(gSiPkgT= okenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60=0D -SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gSiP= kgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashM= icrocodeFvOffset)=0D -SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(g= SiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)=0D -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset =3D 0x60=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv =3D 0x60=0D SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D gSiPkgTok= enSpaceGuid.PcdFlashMicrocodeFvBase=0D SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D gSiPkgTok= enSpaceGuid.PcdFlashMicrocodeFvSize=0D SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D gSiPkgTok= enSpaceGuid.PcdFlashMicrocodeFvOffset=0D --=20 2.28.0.windows.1