From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web12.10602.1619611962443156121 for ; Wed, 28 Apr 2021 05:12:42 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: pranav.madhu@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D2B801FB; Wed, 28 Apr 2021 05:12:40 -0700 (PDT) Received: from usa.arm.com (a074742.blr.arm.com [10.162.16.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 6E2443F694; Wed, 28 Apr 2021 05:12:39 -0700 (PDT) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Pierre Gondois , Sami Mujawar Subject: [edk2-platforms][PATCH V2 0/8] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms Date: Wed, 28 Apr 2021 17:42:21 +0530 Message-Id: <20210428121229.32674-1-pranav.madhu@arm.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Changes since V1: - Rebase the patches on top of latest master branch - Addressed comments from Pierre Processor Properties Topology Table (PPTT) describes the topological structure of processors, and their shared resources such as caches. This patch series adds PPTT table for Arm's Neoverse Reference Design platforms. The first patch in this series adds helper macros for PPTT table, and the subsequent patches in this series adds PPTT table for Neoverse Reference Design platforms which is mandatory as per Arm SystemReady SR specification. Link to github branch with the patches in this series - https://github.com/Pranav-Madhu/edk2-platforms/tree/topics/rd_pptt Pranav Madhu (8): Platform/Sgi: Helper macros for PPTT Table Platform/Sgi: ACPI PPTT table for SGI-575 platform Platform/Sgi: ACPI PPTT table for RD-N1-Edge platform Platform/Sgi: ACPI PPTT table for RD-N1-Edge dual-chip Platform/Sgi: ACPI PPTT table for RD-E1-Edge platform Platform/Sgi: ACPI PPTT Table for RD-V1 platform Platform/Sgi: ACPI PPTT Table for RD-V1 quad-chip platform Platform/Sgi: ACPI PPTT table for RD-N2 platform .../SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf | 3 +- .../SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf | 3 +- .../AcpiTables/RdN1EdgeX2AcpiTables.inf | 1 + .../ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 3 +- .../ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf | 3 +- .../SgiPkg/AcpiTables/RdV1McAcpiTables.inf | 1 + .../SgiPkg/AcpiTables/Sgi575AcpiTables.inf | 3 +- Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 160 ++++++++++++ .../ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc | 230 ++++++++++++++++++ .../ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc | 175 +++++++++++++ .../SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc | 192 +++++++++++++++ Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc | 163 +++++++++++++ Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc | 164 +++++++++++++ .../ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc | 169 +++++++++++++ .../ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc | 161 ++++++++++++ 15 files changed, 1426 insertions(+), 5 deletions(-) create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc create mode 100644 Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc --=20 2.17.1