From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.10983.1619611970650961782 for ; Wed, 28 Apr 2021 05:12:50 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: pranav.madhu@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4D4E01042; Wed, 28 Apr 2021 05:12:50 -0700 (PDT) Received: from usa.arm.com (a074742.blr.arm.com [10.162.16.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A669D3F694; Wed, 28 Apr 2021 05:12:48 -0700 (PDT) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Pierre Gondois , Sami Mujawar Subject: [edk2-platforms][PATCH V2 5/8] Platform/Sgi: ACPI PPTT table for RD-E1-Edge platform Date: Wed, 28 Apr 2021 17:42:26 +0530 Message-Id: <20210428121229.32674-6-pranav.madhu@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210428121229.32674-1-pranav.madhu@arm.com> References: <20210428121229.32674-1-pranav.madhu@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable The RD-E1-Edge platform includes two clusters with eight multi-thread CPUs. Each of the CPUs include 32KB L1 Data cache, 32KB L1 Instruction cache and 256KB L2 cache. Each cluster includes a 2MB L3 cache. The platform also includes a system level cache of 8MB. Add PPTT table for RD-E1-Edge platform with this information. Signed-off-by: Pranav Madhu --- Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf | 3 +- Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc | 230 ++++++++++++= ++++++++ 2 files changed, 232 insertions(+), 1 deletion(-) diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf b/Plat= form/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf index 2dd2275665a2..04ef2bfcaa26 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf +++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf @@ -1,7 +1,7 @@ ## @file # ACPI table data and ASL sources required to boot the platform. # -# Copyright (c) 2018-2020, ARM Ltd. All rights reserved. +# Copyright (c) 2018-2021, ARM Ltd. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -23,6 +23,7 @@ Mcfg.aslc RdE1Edge/Dsdt.asl RdE1Edge/Madt.aslc + RdE1Edge/Pptt.aslc Spcr.aslc Ssdt.asl =20 diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc b/Platform= /ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc new file mode 100644 index 000000000000..d4c7b1613a28 --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc @@ -0,0 +1,230 @@ +/** @file +* Processor Properties Topology Table (PPTT) for RD-E1-Edge platform +* +* This file describes the topological structure of the processor block o= n the +* RD-E1-Edge platform in the form as defined by ACPI PPTT table. The RD-= E1-Edge +* platform includes two clusters with eight dual-thread CPUS. Each of th= e CPUs +* include 32KB L1 Data cache, 32KB L1 Instruction cache and 256KB L2 cac= he. +* Each cluster includes a 2MB L3 cache. The platform also includes a sys= tem +* level cache of 8MB. +* +* Copyright (c) 2021, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +* @par Specification Reference: +* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology= Table +**/ + +#include +#include +#include +#include + +#include "SgiPlatform.h" +#include "SgiAcpiHeader.h" + +#define THREAD_PER_CORE_E1 2 + +#define PPTT_THREAD_INIT(pid, cid, cpuid, tid) = \ + { = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + sizeof (RDE1EDGE_PPTT_THREAD), /* Length */ = \ + PPTT_PROCESSOR_THREAD_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid].Core[cpuid]), /* Parent */ = \ + ((pid << 5) | (cid << 4) | (cpuid << 1) | tid), = \ + /* ACPI Id */ = \ + 0 /* Num of private resource *= / \ + ) = \ + } + +#define PPTT_CORE_INIT(pid, cid, cpuid) = \ + { = \ + /* Parameters for CPU Core */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + OFFSET_OF (RDE1EDGE_PPTT_CORE, DCache), /* Length */ = \ + PPTT_PROCESSOR_CORE_THREADED_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid]), /* Parent */ = \ + 0, /* ACPI Id */ = \ + 2 /* Num of private resour= ce */ \ + ), = \ + = \ + /* Offsets of the private resources */ = \ + { = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid].Core[cpuid].DCache), = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid].Core[cpuid].ICache) = \ + }, = \ + = \ + /* L1 data cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid].Core[cpuid].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_32KB, /* Size */ = \ + 128, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_DATA_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* L1 instruction cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid].Core[cpuid].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_32KB, /* Size */ = \ + 128, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_INST_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* L2 cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + 0, /* Next level of cache */ = \ + SIZE_256KB, /* Size */ = \ + 1024, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* Thread Initialization */ = \ + { = \ + PPTT_THREAD_INIT (pid, cid, cpuid, 0), = \ + PPTT_THREAD_INIT (pid, cid, cpuid, 1) = \ + } = \ + } + +#define PPTT_CLUSTER_INIT(pid, cid) = \ + { = \ + /* Parameters for Cluster */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + OFFSET_OF (RDE1EDGE_PPTT_CLUSTER, L3Cache), /* Length */ = \ + PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package), /* Parent */ = \ + 0, /* ACPI Id */ = \ + 1 /* Num of private resource *= / \ + ), = \ + = \ + /* Offsets of the private resources */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid].L3Cache), = \ + = \ + /* L3 cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + 0, /* Next level of cache */ = \ + SIZE_2MB, /* Size */ = \ + 2048, /* Num of sets */ = \ + 16, /* Associativity */ = \ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* Initialize child cores */ = \ + { = \ + PPTT_CORE_INIT (pid, cid, 0), = \ + PPTT_CORE_INIT (pid, cid, 1), = \ + PPTT_CORE_INIT (pid, cid, 2), = \ + PPTT_CORE_INIT (pid, cid, 3), = \ + PPTT_CORE_INIT (pid, cid, 4), = \ + PPTT_CORE_INIT (pid, cid, 5), = \ + PPTT_CORE_INIT (pid, cid, 6), = \ + PPTT_CORE_INIT (pid, cid, 7) = \ + } = \ + } + +#define PPTT_PACKAGE_INIT(pid) = \ + { = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + OFFSET_OF (RDE1EDGE_PPTT_PACKAGE, Slc), = \ + PPTT_PROCESSOR_PACKAGE_FLAGS, = \ + 0, = \ + 0, = \ + 1 = \ + ), = \ + = \ + /* Offsets of the private resources */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Slc), = \ + = \ + /* SLC parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + 0, /* Next level of cache */ = \ + SIZE_8MB, /* Size */ = \ + 8192, /* Num of sets */ = \ + 16, /* Associativity */ = \ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + { = \ + PPTT_CLUSTER_INIT (pid, 0), = \ + PPTT_CLUSTER_INIT (pid, 1), = \ + } = \ + } + +#pragma pack(1) +typedef struct { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Thread; +} RDE1EDGE_PPTT_THREAD; + +typedef struct { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core; + UINT32 Offset[2]; + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE DCache; + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE ICache; + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache; + RDE1EDGE_PPTT_THREAD Thread[THREAD_PER_CORE_E1]; +} RDE1EDGE_PPTT_CORE; + +typedef struct { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster; + UINT32 Offset; + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L3Cache; + RDE1EDGE_PPTT_CORE Core[CORE_COUNT / THREAD_PER_CO= RE_E1]; +} RDE1EDGE_PPTT_CLUSTER; + +typedef struct { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package; + UINT32 Offset; + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc; + RDE1EDGE_PPTT_CLUSTER Cluster[CLUSTER_COUNT]; +} RDE1EDGE_PPTT_PACKAGE; + +/* + * Processor Properties Topology Table + */ +typedef struct { + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; + RDE1EDGE_PPTT_PACKAGE Package; +} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; +#pragma pack () + +STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { + { + ARM_ACPI_HEADER ( + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATU= RE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION + ) + }, + + PPTT_PACKAGE_INIT (0) +}; + +/* + * Reference the table being generated to prevent the optimizer from rem= oving + * the data structure from the executable + */ +VOID* CONST ReferenceAcpiTable =3D &Pptt; --=20 2.17.1