From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web09.10791.1619611977544393327 for ; Wed, 28 Apr 2021 05:12:57 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: pranav.madhu@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2CB7B1FB; Wed, 28 Apr 2021 05:12:52 -0700 (PDT) Received: from usa.arm.com (a074742.blr.arm.com [10.162.16.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B8FD43F694; Wed, 28 Apr 2021 05:12:50 -0700 (PDT) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Pierre Gondois , Sami Mujawar Subject: [edk2-platforms][PATCH V2 6/8] Platform/Sgi: ACPI PPTT Table for RD-V1 platform Date: Wed, 28 Apr 2021 17:42:27 +0530 Message-Id: <20210428121229.32674-7-pranav.madhu@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210428121229.32674-1-pranav.madhu@arm.com> References: <20210428121229.32674-1-pranav.madhu@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable The RD-V1 platform includes sixteen single-thread CPUs. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB L2 cache. The platform also includes a system level cache of 16MB. Add PPTT table for RD-V1 platform with this information. Signed-off-by: Pranav Madhu --- Platform/ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf | 3 +- Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc | 164 ++++++++++++++++= ++++ 2 files changed, 166 insertions(+), 1 deletion(-) diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf b/Platform= /ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf index a21dcfafef1a..a3e558cf1535 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf +++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf @@ -1,7 +1,7 @@ ## @file # ACPI table data and ASL sources required to boot the platform. # -# Copyright (c) 2020, Arm Ltd. All rights reserved. +# Copyright (c) 2020-2021, Arm Ltd. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -23,6 +23,7 @@ Mcfg.aslc RdV1/Dsdt.asl RdV1/Madt.aslc + RdV1/Pptt.aslc Spcr.aslc Ssdt.asl =20 diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc b/Platform/ARM= /SgiPkg/AcpiTables/RdV1/Pptt.aslc new file mode 100644 index 000000000000..1c157e3bee2e --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc @@ -0,0 +1,164 @@ +/** @file +* Processor Properties Topology Table (PPTT) for RD-V1 single-chip platf= orm +* +* This file describes the topological structure of the processor block o= n the +* RD-V1 single-chip platform in the form as defined by ACPI PPTT table. = The +* RD-V1 single-chip platform includes sixteen single-thread CPUS. Each o= f the +* CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB L2 = cache. +* The platform also includes a system level cache of 16MB. +* +* Copyright (c) 2021, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +* @par Specification Reference: +* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology= Table +**/ + +#include +#include +#include +#include + +#include "SgiPlatform.h" +#include "SgiAcpiHeader.h" + +#define PPTT_CORE_INIT(pid, cid, cpuid) = \ + { = \ + /* Parameters for CPU Core */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ = \ + PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid]), /* Parent */ = \ + ((pid << 4) | cid), /* ACPI Id */ = \ + 2 /* Num of private resource *= / \ + ), = \ + = \ + /* Offsets of the private resources */ = \ + { = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid].Core[cpuid].DCache), = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid].Core[cpuid].ICache) = \ + }, = \ + = \ + /* L1 data cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid].Core[cpuid].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_64KB, /* Size */ = \ + 256, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_DATA_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* L1 instruction cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[cid].Core[cpuid].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_64KB, /* Size */ = \ + 256, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_INST_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* L2 cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + 0, /* Next level of cache */ = \ + SIZE_1MB, /* Size */ = \ + 2048, /* Num of sets */ = \ + 8, /* Associativity */ = \ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + } + +#define PPTT_CLUSTER_INIT(pid, cid) = \ + { = \ + /* Parameters for Cluster */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + OFFSET_OF (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ = \ + PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package), /* Parent */ = \ + 0, /* ACPI Id */ = \ + 0 /* Num of private resource *= / \ + ), = \ + = \ + /* Initialize child core */ = \ + { = \ + PPTT_CORE_INIT (pid, cid, 0) = \ + } = \ + } + +#pragma pack(1) +/* + * Processor Properties Topology Table + */ +typedef struct { + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; + RD_PPTT_SLC_PACKAGE Package; +} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; +#pragma pack () + +STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { + { + ARM_ACPI_HEADER ( + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATU= RE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION + ) + }, + + { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( + OFFSET_OF (RD_PPTT_SLC_PACKAGE, Slc), + PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 1), + + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + Package.Slc), + + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ + 0, /* Next level of cache */ + SIZE_16MB, /* Size */ + 16384, /* Num of sets */ + 16, /* Associativity */ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ + 64 /* Line size */ + ), + + { + PPTT_CLUSTER_INIT (0, 0), + PPTT_CLUSTER_INIT (0, 1), + PPTT_CLUSTER_INIT (0, 2), + PPTT_CLUSTER_INIT (0, 3), + PPTT_CLUSTER_INIT (0, 4), + PPTT_CLUSTER_INIT (0, 5), + PPTT_CLUSTER_INIT (0, 6), + PPTT_CLUSTER_INIT (0, 7), + PPTT_CLUSTER_INIT (0, 8), + PPTT_CLUSTER_INIT (0, 9), + PPTT_CLUSTER_INIT (0, 10), + PPTT_CLUSTER_INIT (0, 11), + PPTT_CLUSTER_INIT (0, 12), + PPTT_CLUSTER_INIT (0, 13), + PPTT_CLUSTER_INIT (0, 14), + PPTT_CLUSTER_INIT (0, 15) + } + } +}; + +/* + * Reference the table being generated to prevent the optimizer from rem= oving + * the data structure from the executable + */ +VOID* CONST ReferenceAcpiTable =3D &Pptt; --=20 2.17.1