From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.10984.1619611974321192334 for ; Wed, 28 Apr 2021 05:12:54 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: pranav.madhu@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 01A0F1042; Wed, 28 Apr 2021 05:12:54 -0700 (PDT) Received: from usa.arm.com (a074742.blr.arm.com [10.162.16.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 934883F694; Wed, 28 Apr 2021 05:12:52 -0700 (PDT) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Pierre Gondois , Sami Mujawar Subject: [edk2-platforms][PATCH V2 7/8] Platform/Sgi: ACPI PPTT Table for RD-V1 quad-chip platform Date: Wed, 28 Apr 2021 17:42:28 +0530 Message-Id: <20210428121229.32674-8-pranav.madhu@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210428121229.32674-1-pranav.madhu@arm.com> References: <20210428121229.32674-1-pranav.madhu@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable The RD-V1 quad-chip platform consists of four chips connected over cache coherent interconnect. Each chip on the platform includes four single- thread CPUS. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB L2 cache. The platform also includes a system level cache of 16MB per chip. Add PPTT table for RD-V1 quad-chip platform with this information. Signed-off-by: Pranav Madhu --- Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf | 1 + Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc | 169 ++++++++++++++= ++++++ 2 files changed, 170 insertions(+) diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf b/Platfo= rm/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf index c49546ec0b27..ffda4f925b19 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf +++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf @@ -24,6 +24,7 @@ RdV1Mc/Dsdt.asl RdV1Mc/Hmat.aslc RdV1Mc/Madt.aslc + RdV1Mc/Pptt.aslc RdV1Mc/Srat.aslc Spcr.aslc Ssdt.asl diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc b/Platform/A= RM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc new file mode 100644 index 000000000000..5e35871b068b --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc @@ -0,0 +1,169 @@ +/** @file +* Processor Properties Topology Table (PPTT) for RD-V1 quad-chip platfor= m +* +* This file describes the topological structure of the processor block o= n the +* RD-V1 quad-chip platform in the form as defined by ACPI PPTT table. Th= e RD-V1 +* quad-chip platform is composed of four identical chips connected over = cache +* coherent interconnect. Each of the chip on the platform includes four = single +* thread CPUS. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Inst= ruction +* cache and 1MB L2 cache. The platform also includes a system level cach= e of +* 16MB per chip. +* +* Copyright (c) 2021, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +* @par Specification Reference: +* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology= Table +**/ + +#include +#include +#include +#include + +#include "SgiPlatform.h" +#include "SgiAcpiHeader.h" + +#define CHIP_COUNT FixedPcdGet32 (PcdChipCount) + +#define PPTT_CORE_INIT(pid, cid, cpuid) = \ + { = \ + /* Parameters for CPU Core */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ = \ + PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package[pid].Cluster[cid]), /* Parent */ = \ + ((pid << 2) | cid), /* ACPI Id */ = \ + 2 /* Num of private resource *= / \ + ), = \ + = \ + /* Offsets of the private resources */ = \ + { = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package[pid].Cluster[cid].Core[cpuid].DCache), = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package[pid].Cluster[cid].Core[cpuid].ICache) = \ + }, = \ + = \ + /* L1 data cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package[pid].Cluster[cid].Core[cpuid].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_64KB, /* Size */ = \ + 256, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_DATA_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* L1 instruction cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package[pid].Cluster[cid].Core[cpuid].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_64KB, /* Size */ = \ + 256, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_INST_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + /* L2 cache parameters */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + 0, /* Next level of cache */ = \ + SIZE_1MB, /* Size */ = \ + 2048, /* Num of sets */ = \ + 8, /* Associativity */ = \ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + } + +#define PPTT_CLUSTER_INIT(pid, cid) = \ + { = \ + /* Parameters for Cluster */ = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + OFFSET_OF (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ = \ + PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package[pid]), /* Parent */ = \ + 0, /* ACPI Id */ = \ + 0 /* Num of private resource *= / \ + ), = \ + = \ + /* Initialize child core */ = \ + { = \ + PPTT_CORE_INIT (pid, cid, 0) = \ + } = \ + } + +#define PPTT_PACKAGE_INIT(pid) = \ + { = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + OFFSET_OF (RD_PPTT_SLC_PACKAGE, Slc), /* Length */ = \ + PPTT_PROCESSOR_PACKAGE_FLAGS, /* Flag */ = \ + 0, /* Parent */ = \ + 0, /* ACPI Id */ = \ + 1 /* Num of private resource *= / \ + ), = \ + = \ + /* Offsets of the private resources */ = \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package[pid].Slc), = \ + = \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + 0, /* Next level of cache */ = \ + SIZE_16MB, /* Size */ = \ + 16384, /* Num of sets */ = \ + 16, /* Associativity */ = \ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ + 64 /* Line size */ = \ + ), = \ + = \ + { = \ + PPTT_CLUSTER_INIT (pid, 0), = \ + PPTT_CLUSTER_INIT (pid, 1), = \ + PPTT_CLUSTER_INIT (pid, 2), = \ + PPTT_CLUSTER_INIT (pid, 3), = \ + } = \ + } + +#pragma pack(1) +/* + * Processor Properties Topology Table + */ +typedef struct { + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; + RD_PPTT_SLC_PACKAGE Package[CHIP_= COUNT]; +} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; +#pragma pack () + +STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { + { + ARM_ACPI_HEADER ( + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATU= RE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION + ) + }, + + { + PPTT_PACKAGE_INIT (0), + PPTT_PACKAGE_INIT (1), + PPTT_PACKAGE_INIT (2), + PPTT_PACKAGE_INIT (3) + } +}; + +/* + * Reference the table being generated to prevent the optimizer from rem= oving + * the data structure from the executable + */ +VOID* CONST ReferenceAcpiTable =3D &Pptt; --=20 2.17.1