From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) by mx.groups.io with SMTP id smtpd.web09.7361.1620141655803480463 for ; Tue, 04 May 2021 08:20:56 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=fCaJ9eWS; spf=pass (domain: linaro.org, ip: 209.85.221.42, mailfrom: etienne.carriere@linaro.org) Received: by mail-wr1-f42.google.com with SMTP id x7so9869593wrw.10 for ; Tue, 04 May 2021 08:20:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dHylevd3siCXFLC0TbTIB2zY8w5Dtzvs+4E91i03nTI=; b=fCaJ9eWSp7dt1U5FNkxTVzLN92EVGjENKcl56zFts0haK2E50aUFox+kr25KdXmkQ+ XRnjJc0cL/8TEqSXyuK+T9+K8RY4sW38QJ5VHkpS9T7jRP3PO8HCAGiz2lA5rFGCRWQS ZDO+rNn/kctsQJypJ2Ceg9X4gHyWFsj+pldfHCGINux09Baf5U3QBUseV7obbn/5SDKS 90qqag36VACkUIOyrpjAh7e2GDOkkIwCbsXZ69XvgS/U5O0hllF0YwwNlcsSSnlVeAOF ApxRvhMt1n3R4efOZNKz3sDYWWphxm8y5v+rU9y1KGnHJouKxSCTeHPjIWc6LF4NGAu6 Iozw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dHylevd3siCXFLC0TbTIB2zY8w5Dtzvs+4E91i03nTI=; b=ZG0bLyb/+wmXrubnL56psBGRjojYUaCvXoi4Zl8vikATBjpry9NqfumACtq55A6uuN KVXX4tIzFsi+ANLYgveCh9vRSRT+WWQRKsOwCy6R7f3qVTBLLit/9JYPG9yM09hol5Os BNVv8KfCHjctJUn5nLpIL/VaCwkVEOQasC//0viD6TKnPyrPrgGKXwr+UPMrKYOcTdOJ uJ69gmeYf7pGGSyC/FFTjQN/o1wnRlJJ90vsBfSU1MOUv5zxtYzKv5LMsz8OFst1Z0Ba GEqLH7Y8IkVAfsGaXZSWEXckP8jvosGXpg2gQcjFk3Ncz9Tvj+aWGCWhKeFfkNfPwvst gtfA== X-Gm-Message-State: AOAM530HpOCZ0ui3jL3LpAz4i0yky7W+2zboDRms+iQncWcNNNzLsEOB G9S8qHRCzXkeH7vYFVgvRJ6U5fp9O4Cycw== X-Google-Smtp-Source: ABdhPJxLO9x9nKDnCBJGxeVI7TM7pZ5oEPTt1ZKhwQWHY4eX9+ehkK9I77JbhjmOMGQyh63uFmPmXQ== X-Received: by 2002:a5d:4888:: with SMTP id g8mr4363841wrq.384.1620141654305; Tue, 04 May 2021 08:20:54 -0700 (PDT) Return-Path: Received: from lmecxl0524.lme.st.com ([2a04:cec0:11d7:652f:452f:f0ef:fb46:d5f4]) by smtp.gmail.com with ESMTPSA id c2sm2919661wmr.22.2021.05.04.08.20.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 May 2021 08:20:54 -0700 (PDT) From: "Etienne Carriere" To: devel@edk2.groups.io Cc: Achin Gupta , Ard Biesheuvel , Jiewen Yao , Leif Lindholm , Sami Mujawar , Sughosh Ganu , Etienne Carriere Subject: [PATCH 1/5] ArmPkg/IndustryStandard: 32b/64b agnostic FF-A and Mm SVC IDs Date: Tue, 4 May 2021 17:20:44 +0200 Message-Id: <20210504152048.8739-2-etienne.carriere@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504152048.8739-1-etienne.carriere@linaro.org> References: <20210504152048.8739-1-etienne.carriere@linaro.org> Defines ARM_SVC_ID_FFA_* and ARM_SVC_ID_SP_* identifiers for 32bit function IDs as per SMCCC specification. Defines also generic ARM SVC identifier macros to wrap 32bit or 64bit identifiers upon target built architecture. Cc: Achin Gupta Cc: Ard Biesheuvel Cc: Leif Lindholm Cc: Sughosh Ganu Signed-off-by: Etienne Carriere --- ArmPkg/Include/IndustryStandard/ArmFfaSvc.h | 12 ++++++++++++ ArmPkg/Include/IndustryStandard/ArmMmSvc.h | 15 +++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/ArmPkg/Include/IndustryStandard/ArmFfaSvc.h b/ArmPkg/Include/IndustryStandard/ArmFfaSvc.h index 65b8343ade..ebcb54b28b 100644 --- a/ArmPkg/Include/IndustryStandard/ArmFfaSvc.h +++ b/ArmPkg/Include/IndustryStandard/ArmFfaSvc.h @@ -17,9 +17,21 @@ #define ARM_FFA_SVC_H_ #define ARM_SVC_ID_FFA_VERSION_AARCH32 0x84000063 +#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32 0x8400006F +#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32 0x84000070 #define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64 0xC400006F #define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64 0xC4000070 +/* Generic IDs when using AArch32 or AArch64 execution state */ +#ifdef MDE_CPU_AARCH64 +#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64 +#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64 +#endif +#ifdef MDE_CPU_ARM +#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32 +#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32 +#endif + #define SPM_MAJOR_VERSION_FFA 1 #define SPM_MINOR_VERSION_FFA 0 diff --git a/ArmPkg/Include/IndustryStandard/ArmMmSvc.h b/ArmPkg/Include/IndustryStandard/ArmMmSvc.h index 33d60ccf17..deb3bc99d2 100644 --- a/ArmPkg/Include/IndustryStandard/ArmMmSvc.h +++ b/ArmPkg/Include/IndustryStandard/ArmMmSvc.h @@ -15,10 +15,25 @@ * privileged operations on its behalf. */ #define ARM_SVC_ID_SPM_VERSION_AARCH32 0x84000060 +#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32 0x84000061 +#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32 0x84000064 +#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32 0x84000065 #define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64 0xC4000061 #define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64 0xC4000064 #define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64 0xC4000065 +/* Generic IDs when using AArch32 or AArch64 execution state */ +#ifdef MDE_CPU_AARCH64 +#define ARM_SVC_ID_SP_EVENT_COMPLETE ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64 +#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64 +#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64 +#endif +#ifdef MDE_CPU_ARM +#define ARM_SVC_ID_SP_EVENT_COMPLETE ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32 +#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32 +#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32 +#endif + #define SET_MEM_ATTR_DATA_PERM_MASK 0x3 #define SET_MEM_ATTR_DATA_PERM_SHIFT 0 #define SET_MEM_ATTR_DATA_PERM_NO_ACCESS 0 -- 2.17.1