From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) by mx.groups.io with SMTP id smtpd.web09.7363.1620141657784929652 for ; Tue, 04 May 2021 08:20:58 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=Eb208A1x; spf=pass (domain: linaro.org, ip: 209.85.221.46, mailfrom: etienne.carriere@linaro.org) Received: by mail-wr1-f46.google.com with SMTP id l14so9878533wrx.5 for ; Tue, 04 May 2021 08:20:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/eFQoNtzjz0NZZjGA+x13gCxiNPiRKSR6eeSK6NY3E0=; b=Eb208A1x+5RduU4uXy82VWiEl5fXwUi9OrmhWQkSnJTLXPJGIGnTLafjUWHwaohqpf QeYlOzb5fLbtNqzNcUgt39z6ziMYAt9kFK02NTwHrPUzf5sXkfy87vAnsnnaS54Ve5pI b0LZjbvk8p1N3IbgGQnMhRNTTv9FZ/avS4/AzsORs/qLrYPuE5+meMqO/FqHcIpSbnaR At0IOMaGI/qLu+bDgRrH2fofF+TeoPnVgEcwtZXoxp9C6TopToRrJn2lwbbH7hDOxC/G 4NCx6uLQmfIYhQk6y6vWT/ma3QD9jTE0jGgfnTVlO9ioRompDoGefIMwtImP4SYFsGps 4j7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/eFQoNtzjz0NZZjGA+x13gCxiNPiRKSR6eeSK6NY3E0=; b=S+cBz9qWzsh7F66tzGmZ36MaGjeaY444RKWQwqAoRFQvhkm7gYu0LdOokhsVNEt8DY AAkp9NgaIFGIQS2LGm421ZHqIX227Z4stjJPT+5JwekqHfHH9dAIWVIyUJ38PqbKMej8 UBCvB+bPpGwrNTxv5XICA09eeZe4N6Ckweu9I0Aac7chmH55RhXpFvLNeeTwm7B5Ojln S4c7RYxBgRJEqyS8ixXxw3sB6yVuz+TAvGWeyKVKlBI6KdAe9d/z9tDdIzMnMtLT236S azCyXVLwYpq4BM8mYdT6X+S8Fhui9Z6q1BdOINWxSLj8Q5kqcGwU5U4WEvcwGAatg7l9 yRjA== X-Gm-Message-State: AOAM532qQIIv2el7rZx/VhLVkTbUv9wUDjSd8gYDqA6CRh7hwLcsRTjf XHSpwM0+jbaQWnW2COesLsfXnYdoQk9uew== X-Google-Smtp-Source: ABdhPJy3EcNz7FHvu5aKviGH3H8Zj33briJaW58iNDG6e/uzyN0owMUbvXn4I1LYZfsEBgk5hxJyVQ== X-Received: by 2002:adf:f1ca:: with SMTP id z10mr4362407wro.271.1620141656272; Tue, 04 May 2021 08:20:56 -0700 (PDT) Return-Path: Received: from lmecxl0524.lme.st.com ([2a04:cec0:11d7:652f:452f:f0ef:fb46:d5f4]) by smtp.gmail.com with ESMTPSA id c2sm2919661wmr.22.2021.05.04.08.20.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 May 2021 08:20:55 -0700 (PDT) From: "Etienne Carriere" To: devel@edk2.groups.io Cc: Achin Gupta , Ard Biesheuvel , Jiewen Yao , Leif Lindholm , Sami Mujawar , Sughosh Ganu , Etienne Carriere , Bob Feng , Liming Gao Subject: [PATCH 3/5] GenGv: Arm: support images entered in Thumb mode Date: Tue, 4 May 2021 17:20:46 +0200 Message-Id: <20210504152048.8739-4-etienne.carriere@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504152048.8739-1-etienne.carriere@linaro.org> References: <20210504152048.8739-1-etienne.carriere@linaro.org> Change GenFv for Arm architecture to generate a specific jump instruction as image entry instruction, when the target entry label is assembled with Thumb instruction set. This is possible since SecCoreEntryAddress value fetched from the PE32 as its LSBit set when the entry instruction executes in Thumb mode. Cc: Bob Feng Cc: Liming Gao Cc: Achin Gupta Cc: Ard Biesheuvel Cc: Leif Lindholm Cc: Sughosh Ganu Signed-off-by: Etienne Carriere --- BaseTools/Source/C/GenFv/GenFvInternalLib.c | 38 +++++++++++++++----- 1 file changed, 29 insertions(+), 9 deletions(-) diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c b/BaseTools/Source/C/GenFv/GenFvInternalLib.c index 6e296b8ad6..3af65146f6 100644 --- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c +++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c @@ -34,9 +34,27 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "FvLib.h" #include "PeCoffLib.h" -#define ARMT_UNCONDITIONAL_JUMP_INSTRUCTION 0xEB000000 #define ARM64_UNCONDITIONAL_JUMP_INSTRUCTION 0x14000000 +/* + * Arm instruction to jump to Fv enry instruction in Arm or Thumb mode. + * From ARM Arch Ref Manual versions b/c/d, section A8.8.25 BL, BLX (immediate) + * BLX (encoding A2) branches to offset in Thumb instruction set mode. + * BL (encoding A1) branches to offset in Arm instruction set mode. + */ +#define ARM_JUMP_OFFSET_MAX 0xffffff +#define ARM_JUMP_TO_ARM(Offset) (0xeb000000 | ((Offset - 8) >> 2)) + +#define _ARM_JUMP_TO_THUMB(Imm32) (0xfa000000 | \ + (((Imm32) & (1 << 1)) << (24 - 1)) | \ + (((Imm32) >> 2) & 0x7fffff)) +#define ARM_JUMP_TO_THUMB(Offset) _ARM_JUMP_TO_THUMB((Offset) - 8) + +/* + * Arm instruction to retrun from exception (MOVS PC, LR) + */ +#define ARM_RETURN_FROM_EXCEPTION 0xE1B0F07E + BOOLEAN mArm = FALSE; BOOLEAN mRiscV = FALSE; STATIC UINT32 MaxFfsAlignment = 0; @@ -2203,23 +2221,25 @@ Returns: // if we found an SEC core entry point then generate a branch instruction // to it and populate a debugger SWI entry as well if (UpdateVectorSec) { + UINT32 EntryOffset; VerboseMsg("UpdateArmResetVectorIfNeeded updating ARM SEC vector"); - // B SecEntryPoint - signed_immed_24 part +/-32MB offset - // on ARM, the PC is always 8 ahead, so we're not really jumping from the base address, but from base address + 8 - ResetVector[0] = (INT32)(SecCoreEntryAddress - FvInfo->BaseAddress - 8) >> 2; + EntryOffset = (INT32)(SecCoreEntryAddress - FvInfo->BaseAddress); - if (ResetVector[0] > 0x00FFFFFF) { - Error(NULL, 0, 3000, "Invalid", "SEC Entry point must be within 32MB of the start of the FV"); + if (EntryOffset > ARM_JUMP_OFFSET_MAX) { + Error(NULL, 0, 3000, "Invalid", "SEC Entry point offset above 1MB of the start of the FV"); return EFI_ABORTED; } - // Add opcode for an unconditional branch with no link. i.e.: " B SecEntryPoint" - ResetVector[0] |= ARMT_UNCONDITIONAL_JUMP_INSTRUCTION; + if (SecCoreEntryAddress & 1) { + ResetVector[0] = ARM_JUMP_TO_THUMB(EntryOffset); + } else { + ResetVector[0] = ARM_JUMP_TO_ARM(EntryOffset); + } // SWI handler movs pc,lr. Just in case a debugger uses SWI - ResetVector[2] = 0xE1B0F07E; + ResetVector[2] = ARM_RETURN_FROM_EXCEPTION; // Place holder to support a common interrupt handler from ROM. // Currently not supported. For this to be used the reset vector would not be in this FV -- 2.17.1