From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) by mx.groups.io with SMTP id smtpd.web10.28613.1620633210967283213 for ; Mon, 10 May 2021 00:53:31 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=xlZNbuXv; spf=pass (domain: linaro.org, ip: 209.85.221.47, mailfrom: etienne.carriere@linaro.org) Received: by mail-wr1-f47.google.com with SMTP id l14so15532278wrx.5 for ; Mon, 10 May 2021 00:53:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=NM7KV4xjWHxIKYiFX8mU1n4N9kNkWvW4F23OVrLkuB4=; b=xlZNbuXvAwPNhk5HgWsQxFkfrkreycsItNin/dTgiKA/N09JXQyI9AXxQsAwyGKfxv xstevcQNMBnjocXTC6QVYaz/y7c2BWFvVN7sh3qrCp7VG1rW+H1olXXgof+BR3PcsO1z dVEXRY+D9uL3fqbex3R4O3NjZhz7bSjpvX6fBmEpimSeJAc1Udy+xSQgPC2hGLjsxMon l3VIGoqus75KxTTbm8Mxg71fy3uOs8l737DEl3ESkZdK2bkviF8PGcfPQxrL0dv6Xm0r EI6Rwo+VcuR45YE1LoP5KSUf+9O45/rfL4IhNpQDENgjhCm6JGk+1mFgULmMs7E7ExK3 XCVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=NM7KV4xjWHxIKYiFX8mU1n4N9kNkWvW4F23OVrLkuB4=; b=qKMDgpRmQYKYYyRVLY7WnJ0cbgRP521uHtpKS4giHu/ahAOxsNJxqsxvlDil/VqyuU vzUl6YN49KDPk/F9Mns0ZoFxd6uEuOv4gy/l5HzODcqAq/W24CUSPnKk/vYwQl7y3qIk /DiQGLSco5BerTi/MI2csMdZeKUjN3vcpfmR+ECOeS+F9sICW2hE36jvf7sz20DDKKuE X2857vj9TxeRxheEDQPkH/JVIDxHS6V8qkvVEPVINPJx27JGHeYzCY0trlrj4FnBdQzF ZbWNQ8U4bnWABsrxW+VHYeU0iCfhzBcTMEBr7um09A3/Z3auS0a5zzILYn17cqYl3K0N C/RQ== X-Gm-Message-State: AOAM531tIlWlGjUfG7SNv9Pa31uCu0jOa9ma10n5yFYXsJRiH4ys0vyt lGny79oXLqAsKl+gqiq/qYIgBCr9rjtGFDbs X-Google-Smtp-Source: ABdhPJxqj0ZLHubmggcr4BZD8Tzd2WXIypwJZKvLFKRjIPqotiwXfbdZAQlCV6ieuXb+JLrruErQpA== X-Received: by 2002:adf:fd0d:: with SMTP id e13mr29162394wrr.56.1620633209447; Mon, 10 May 2021 00:53:29 -0700 (PDT) Return-Path: Received: from lmecxl0524.home (2a01cb058b850800452ff0effb46d5f4.ipv6.abo.wanadoo.fr. [2a01:cb05:8b85:800:452f:f0ef:fb46:d5f4]) by smtp.gmail.com with ESMTPSA id o13sm18237660wmh.34.2021.05.10.00.53.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 00:53:29 -0700 (PDT) From: "Etienne Carriere" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Ilias Apalodimas , Leif Lindholm , Sami Mujawar , Sughosh Ganu , Thomas Abraham , Etienne Carriere Subject: [edk2-platforms][PATCH 2/4] Drivers/OpTee: Add Aarch32 SVC IDs for 32bit Arm targets Date: Mon, 10 May 2021 09:53:02 +0200 Message-Id: <20210510075304.9125-3-etienne.carriere@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210510075304.9125-1-etienne.carriere@linaro.org> References: <20210510075304.9125-1-etienne.carriere@linaro.org> Add SMCCC function IDs for RPMB read/write service on 32bit architectures. Define generic SP_SVC_RPMB_READ/SP_SVC_RPMB_WRITE IDs for native target architecture (32b or 64b). Changes OpTeeRpmbFvb.c to use architecture agnostic macro ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ for 32b and 64b support. Cc: Ard Biesheuvel Cc: Ilias Apalodimas Cc: Leif Lindholm Cc: Sami Mujawar Signed-off-by: Etienne Carriere --- Drivers/OpTee/OpteeRpmbPkg/OpTeeRpmbFvb.c | 2 +- Drivers/OpTee/OpteeRpmbPkg/OpTeeRpmbFvb.h | 16 ++++++++++++++-- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/Drivers/OpTee/OpteeRpmbPkg/OpTeeRpmbFvb.c b/Drivers/OpTee/OpteeRpmbPkg/OpTeeRpmbFvb.c index 5197c95abd..6eb19bed0e 100644 --- a/Drivers/OpTee/OpteeRpmbPkg/OpTeeRpmbFvb.c +++ b/Drivers/OpTee/OpteeRpmbPkg/OpTeeRpmbFvb.c @@ -68,7 +68,7 @@ ReadWriteRpmb ( ZeroMem (&SvcArgs, sizeof (SvcArgs)); - SvcArgs.Arg0 = ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64; + SvcArgs.Arg0 = ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ; SvcArgs.Arg1 = mStorageId; SvcArgs.Arg2 = 0; SvcArgs.Arg3 = SvcAct; diff --git a/Drivers/OpTee/OpteeRpmbPkg/OpTeeRpmbFvb.h b/Drivers/OpTee/OpteeRpmbPkg/OpTeeRpmbFvb.h index c17fc287ef..bf4a39b9db 100644 --- a/Drivers/OpTee/OpteeRpmbPkg/OpTeeRpmbFvb.h +++ b/Drivers/OpTee/OpteeRpmbPkg/OpTeeRpmbFvb.h @@ -13,8 +13,20 @@ contract between OP-TEE and EDK2. For more details check core/arch/arm/include/kernel/stmm_sp.h in OP-TEE **/ -#define SP_SVC_RPMB_READ 0xC4000066 -#define SP_SVC_RPMB_WRITE 0xC4000067 +#define SP_SVC_RPMB_READ_64 0xC4000066 +#define SP_SVC_RPMB_WRITE_64 0xC4000067 + +#define SP_SVC_RPMB_READ_32 0x84000066 +#define SP_SVC_RPMB_WRITE_32 0x84000067 + +#ifdef MDE_CPU_AARCH64 +#define SP_SVC_RPMB_READ SP_SVC_RPMB_READ_64 +#define SP_SVC_RPMB_WRITE SP_SVC_RPMB_WRITE_64 +#endif +#ifdef MDE_CPU_ARM +#define SP_SVC_RPMB_READ SP_SVC_RPMB_READ_32 +#define SP_SVC_RPMB_WRITE SP_SVC_RPMB_WRITE_32 +#endif #define FLASH_SIGNATURE SIGNATURE_32 ('r', 'p', 'm', 'b') #define INSTANCE_FROM_FVB_THIS(a) CR (a, MEM_INSTANCE, FvbProtocol, \ -- 2.17.1