* [edk2-platforms][PATCH V3 01/14] Platform/Sgi: Helper macros for PPTT Table
2021-05-10 20:06 [edk2-platforms][PATCH V3 00/14] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms Pranav Madhu
@ 2021-05-10 20:06 ` Pranav Madhu
2021-05-10 20:06 ` [edk2-platforms][PATCH V3 02/14] Platform/Sgi: Add CPU container for SGI-575 Pranav Madhu
` (14 subsequent siblings)
15 siblings, 0 replies; 20+ messages in thread
From: Pranav Madhu @ 2021-05-10 20:06 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar, Pierre Gondois
Add helper macros for the creation for PPTT table. These macros help
with initializing processor hierarchy node structure, cache type
structure and ID structure.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
| 170 ++++++++++++++++++++
1 file changed, 170 insertions(+)
--git a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
index dcb4e6c77a74..23e6ee14a761 100644
--- a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
+++ b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
@@ -20,6 +20,141 @@
#define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('A','R','M',' ')
#define EFI_ACPI_ARM_CREATOR_REVISION 0x00000099
+#define CORE_COUNT FixedPcdGet32 (PcdCoreCount)
+#define CLUSTER_COUNT FixedPcdGet32 (PcdClusterCount)
+
+#pragma pack(1)
+// PPTT processor core structure
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core;
+ UINT32 ResourceOffset[2];
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE DCache;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE ICache;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache;
+} RD_PPTT_CORE;
+
+// PPTT processor cluster structure
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster;
+ UINT32 ResourceOffset;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L3Cache;
+ RD_PPTT_CORE Core[CORE_COUNT];
+} RD_PPTT_CLUSTER;
+
+// PPTT processor cluster structure without cache
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster;
+ RD_PPTT_CORE Core[CORE_COUNT];
+} RD_PPTT_MINIMAL_CLUSTER;
+
+// PPTT processor package structure
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package;
+ UINT32 ResourceOffset;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc;
+ RD_PPTT_MINIMAL_CLUSTER Cluster[CLUSTER_COUNT];
+} RD_PPTT_SLC_PACKAGE;
+#pragma pack ()
+
+//
+// PPTT processor structure flags for different SoC components as defined in
+// ACPI 6.3 specification
+//
+
+// Processor structure flags for SoC package
+#define PPTT_PROCESSOR_PACKAGE_FLAGS \
+ { \
+ EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL, \
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, \
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, \
+ EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, \
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL \
+ }
+
+// Processor structure flags for cluster
+#define PPTT_PROCESSOR_CLUSTER_FLAGS \
+ { \
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, \
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, \
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, \
+ EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, \
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL \
+ }
+
+// Processor structure flags for cluster with multi-thread core
+#define PPTT_PROCESSOR_CLUSTER_THREADED_FLAGS \
+ { \
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, \
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, \
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, \
+ EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, \
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL \
+ }
+
+// Processor structure flags for single-thread core
+#define PPTT_PROCESSOR_CORE_FLAGS \
+ { \
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, \
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, \
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, \
+ EFI_ACPI_6_3_PPTT_NODE_IS_LEAF \
+ }
+
+// Processor structure flags for multi-thread core
+#define PPTT_PROCESSOR_CORE_THREADED_FLAGS \
+ { \
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, \
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, \
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, \
+ EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, \
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL \
+ }
+
+// Processor structure flags for CPU thread
+#define PPTT_PROCESSOR_THREAD_FLAGS \
+ { \
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, \
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, \
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_THREAD, \
+ EFI_ACPI_6_3_PPTT_NODE_IS_LEAF \
+ }
+
+// PPTT cache structure flags as defined in ACPI 6.3 Specification
+#define PPTT_CACHE_STRUCTURE_FLAGS \
+ { \
+ EFI_ACPI_6_3_PPTT_CACHE_SIZE_VALID, \
+ EFI_ACPI_6_3_PPTT_NUMBER_OF_SETS_VALID, \
+ EFI_ACPI_6_3_PPTT_ASSOCIATIVITY_VALID, \
+ EFI_ACPI_6_3_PPTT_ALLOCATION_TYPE_VALID, \
+ EFI_ACPI_6_3_PPTT_CACHE_TYPE_VALID, \
+ EFI_ACPI_6_3_PPTT_WRITE_POLICY_VALID, \
+ EFI_ACPI_6_3_PPTT_LINE_SIZE_VALID \
+ }
+
+// PPTT cache attributes for data cache
+#define PPTT_DATA_CACHE_ATTR \
+ { \
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, \
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK \
+ }
+
+// PPTT cache attributes for instruction cache
+#define PPTT_INST_CACHE_ATTR \
+ { \
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ, \
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, \
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK \
+ }
+
+// PPTT cache attributes for unified cache
+#define PPTT_UNIFIED_CACHE_ATTR \
+ { \
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, \
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK \
+ }
+
// A macro to initialise the common header part of EFI ACPI tables as defined by
// EFI_ACPI_DESCRIPTION_HEADER structure.
#define ARM_ACPI_HEADER(Signature, Type, Revision) { \
@@ -246,4 +381,39 @@
TotalCacheLevels, CacheLevel, CacheAssociativity, WritePolicy, CacheLineSize \
}
+// EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR
+#define EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT(Length, Flag, Parent, \
+ ACPIProcessorID, NumberOfPrivateResource) \
+ { \
+ EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, /* Type 0 */ \
+ Length, /* Length */ \
+ { \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ }, \
+ Flag, /* Processor flags */ \
+ Parent, /* Ref to parent node */ \
+ ACPIProcessorID, /* UID, as per MADT */ \
+ NumberOfPrivateResource /* Resource count */ \
+ }
+
+// EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE
+#define EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT(Flag, NextLevelCache, Size, \
+ NoOfSets, Associativity, Attributes, LineSize) \
+ { \
+ EFI_ACPI_6_3_PPTT_TYPE_CACHE, /* Type 1 */ \
+ sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), /* Length */ \
+ { \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ }, \
+ Flag, /* Cache flags */ \
+ NextLevelCache, /* Ref to next level */ \
+ Size, /* Size in bytes */ \
+ NoOfSets, /* Num of sets */ \
+ Associativity, /* Num of ways */ \
+ Attributes, /* Cache attributes */ \
+ LineSize /* Line size in bytes */ \
+ }
+
#endif /* __SGI_ACPI_HEADER__ */
--
2.17.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [edk2-platforms][PATCH V3 02/14] Platform/Sgi: Add CPU container for SGI-575
2021-05-10 20:06 [edk2-platforms][PATCH V3 00/14] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms Pranav Madhu
2021-05-10 20:06 ` [edk2-platforms][PATCH V3 01/14] Platform/Sgi: Helper macros for PPTT Table Pranav Madhu
@ 2021-05-10 20:06 ` Pranav Madhu
2021-05-10 20:06 ` [edk2-platforms][PATCH V3 03/14] Platform/Sgi: ACPI PPTT table for SGI-575 platform Pranav Madhu
` (13 subsequent siblings)
15 siblings, 0 replies; 20+ messages in thread
From: Pranav Madhu @ 2021-05-10 20:06 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar, Pierre Gondois
The SGI-575 platform includes two clusters with four single-thread CPUs.
Add processor container devices for the two clusters on the SGI-575
platform and move the existing processor devices into respective
processor containers.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl | 99 +++++++++++---------
1 file changed, 54 insertions(+), 45 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl
index fe0b92137bde..7390849e6231 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl
@@ -12,53 +12,62 @@
DefinitionBlock("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", EFI_ACPI_ARM_OEM_REVISION) {
Scope(_SB) {
-
- Device(CP00) { // A75-0: Cluster 0, Cpu 0
- Name(_HID, "ACPI0007")
- Name(_UID, 0)
- Name(_STA, 0xF)
- }
-
- Device(CP01) { // A75-0: Cluster 0, Cpu 1
- Name(_HID, "ACPI0007")
- Name(_UID, 1)
- Name(_STA, 0xF)
- }
-
- Device(CP02) { // A75-0: Cluster 0, Cpu 2
- Name(_HID, "ACPI0007")
- Name(_UID, 2)
- Name(_STA, 0xF)
- }
-
- Device(CP03) { // A75-0: Cluster 0, Cpu 3
- Name(_HID, "ACPI0007")
- Name(_UID, 3)
- Name(_STA, 0xF)
- }
-
- Device(CP04) { // A75-0: Cluster 1, Cpu 0
- Name(_HID, "ACPI0007")
- Name(_UID, 4)
- Name(_STA, 0xF)
- }
-
- Device(CP05) { // A75-0: Cluster 1, Cpu 1
- Name(_HID, "ACPI0007")
- Name(_UID, 5)
- Name(_STA, 0xF)
- }
-
- Device(CP06) { // A75-0: Cluster 1, Cpu 2
- Name(_HID, "ACPI0007")
- Name(_UID, 6)
- Name(_STA, 0xF)
+ Device (CLU0) { // Cluster 0
+ Name (_HID, "ACPI0010")
+ Name (_UID, 0)
+
+ Device (CP00) { // A75-0: Cluster 0, Cpu 0
+ Name (_HID, "ACPI0007")
+ Name (_UID, 0)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP01) { // A75-0: Cluster 0, Cpu 1
+ Name (_HID, "ACPI0007")
+ Name (_UID, 1)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP02) { // A75-0: Cluster 0, Cpu 2
+ Name (_HID, "ACPI0007")
+ Name (_UID, 2)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP03) { // A75-0: Cluster 0, Cpu 3
+ Name (_HID, "ACPI0007")
+ Name (_UID, 3)
+ Name (_STA, 0xF)
+ }
}
- Device(CP07) { // A75-0: Cluster 1, Cpu 3
- Name(_HID, "ACPI0007")
- Name(_UID, 7)
- Name(_STA, 0xF)
+ Device (CLU1) { // Cluster 1
+ Name (_HID, "ACPI0010")
+ Name (_UID, 1)
+
+ Device (CP04) { // A75-0: Cluster 1, Cpu 0
+ Name (_HID, "ACPI0007")
+ Name (_UID, 4)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP05) { // A75-0: Cluster 1, Cpu 1
+ Name (_HID, "ACPI0007")
+ Name (_UID, 5)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP06) { // A75-0: Cluster 1, Cpu 2
+ Name (_HID, "ACPI0007")
+ Name (_UID, 6)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP07) { // A75-0: Cluster 1, Cpu 3
+ Name (_HID, "ACPI0007")
+ Name (_UID, 7)
+ Name (_STA, 0xF)
+ }
}
// UART PL011
--
2.17.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [edk2-platforms][PATCH V3 03/14] Platform/Sgi: ACPI PPTT table for SGI-575 platform
2021-05-10 20:06 [edk2-platforms][PATCH V3 00/14] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms Pranav Madhu
2021-05-10 20:06 ` [edk2-platforms][PATCH V3 01/14] Platform/Sgi: Helper macros for PPTT Table Pranav Madhu
2021-05-10 20:06 ` [edk2-platforms][PATCH V3 02/14] Platform/Sgi: Add CPU container for SGI-575 Pranav Madhu
@ 2021-05-10 20:06 ` Pranav Madhu
2021-05-10 20:06 ` [edk2-platforms][PATCH V3 04/14] Platform/Sgi: Add CPU container for RD-N1-Edge Pranav Madhu
` (12 subsequent siblings)
15 siblings, 0 replies; 20+ messages in thread
From: Pranav Madhu @ 2021-05-10 20:06 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar, Pierre Gondois
The SGI-575 platform includes two clusters with four single-thread CPUs.
Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache
and 512KB L2 cache. Each cluster includes a 2MB L3 cache. Add PPTT table
for SGI-575 platform with this information.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf | 3 +-
Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc | 172 ++++++++++++++++++++
2 files changed, 174 insertions(+), 1 deletion(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf
index 2121fd39f2f0..b1ee16e98ea3 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf
@@ -1,7 +1,7 @@
## @file
# ACPI table data and ASL sources required to boot the platform.
#
-# Copyright (c) 2018, ARM Ltd. All rights reserved.
+# Copyright (c) 2018 - 2021, ARM Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -22,6 +22,7 @@
Mcfg.aslc
Sgi575/Dsdt.asl
Sgi575/Madt.aslc
+ Sgi575/Pptt.aslc
Spcr.aslc
Ssdt.asl
diff --git a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc
new file mode 100644
index 000000000000..f3032b7e4cdc
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc
@@ -0,0 +1,172 @@
+/** @file
+* Processor Properties Topology Table (PPTT) for SGI-575 platform
+*
+* This file describes the topological structure of the processor block on the
+* SGI-575 platform in the form as defined by ACPI PPTT table. The SGI-575
+* platform includes two clusters with four single-thread CPUS. Each of the CPUs
+* include 64KB L1 Data cache, 64KB L1 Instruction cache and 512KB L2 cache.
+* Each cluster includes a 2MB L3 cache.
+*
+* Copyright (c) 2021, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+
+/*!
+ \brief Define helper macro for populating processor core information.
+ \param PackageId Package instance number.
+ \param ClusterId Cluster instance number.
+ \param CpuId CPU instance number.
+*/
+#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) \
+ { \
+ /* Parameters for CPU Core */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ \
+ PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[ClusterId]), /* Parent */ \
+ ((PackageId << 3) | (ClusterId << 2) | CpuId), /* ACPI Id */ \
+ 2 /* Num of private resource */ \
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ { \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[ClusterId].Core[CpuId].DCache), \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[ClusterId].Core[CpuId].ICache) \
+ }, \
+ \
+ /* L1 data cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[ClusterId].Core[CpuId].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_64KB, /* Size */ \
+ 64, /* Num of sets */ \
+ 16, /* Associativity */ \
+ PPTT_DATA_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L1 instruction cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[ClusterId].Core[CpuId].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_64KB, /* Size */ \
+ 256, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_INST_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L2 cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_512KB, /* Size */ \
+ 1024, /* Num of sets */ \
+ 8, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ }
+
+/*!
+ \brief Define helper macro for populating processor container information.
+ \param PackageId Package instance number.
+ \param ClusterId Cluster instance number.
+*/
+#define PPTT_CLUSTER_INIT(PackageId, ClusterId) \
+ { \
+ /* Parameters for Cluster */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ OFFSET_OF (RD_PPTT_CLUSTER, L3Cache), \
+ /* Length */ \
+ PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package), /* Parent */ \
+ ((PackageId << 1) | ClusterId), /* ACPI Id */ \
+ 1 /* Num of private resource */ \
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[ClusterId].L3Cache), \
+ \
+ /* L3 cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_2MB, /* Size */ \
+ 2048, /* Num of sets */ \
+ 16, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* Initialize child cores */ \
+ { \
+ PPTT_CORE_INIT (PackageId, ClusterId, 0), \
+ PPTT_CORE_INIT (PackageId, ClusterId, 1), \
+ PPTT_CORE_INIT (PackageId, ClusterId, 2), \
+ PPTT_CORE_INIT (PackageId, ClusterId, 3) \
+ } \
+ }
+
+#pragma pack(1)
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package;
+ RD_PPTT_CLUSTER Cluster[CLUSTER_COUNT];
+} SGI575_PPTT_PACKAGE;
+
+/*
+ * Processor Properties Topology Table
+ */
+typedef struct {
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ SGI575_PPTT_PACKAGE Package;
+} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+#pragma pack ()
+
+STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ )
+ },
+
+ {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (
+ OFFSET_OF (SGI575_PPTT_PACKAGE, Cluster[0]),
+ PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 0
+ ),
+ {
+ PPTT_CLUSTER_INIT (0, 0),
+ PPTT_CLUSTER_INIT (0, 1)
+ }
+ }
+};
+
+/*
+ * Reference the table being generated to prevent the optimizer from removing
+ * the data structure from the executable
+ */
+VOID* CONST ReferenceAcpiTable = &Pptt;
--
2.17.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [edk2-platforms][PATCH V3 04/14] Platform/Sgi: Add CPU container for RD-N1-Edge
2021-05-10 20:06 [edk2-platforms][PATCH V3 00/14] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms Pranav Madhu
` (2 preceding siblings ...)
2021-05-10 20:06 ` [edk2-platforms][PATCH V3 03/14] Platform/Sgi: ACPI PPTT table for SGI-575 platform Pranav Madhu
@ 2021-05-10 20:06 ` Pranav Madhu
2021-05-10 20:06 ` [edk2-platforms][PATCH V3 05/14] Platform/Sgi: ACPI PPTT table for RD-N1-Edge platform Pranav Madhu
` (11 subsequent siblings)
15 siblings, 0 replies; 20+ messages in thread
From: Pranav Madhu @ 2021-05-10 20:06 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar, Pierre Gondois
The RD-N1-Edge platform includes two clusters with four single-thread
CPUs. Add processor container devices for the two clusters on the
RD-N1-Edge platform and move the existing processor devices into
respective processor containers.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl | 88 +++++++++++---------
1 file changed, 48 insertions(+), 40 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl
index d9bac33898b1..b88344c3a7ba 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl
@@ -13,54 +13,62 @@
DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
EFI_ACPI_ARM_OEM_REVISION) {
Scope (_SB) {
-
- Device (CP00) { // Neoverse-N1: Cluster 0, Cpu 0
- Name (_HID, "ACPI0007")
+ Device (CLU0) { // Cluster 0
+ Name (_HID, "ACPI0010")
Name (_UID, 0)
- Name (_STA, 0xF)
+
+ Device (CP00) { // Neoverse-N1: Cluster 0, Cpu 0
+ Name (_HID, "ACPI0007")
+ Name (_UID, 0)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP01) { // Neoverse-N1: Cluster 0, Cpu 1
+ Name (_HID, "ACPI0007")
+ Name (_UID, 1)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP02) { // Neoverse-N1: Cluster 0, Cpu 2
+ Name (_HID, "ACPI0007")
+ Name (_UID, 2)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP03) { // Neoverse-N1: Cluster 0, Cpu 3
+ Name (_HID, "ACPI0007")
+ Name (_UID, 3)
+ Name (_STA, 0xF)
+ }
}
- Device (CP01) { // Neoverse-N1: Cluster 0, Cpu 1
- Name (_HID, "ACPI0007")
+ Device (CLU1) { // Cluster 1
+ Name (_HID, "ACPI0010")
Name (_UID, 1)
- Name (_STA, 0xF)
- }
- Device (CP02) { // Neoverse-N1: Cluster 0, Cpu 2
- Name (_HID, "ACPI0007")
- Name (_UID, 2)
- Name (_STA, 0xF)
- }
+ Device (CP04) { // Neoverse-N1: Cluster 1, Cpu 0
+ Name (_HID, "ACPI0007")
+ Name (_UID, 4)
+ Name (_STA, 0xF)
+ }
- Device (CP03) { // Neoverse-N1: Cluster 0, Cpu 3
- Name (_HID, "ACPI0007")
- Name (_UID, 3)
- Name (_STA, 0xF)
- }
+ Device (CP05) { // Neoverse-N1: Cluster 1, Cpu 1
+ Name (_HID, "ACPI0007")
+ Name (_UID, 5)
+ Name (_STA, 0xF)
+ }
- Device (CP04) { // Neoverse-N1: Cluster 1, Cpu 0
- Name (_HID, "ACPI0007")
- Name (_UID, 4)
- Name (_STA, 0xF)
- }
+ Device (CP06) { // Neoverse-N1: Cluster 1, Cpu 2
+ Name (_HID, "ACPI0007")
+ Name (_UID, 6)
+ Name (_STA, 0xF)
+ }
- Device (CP05) { // Neoverse-N1: Cluster 1, Cpu 1
- Name (_HID, "ACPI0007")
- Name (_UID, 5)
- Name (_STA, 0xF)
+ Device (CP07) { // Neoverse-N1: Cluster 1, Cpu 3
+ Name (_HID, "ACPI0007")
+ Name (_UID, 7)
+ Name (_STA, 0xF)
+ }
}
-
- Device (CP06) { // Neoverse-N1: Cluster 1, Cpu 2
- Name (_HID, "ACPI0007")
- Name (_UID, 6)
- Name (_STA, 0xF)
- }
-
- Device (CP07) { // Neoverse-N1: Cluster 1, Cpu 3
- Name (_HID, "ACPI0007")
- Name (_UID, 7)
- Name (_STA, 0xF)
- }
-
} // Scope(_SB)
}
--
2.17.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [edk2-platforms][PATCH V3 05/14] Platform/Sgi: ACPI PPTT table for RD-N1-Edge platform
2021-05-10 20:06 [edk2-platforms][PATCH V3 00/14] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms Pranav Madhu
` (3 preceding siblings ...)
2021-05-10 20:06 ` [edk2-platforms][PATCH V3 04/14] Platform/Sgi: Add CPU container for RD-N1-Edge Pranav Madhu
@ 2021-05-10 20:06 ` Pranav Madhu
2021-05-10 20:06 ` [edk2-platforms][PATCH V3 06/14] Platform/Sgi: Add DSDT ACPI table for RD-N1-Edge dual-chip platform Pranav Madhu
` (10 subsequent siblings)
15 siblings, 0 replies; 20+ messages in thread
From: Pranav Madhu @ 2021-05-10 20:06 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar, Pierre Gondois
The RD-N1-Edge platform includes two clusters with four single-thread
CPUS. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction
cache and 512KB L2 cache. Each cluster includes a 2MB L3 cache. The
platform also includes a system level cache of 8MB. Add PPTT table for
RD-N1-Edge platform with this information.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf | 3 +-
Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc | 186 ++++++++++++++++++++
2 files changed, 188 insertions(+), 1 deletion(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
index 22e33239070b..eecb64186473 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
@@ -1,7 +1,7 @@
## @file
# ACPI table data and ASL sources required to boot the platform.
#
-# Copyright (c) 2018-2020, ARM Ltd. All rights reserved.
+# Copyright (c) 2018-2021, ARM Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -23,6 +23,7 @@
Mcfg.aslc
RdN1Edge/Dsdt.asl
RdN1Edge/Madt.aslc
+ RdN1Edge/Pptt.aslc
Spcr.aslc
Ssdt.asl
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc
new file mode 100644
index 000000000000..028efa908c54
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc
@@ -0,0 +1,186 @@
+/** @file
+* Processor Properties Topology Table (PPTT) for RD-N1-Edge single-chip platform
+*
+* This file describes the topological structure of the processor block on the
+* RD-N1-Edge single-chip platform in the form as defined by ACPI PPTT table. The
+* RD-N1-Edge platform includes two clusters with four single-thread CPUS. Each
+* of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 512KB L2
+* cache. Each cluster includes a 2MB L3 cache. The platform also includes a
+* system level cache of 8MB.
+*
+* Copyright (c) 2021, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+
+/*!
+ \brief Define helper macro for populating processor core information.
+ \param PackageId Package instance number.
+ \param ClusterId Cluster instance number.
+ \param CpuId CPU instance number.
+*/
+#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) \
+ { \
+ /* Parameters for CPU Core */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ \
+ PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[ClusterId]), /* Parent */ \
+ ((PackageId << 3) | (ClusterId << 2) | CpuId), /* ACPI Id */ \
+ 2 /* Num of private resource */ \
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ { \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[ClusterId].Core[CpuId].DCache), \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[ClusterId].Core[CpuId].ICache) \
+ }, \
+ \
+ /* L1 data cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[ClusterId].Core[CpuId].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_64KB, /* Size */ \
+ 256, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_DATA_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L1 instruction cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[ClusterId].Core[CpuId].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_64KB, /* Size */ \
+ 256, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_INST_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L2 cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_512KB, /* Size */ \
+ 1024, /* Num of sets */ \
+ 8, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ }
+
+/*!
+ \brief Define helper macro for populating processor container information.
+ \param PackageId Package instance number.
+ \param ClusterId Cluster instance number.
+*/
+#define PPTT_CLUSTER_INIT(PackageId, ClusterId) \
+ { \
+ /* Parameters for Cluster */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ OFFSET_OF (RD_PPTT_CLUSTER, L3Cache), /* Length */ \
+ PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package), /* Parent */ \
+ ((PackageId << 1) | ClusterId), /* ACPI Id */ \
+ 1 /* Num of private resource */ \
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[ClusterId].L3Cache), \
+ \
+ /* L3 cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_2MB, /* Size */ \
+ 2048, /* Num of sets */ \
+ 16, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* Initialize child cores */ \
+ { \
+ PPTT_CORE_INIT (PackageId, ClusterId, 0), \
+ PPTT_CORE_INIT (PackageId, ClusterId, 1), \
+ PPTT_CORE_INIT (PackageId, ClusterId, 2), \
+ PPTT_CORE_INIT (PackageId, ClusterId, 3) \
+ } \
+ }
+
+#pragma pack(1)
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package;
+ UINT32 Offset;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc;
+ RD_PPTT_CLUSTER Cluster[CLUSTER_COUNT];
+} RDN1EDGE_PPTT_PACKAGE ;
+
+/*
+ * Processor Properties Topology Table
+ */
+typedef struct {
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ RDN1EDGE_PPTT_PACKAGE Package;
+} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+#pragma pack ()
+
+STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ )
+ },
+
+ {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (
+ OFFSET_OF (RDN1EDGE_PPTT_PACKAGE , Slc),
+ PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 1),
+
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ Package.Slc),
+
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT (
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */
+ 0, /* Next level of cache */
+ SIZE_8MB, /* Size */
+ 8192, /* Num of sets */
+ 16, /* Associativity */
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */
+ 64 /* Line size */
+ ),
+ {
+ PPTT_CLUSTER_INIT (0, 0),
+ PPTT_CLUSTER_INIT (0, 1),
+ }
+ }
+};
+
+/*
+ * Reference the table being generated to prevent the optimizer from removing
+ * the data structure from the executable
+ */
+VOID* CONST ReferenceAcpiTable = &Pptt;
--
2.17.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [edk2-platforms][PATCH V3 06/14] Platform/Sgi: Add DSDT ACPI table for RD-N1-Edge dual-chip platform
2021-05-10 20:06 [edk2-platforms][PATCH V3 00/14] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms Pranav Madhu
` (4 preceding siblings ...)
2021-05-10 20:06 ` [edk2-platforms][PATCH V3 05/14] Platform/Sgi: ACPI PPTT table for RD-N1-Edge platform Pranav Madhu
@ 2021-05-10 20:06 ` Pranav Madhu
2021-05-10 20:06 ` [edk2-platforms][PATCH V3 07/14] Platform/Sgi: ACPI PPTT table for RD-N1-Edge dual-chip Pranav Madhu
` (9 subsequent siblings)
15 siblings, 0 replies; 20+ messages in thread
From: Pranav Madhu @ 2021-05-10 20:06 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar, Pierre Gondois
The RD-N1-Edge dual-chip platform is composed of two RD-N1-Edge
platforms connected over a coherent link. Each chip has two clusters
with four CPUs in each cluster. Add the Differentiated System
Description Table (DSDT) ACPI table for this platform with processor
container devices defined containing the corresponding processor
devices.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf | 2 +-
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl | 136 ++++++++++++++++++++
2 files changed, 137 insertions(+), 1 deletion(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
index 76886d1c6a17..c7c29b9c5946 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
@@ -21,7 +21,7 @@
Gtdt.aslc
Iort.aslc
Mcfg.aslc
- RdN1Edge/Dsdt.asl
+ RdN1EdgeX2/Dsdt.asl
RdN1EdgeX2/Hmat.aslc
RdN1EdgeX2/Madt.aslc
RdN1EdgeX2/Srat.aslc
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl
new file mode 100644
index 000000000000..2379f20a79ef
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl
@@ -0,0 +1,136 @@
+/** @file
+* Differentiated System Description Table Fields (DSDT)
+*
+* Copyright (c) 2021, ARM Ltd. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+* - ACPI 6.3, Section 5.2.11.1, Differentiated System Description Table
+**/
+
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
+
+DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
+ EFI_ACPI_ARM_OEM_REVISION) {
+ Scope (_SB) {
+ /* Chip 0 CPUs */
+ Device (CLU0) { // Cluster 0
+ Name (_HID, "ACPI0010")
+ Name (_UID, 0)
+
+ Device (CP00) { // Neoverse-N1: Cluster 0, Cpu 0
+ Name (_HID, "ACPI0007")
+ Name (_UID, 0)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP01) { // Neoverse-N1: Cluster 0, Cpu 1
+ Name (_HID, "ACPI0007")
+ Name (_UID, 1)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP02) { // Neoverse-N1: Cluster 0, Cpu 2
+ Name (_HID, "ACPI0007")
+ Name (_UID, 2)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP03) { // Neoverse-N1: Cluster 0, Cpu 3
+ Name (_HID, "ACPI0007")
+ Name (_UID, 3)
+ Name (_STA, 0xF)
+ }
+ }
+
+ Device (CLU1) { // Cluster 1
+ Name (_HID, "ACPI0010")
+ Name (_UID, 1)
+
+ Device (CP04) { // Neoverse-N1: Cluster 1, Cpu 0
+ Name (_HID, "ACPI0007")
+ Name (_UID, 4)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP05) { // Neoverse-N1: Cluster 1, Cpu 1
+ Name (_HID, "ACPI0007")
+ Name (_UID, 5)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP06) { // Neoverse-N1: Cluster 1, Cpu 2
+ Name (_HID, "ACPI0007")
+ Name (_UID, 6)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP07) { // Neoverse-N1: Cluster 1, Cpu 3
+ Name (_HID, "ACPI0007")
+ Name (_UID, 7)
+ Name (_STA, 0xF)
+ }
+ }
+
+ /* Chip 1 CPUs */
+ Device (CLU2) { // Cluster 2
+ Name (_HID, "ACPI0010")
+ Name (_UID, 2)
+
+ Device (CP08) { // Neoverse-N1: Cluster 2, Cpu 0
+ Name (_HID, "ACPI0007")
+ Name (_UID, 8)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP09) { // Neoverse-N1: Cluster 2, Cpu 1
+ Name (_HID, "ACPI0007")
+ Name (_UID, 9)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP10) { // Neoverse-N1: Cluster 2, Cpu 2
+ Name (_HID, "ACPI0007")
+ Name (_UID, 10)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP11) { // Neoverse-N1: Cluster 2, Cpu 3
+ Name (_HID, "ACPI0007")
+ Name (_UID, 11)
+ Name (_STA, 0xF)
+ }
+ }
+
+ Device (CLU3) { // Cluster 3
+ Name (_HID, "ACPI0010")
+ Name (_UID, 3)
+
+ Device (CP12) { // Neoverse-N1: Cluster 3, Cpu 0
+ Name (_HID, "ACPI0007")
+ Name (_UID, 12)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP13) { // Neoverse-N1: Cluster 3, Cpu 1
+ Name (_HID, "ACPI0007")
+ Name (_UID, 13)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP14) { // Neoverse-N1: Cluster 3, Cpu 2
+ Name (_HID, "ACPI0007")
+ Name (_UID, 14)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP15) { // Neoverse-N1: Cluster 3, Cpu 3
+ Name (_HID, "ACPI0007")
+ Name (_UID, 15)
+ Name (_STA, 0xF)
+ }
+ }
+ } // Scope(_SB)
+}
--
2.17.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [edk2-platforms][PATCH V3 07/14] Platform/Sgi: ACPI PPTT table for RD-N1-Edge dual-chip
2021-05-10 20:06 [edk2-platforms][PATCH V3 00/14] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms Pranav Madhu
` (5 preceding siblings ...)
2021-05-10 20:06 ` [edk2-platforms][PATCH V3 06/14] Platform/Sgi: Add DSDT ACPI table for RD-N1-Edge dual-chip platform Pranav Madhu
@ 2021-05-10 20:06 ` Pranav Madhu
2021-05-10 20:06 ` [edk2-platforms][PATCH V3 08/14] Platform/Sgi: ACPI PPTT table for RD-E1-Edge platform Pranav Madhu
` (8 subsequent siblings)
15 siblings, 0 replies; 20+ messages in thread
From: Pranav Madhu @ 2021-05-10 20:06 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar, Pierre Gondois
The RD-N1-Edge dual-chip platform includes two RD-N1-Edge single-chip
platforms connected over cache coherent interconnect. Each of the
RD-N1-Edge single-chip platform includes two clusters with four
single-thread CPUs. Each of the CPUs include 64KB L1 Data cache, 64KB
L1 Instruction cache and 512KB L2 cache. Each cluster includes a 2MB
L3 cache. The platform also includes a system level cache of 8MB per
chip. Add PPTT table for RD-N1-Edge dual-chip platform with this
information.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf | 1 +
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc | 207 ++++++++++++++++++++
2 files changed, 208 insertions(+)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
index c7c29b9c5946..617519d9dd38 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
@@ -24,6 +24,7 @@
RdN1EdgeX2/Dsdt.asl
RdN1EdgeX2/Hmat.aslc
RdN1EdgeX2/Madt.aslc
+ RdN1EdgeX2/Pptt.aslc
RdN1EdgeX2/Srat.aslc
Spcr.aslc
Ssdt.asl
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc
new file mode 100644
index 000000000000..1f92af9496a1
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc
@@ -0,0 +1,207 @@
+/** @file
+* Processor Properties Topology Table (PPTT) for RD-N1-Edge dual-chip platform
+*
+* This file describes the topological structure of the processor block on the
+* RD-N1-Edge dual-chip platform in the form as defined by ACPI PPTT table. The
+* RD-N1-Edge dual-chip platform includes two RD-N1-Edge single-chip platforms
+* connected over cache coherent interconnect. Each of the RD-N1-Edge single-chip
+* platform includes two clusters with four single-thread CPUS. Each of the CPUs
+* include 64KB L1 Data cache, 64KB L1 Instruction cache and 512KB L2 cache. Each
+* cluster includes a 2MB L3 cache. Each instance of the chip includes a system
+* level cache of 8MB.
+*
+* Copyright (c) 2021, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+
+#define CHIP_COUNT FixedPcdGet32 (PcdChipCount)
+
+/*!
+ \brief Define helper macro for populating processor core information.
+ \param PackageId Package instance number.
+ \param ClusterId Cluster instance number.
+ \param CpuId CPU instance number.
+*/
+#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) \
+ { \
+ /* Parameters for CPU Core */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ \
+ PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[PackageId].Cluster[ClusterId]), /* Parent */ \
+ ((PackageId << 3) | (ClusterId << 2) | CpuId), /* ACPI Id */ \
+ 2 /* Num of private resource */ \
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ { \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[PackageId].Cluster[ClusterId].Core[CpuId].DCache), \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[PackageId].Cluster[ClusterId].Core[CpuId].ICache) \
+ }, \
+ \
+ /* L1 data cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[PackageId].Cluster[ClusterId].Core[CpuId].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_64KB, /* Size */ \
+ 256, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_DATA_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L1 instruction cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[PackageId].Cluster[ClusterId].Core[CpuId].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_64KB, /* Size */ \
+ 256, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_INST_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L2 cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_512KB, /* Size */ \
+ 1024, /* Num of sets */ \
+ 8, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ }
+
+/*!
+ \brief Define helper macro for populating processor container information.
+ \param PackageId Package instance number.
+ \param ClusterId Cluster instance number.
+*/
+#define PPTT_CLUSTER_INIT(PackageId, ClusterId) \
+ { \
+ /* Parameters for Cluster */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ OFFSET_OF (RD_PPTT_CLUSTER, L3Cache), /* Length */ \
+ PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[PackageId]), /* Parent */ \
+ ((PackageId << 1) | ClusterId), /* ACPI Id */ \
+ 1 /* Num of private resource */ \
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[PackageId].Cluster[ClusterId].L3Cache), \
+ \
+ /* L3 cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_2MB, /* Size */ \
+ 2048, /* Num of sets */ \
+ 16, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* Initialize child cores */ \
+ { \
+ PPTT_CORE_INIT (PackageId, ClusterId, 0), \
+ PPTT_CORE_INIT (PackageId, ClusterId, 1), \
+ PPTT_CORE_INIT (PackageId, ClusterId, 2), \
+ PPTT_CORE_INIT (PackageId, ClusterId, 3) \
+ } \
+ }
+
+/*!
+ \brief Define helper macro for populating SoC package information.
+ \param PackageId Package instance number.
+*/
+#define PPTT_PACKAGE_INIT(PackageId) \
+ { \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ OFFSET_OF (RDN1EDGEX2_PPTT_PACKAGE , Slc), /* Length */ \
+ PPTT_PROCESSOR_PACKAGE_FLAGS, /* Flag */ \
+ 0, /* Parent */ \
+ 0, /* ACPI Id */ \
+ 1 /* Num of private resource */ \
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[PackageId].Slc), \
+ \
+ /* SLC parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_8MB, /* Size */ \
+ 8192, /* Num of sets */ \
+ 16, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ { \
+ PPTT_CLUSTER_INIT (PackageId, 0), \
+ PPTT_CLUSTER_INIT (PackageId, 1), \
+ } \
+ }
+
+#pragma pack(1)
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package;
+ UINT32 Offset;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc;
+ RD_PPTT_CLUSTER Cluster[CLUSTER_COUNT];
+} RDN1EDGEX2_PPTT_PACKAGE;
+
+/*
+ * Processor Properties Topology Table
+ */
+typedef struct {
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ RDN1EDGEX2_PPTT_PACKAGE Package[CHIP_COUNT];
+} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+#pragma pack ()
+
+STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ )
+ },
+
+ {
+ PPTT_PACKAGE_INIT (0),
+ PPTT_PACKAGE_INIT (1)
+ }
+};
+
+/*
+ * Reference the table being generated to prevent the optimizer from removing
+ * the data structure from the executable
+ */
+VOID* CONST ReferenceAcpiTable = &Pptt;
--
2.17.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [edk2-platforms][PATCH V3 08/14] Platform/Sgi: ACPI PPTT table for RD-E1-Edge platform
2021-05-10 20:06 [edk2-platforms][PATCH V3 00/14] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms Pranav Madhu
` (6 preceding siblings ...)
2021-05-10 20:06 ` [edk2-platforms][PATCH V3 07/14] Platform/Sgi: ACPI PPTT table for RD-N1-Edge dual-chip Pranav Madhu
@ 2021-05-10 20:06 ` Pranav Madhu
2021-05-11 11:05 ` Sami Mujawar
2021-05-10 20:06 ` [edk2-platforms][PATCH V3 09/14] Platform/Sgi: Add CPU container for RD-V1 platform Pranav Madhu
` (7 subsequent siblings)
15 siblings, 1 reply; 20+ messages in thread
From: Pranav Madhu @ 2021-05-10 20:06 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar, Pierre Gondois
The RD-E1-Edge platform includes two clusters with eight multi-thread
CPUs. Each of the CPUs include 32KB L1 Data cache, 32KB L1 Instruction
cache and 256KB L2 cache. Each cluster includes a 2MB L3 cache. The
platform also includes a system level cache of 8MB. Add PPTT table for
RD-E1-Edge platform with this information.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf | 3 +-
Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc | 252 ++++++++++++++++++++
2 files changed, 254 insertions(+), 1 deletion(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
index 2dd2275665a2..04ef2bfcaa26 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
@@ -1,7 +1,7 @@
## @file
# ACPI table data and ASL sources required to boot the platform.
#
-# Copyright (c) 2018-2020, ARM Ltd. All rights reserved.
+# Copyright (c) 2018-2021, ARM Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -23,6 +23,7 @@
Mcfg.aslc
RdE1Edge/Dsdt.asl
RdE1Edge/Madt.aslc
+ RdE1Edge/Pptt.aslc
Spcr.aslc
Ssdt.asl
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc
new file mode 100644
index 000000000000..91baab73d108
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc
@@ -0,0 +1,252 @@
+/** @file
+* Processor Properties Topology Table (PPTT) for RD-E1-Edge platform
+*
+* This file describes the topological structure of the processor block on the
+* RD-E1-Edge platform in the form as defined by ACPI PPTT table. The RD-E1-Edge
+* platform includes two clusters with eight dual-thread CPUS. Each of the CPUs
+* include 32KB L1 Data cache, 32KB L1 Instruction cache and 256KB L2 cache.
+* Each cluster includes a 2MB L3 cache. The platform also includes a system
+* level cache of 8MB.
+*
+* Copyright (c) 2021, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+
+#define THREAD_PER_CORE_E1 2
+
+/*!
+ \brief Define helper macro for populating processor thread information.
+ \param PackageId Package instance number.
+ \param ClusterId Cluster instance number.
+ \param CpuId CPU instance number.
+ \param ThreadId CPU thread number.
+*/
+#define PPTT_THREAD_INIT(PackageId, ClusterId, CpuId, ThreadId) \
+ { \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ sizeof (RDE1EDGE_PPTT_THREAD), /* Length */ \
+ PPTT_PROCESSOR_THREAD_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[ClusterId].Core[CpuId]), /* Parent */ \
+ ((PackageId << 5) | (ClusterId << 4) | (CpuId << 1) | ThreadId), \
+ /* ACPI Id */ \
+ 0 /* Num of private resource */ \
+ ) \
+ }
+
+/*!
+ \brief Define helper macro for populating processor core information.
+ \param PackageId Package instance number.
+ \param ClusterId Cluster instance number.
+ \param CpuId CPU instance number.
+*/
+#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) \
+ { \
+ /* Parameters for CPU Core */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ OFFSET_OF (RDE1EDGE_PPTT_CORE, DCache), /* Length */ \
+ PPTT_PROCESSOR_CORE_THREADED_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[ClusterId]), /* Parent */ \
+ 0, /* ACPI Id */ \
+ 2 /* Num of private resource */ \
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ { \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[ClusterId].Core[CpuId].DCache), \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[ClusterId].Core[CpuId].ICache) \
+ }, \
+ \
+ /* L1 data cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[ClusterId].Core[CpuId].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_32KB, /* Size */ \
+ 128, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_DATA_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L1 instruction cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[ClusterId].Core[CpuId].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_32KB, /* Size */ \
+ 128, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_INST_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L2 cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_256KB, /* Size */ \
+ 1024, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* Thread Initialization */ \
+ { \
+ PPTT_THREAD_INIT (PackageId, ClusterId, CpuId, 0), \
+ PPTT_THREAD_INIT (PackageId, ClusterId, CpuId, 1) \
+ } \
+ }
+
+/*!
+ \brief Define helper macro for populating processor container information.
+ \param PackageId Package instance number.
+ \param ClusterId Cluster instance number.
+*/
+#define PPTT_CLUSTER_INIT(PackageId, ClusterId) \
+ { \
+ /* Parameters for Cluster */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ OFFSET_OF (RDE1EDGE_PPTT_CLUSTER, L3Cache), /* Length */ \
+ PPTT_PROCESSOR_CLUSTER_THREADED_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package), /* Parent */ \
+ 0, /* ACPI Id */ \
+ 1 /* Num of private resource */ \
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[ClusterId].L3Cache), \
+ \
+ /* L3 cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_2MB, /* Size */ \
+ 2048, /* Num of sets */ \
+ 16, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* Initialize child cores */ \
+ { \
+ PPTT_CORE_INIT (PackageId, ClusterId, 0), \
+ PPTT_CORE_INIT (PackageId, ClusterId, 1), \
+ PPTT_CORE_INIT (PackageId, ClusterId, 2), \
+ PPTT_CORE_INIT (PackageId, ClusterId, 3), \
+ PPTT_CORE_INIT (PackageId, ClusterId, 4), \
+ PPTT_CORE_INIT (PackageId, ClusterId, 5), \
+ PPTT_CORE_INIT (PackageId, ClusterId, 6), \
+ PPTT_CORE_INIT (PackageId, ClusterId, 7) \
+ } \
+ }
+
+/*!
+ \brief Define helper macro for populating SoC package information.
+ \param PackageId Package instance number.
+*/
+#define PPTT_PACKAGE_INIT(PackageId) \
+ { \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ OFFSET_OF (RDE1EDGE_PPTT_PACKAGE, Slc), \
+ PPTT_PROCESSOR_PACKAGE_FLAGS, \
+ 0, \
+ 0, \
+ 1 \
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Slc), \
+ \
+ /* SLC parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_8MB, /* Size */ \
+ 8192, /* Num of sets */ \
+ 16, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ { \
+ PPTT_CLUSTER_INIT (PackageId, 0), \
+ PPTT_CLUSTER_INIT (PackageId, 1), \
+ } \
+ }
+
+#pragma pack(1)
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Thread;
+} RDE1EDGE_PPTT_THREAD;
+
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core;
+ UINT32 Offset[2];
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE DCache;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE ICache;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache;
+ RDE1EDGE_PPTT_THREAD Thread[THREAD_PER_CORE_E1];
+} RDE1EDGE_PPTT_CORE;
+
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster;
+ UINT32 Offset;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L3Cache;
+ RDE1EDGE_PPTT_CORE Core[CORE_COUNT / THREAD_PER_CORE_E1];
+} RDE1EDGE_PPTT_CLUSTER;
+
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package;
+ UINT32 Offset;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc;
+ RDE1EDGE_PPTT_CLUSTER Cluster[CLUSTER_COUNT];
+} RDE1EDGE_PPTT_PACKAGE;
+
+/*
+ * Processor Properties Topology Table
+ */
+typedef struct {
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ RDE1EDGE_PPTT_PACKAGE Package;
+} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+#pragma pack ()
+
+STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ )
+ },
+
+ PPTT_PACKAGE_INIT (0)
+};
+
+/*
+ * Reference the table being generated to prevent the optimizer from removing
+ * the data structure from the executable
+ */
+VOID* CONST ReferenceAcpiTable = &Pptt;
--
2.17.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [edk2-platforms][PATCH V3 08/14] Platform/Sgi: ACPI PPTT table for RD-E1-Edge platform
2021-05-10 20:06 ` [edk2-platforms][PATCH V3 08/14] Platform/Sgi: ACPI PPTT table for RD-E1-Edge platform Pranav Madhu
@ 2021-05-11 11:05 ` Sami Mujawar
2021-05-11 11:25 ` Pranav Madhu
0 siblings, 1 reply; 20+ messages in thread
From: Sami Mujawar @ 2021-05-11 11:05 UTC (permalink / raw)
To: Pranav Madhu, devel; +Cc: Ard Biesheuvel, Pierre Gondois
Hi Pranav,
Please find my response inline marked [SAMI].
Regards,
Sami Mujawar
On 10/05/2021 09:06 PM, Pranav Madhu wrote:
> The RD-E1-Edge platform includes two clusters with eight multi-thread
> CPUs. Each of the CPUs include 32KB L1 Data cache, 32KB L1 Instruction
> cache and 256KB L2 cache. Each cluster includes a 2MB L3 cache. The
> platform also includes a system level cache of 8MB. Add PPTT table for
> RD-E1-Edge platform with this information.
>
> Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
> ---
> Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf | 3 +-
> Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc | 252 ++++++++++++++++++++
> 2 files changed, 254 insertions(+), 1 deletion(-)
>
> diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
> index 2dd2275665a2..04ef2bfcaa26 100644
> --- a/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
> +++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
> @@ -1,7 +1,7 @@
> ## @file
> # ACPI table data and ASL sources required to boot the platform.
> #
> -# Copyright (c) 2018-2020, ARM Ltd. All rights reserved.
> +# Copyright (c) 2018-2021, ARM Ltd. All rights reserved.
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -23,6 +23,7 @@
> Mcfg.aslc
> RdE1Edge/Dsdt.asl
> RdE1Edge/Madt.aslc
> + RdE1Edge/Pptt.aslc
> Spcr.aslc
> Ssdt.asl
>
> diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc
> new file mode 100644
> index 000000000000..91baab73d108
> --- /dev/null
> +++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc
> @@ -0,0 +1,252 @@
> +/** @file
> +* Processor Properties Topology Table (PPTT) for RD-E1-Edge platform
> +*
> +* This file describes the topological structure of the processor block on the
> +* RD-E1-Edge platform in the form as defined by ACPI PPTT table. The RD-E1-Edge
> +* platform includes two clusters with eight dual-thread CPUS. Each of the CPUs
> +* include 32KB L1 Data cache, 32KB L1 Instruction cache and 256KB L2 cache.
> +* Each cluster includes a 2MB L3 cache. The platform also includes a system
> +* level cache of 8MB.
> +*
> +* Copyright (c) 2021, ARM Limited. All rights reserved.
> +*
> +* SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +* @par Specification Reference:
> +* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
> +**/
> +
> +#include <IndustryStandard/Acpi.h>
> +#include <Library/AcpiLib.h>
> +#include <Library/ArmLib.h>
> +#include <Library/PcdLib.h>
> +
> +#include "SgiPlatform.h"
> +#include "SgiAcpiHeader.h"
> +
> +#define THREAD_PER_CORE_E1 2
> +
> +/*!
> + \brief Define helper macro for populating processor thread information.
> + \param PackageId Package instance number.
> + \param ClusterId Cluster instance number.
> + \param CpuId CPU instance number.
> + \param ThreadId CPU thread number.
> +*/
> +#define PPTT_THREAD_INIT(PackageId, ClusterId, CpuId, ThreadId) \
> + { \
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
> + sizeof (RDE1EDGE_PPTT_THREAD), /* Length */ \
> + PPTT_PROCESSOR_THREAD_FLAGS, /* Flag */ \
> + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
> + Package.Cluster[ClusterId].Core[CpuId]), /* Parent */ \
> + ((PackageId << 5) | (ClusterId << 4) | (CpuId << 1) | ThreadId), \
> + /* ACPI Id */ \
> + 0 /* Num of private resource */ \
> + ) \
> + }
> +
> +/*!
> + \brief Define helper macro for populating processor core information.
> + \param PackageId Package instance number.
> + \param ClusterId Cluster instance number.
> + \param CpuId CPU instance number.
> +*/
> +#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) \
> + { \
> + /* Parameters for CPU Core */ \
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
> + OFFSET_OF (RDE1EDGE_PPTT_CORE, DCache), /* Length */ \
> + PPTT_PROCESSOR_CORE_THREADED_FLAGS, /* Flag */ \
> + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
> + Package.Cluster[ClusterId]), /* Parent */ \
> + 0, /* ACPI Id */ \
> + 2 /* Num of private resource */ \
> + ), \
> + \
> + /* Offsets of the private resources */ \
> + { \
> + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
> + Package.Cluster[ClusterId].Core[CpuId].DCache), \
> + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
> + Package.Cluster[ClusterId].Core[CpuId].ICache) \
> + }, \
> + \
> + /* L1 data cache parameters */ \
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
> + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
> + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
> + Package.Cluster[ClusterId].Core[CpuId].L2Cache), \
> + /* Next level of cache */ \
> + SIZE_32KB, /* Size */ \
> + 128, /* Num of sets */ \
> + 4, /* Associativity */ \
> + PPTT_DATA_CACHE_ATTR, /* Attributes */ \
> + 64 /* Line size */ \
> + ), \
> + \
> + /* L1 instruction cache parameters */ \
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
> + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
> + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
> + Package.Cluster[ClusterId].Core[CpuId].L2Cache), \
> + /* Next level of cache */ \
> + SIZE_32KB, /* Size */ \
> + 128, /* Num of sets */ \
> + 4, /* Associativity */ \
> + PPTT_INST_CACHE_ATTR, /* Attributes */ \
> + 64 /* Line size */ \
> + ), \
> + \
> + /* L2 cache parameters */ \
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
> + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
> + 0, /* Next level of cache */ \
> + SIZE_256KB, /* Size */ \
> + 1024, /* Num of sets */ \
> + 4, /* Associativity */ \
> + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
> + 64 /* Line size */ \
> + ), \
> + \
> + /* Thread Initialization */ \
> + { \
> + PPTT_THREAD_INIT (PackageId, ClusterId, CpuId, 0), \
> + PPTT_THREAD_INIT (PackageId, ClusterId, CpuId, 1) \
> + } \
> + }
> +
> +/*!
> + \brief Define helper macro for populating processor container information.
> + \param PackageId Package instance number.
> + \param ClusterId Cluster instance number.
> +*/
> +#define PPTT_CLUSTER_INIT(PackageId, ClusterId) \
> + { \
> + /* Parameters for Cluster */ \
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
> + OFFSET_OF (RDE1EDGE_PPTT_CLUSTER, L3Cache), /* Length */ \
> + PPTT_PROCESSOR_CLUSTER_THREADED_FLAGS, /* Flag */ \
[SAMI] I see that PPTT_PROCESSOR_CLUSTER_THREADED_FLAGS sets the ACPI ID
flag to invalid. Is there a reason for doing this?
Also, it looks like the DSDT for RD-E1-Edge platform does not have the
clusters definitions. Am I missing something here?
Can you take a look, please?
[/SAMI]
> + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
> + Package), /* Parent */ \
> + 0, /* ACPI Id */ \
> + 1 /* Num of private resource */ \
> + ), \
> + \
> + /* Offsets of the private resources */ \
> + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
> + Package.Cluster[ClusterId].L3Cache), \
> + \
> + /* L3 cache parameters */ \
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
> + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
> + 0, /* Next level of cache */ \
> + SIZE_2MB, /* Size */ \
> + 2048, /* Num of sets */ \
> + 16, /* Associativity */ \
> + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
> + 64 /* Line size */ \
> + ), \
> + \
> + /* Initialize child cores */ \
> + { \
> + PPTT_CORE_INIT (PackageId, ClusterId, 0), \
> + PPTT_CORE_INIT (PackageId, ClusterId, 1), \
> + PPTT_CORE_INIT (PackageId, ClusterId, 2), \
> + PPTT_CORE_INIT (PackageId, ClusterId, 3), \
> + PPTT_CORE_INIT (PackageId, ClusterId, 4), \
> + PPTT_CORE_INIT (PackageId, ClusterId, 5), \
> + PPTT_CORE_INIT (PackageId, ClusterId, 6), \
> + PPTT_CORE_INIT (PackageId, ClusterId, 7) \
> + } \
> + }
> +
> +/*!
> + \brief Define helper macro for populating SoC package information.
> + \param PackageId Package instance number.
> +*/
> +#define PPTT_PACKAGE_INIT(PackageId) \
> + { \
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
> + OFFSET_OF (RDE1EDGE_PPTT_PACKAGE, Slc), \
> + PPTT_PROCESSOR_PACKAGE_FLAGS, \
> + 0, \
> + 0, \
> + 1 \
> + ), \
> + \
> + /* Offsets of the private resources */ \
> + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
> + Package.Slc), \
> + \
> + /* SLC parameters */ \
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
> + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
> + 0, /* Next level of cache */ \
> + SIZE_8MB, /* Size */ \
> + 8192, /* Num of sets */ \
> + 16, /* Associativity */ \
> + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
> + 64 /* Line size */ \
> + ), \
> + \
> + { \
> + PPTT_CLUSTER_INIT (PackageId, 0), \
> + PPTT_CLUSTER_INIT (PackageId, 1), \
> + } \
> + }
> +
> +#pragma pack(1)
> +typedef struct {
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Thread;
> +} RDE1EDGE_PPTT_THREAD;
> +
> +typedef struct {
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core;
> + UINT32 Offset[2];
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE DCache;
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE ICache;
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache;
> + RDE1EDGE_PPTT_THREAD Thread[THREAD_PER_CORE_E1];
> +} RDE1EDGE_PPTT_CORE;
> +
> +typedef struct {
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster;
> + UINT32 Offset;
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L3Cache;
> + RDE1EDGE_PPTT_CORE Core[CORE_COUNT / THREAD_PER_CORE_E1];
> +} RDE1EDGE_PPTT_CLUSTER;
> +
> +typedef struct {
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package;
> + UINT32 Offset;
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc;
> + RDE1EDGE_PPTT_CLUSTER Cluster[CLUSTER_COUNT];
> +} RDE1EDGE_PPTT_PACKAGE;
> +
> +/*
> + * Processor Properties Topology Table
> + */
> +typedef struct {
> + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
> + RDE1EDGE_PPTT_PACKAGE Package;
> +} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
> +#pragma pack ()
> +
> +STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
> + {
> + ARM_ACPI_HEADER (
> + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
> + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
> + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
> + )
> + },
> +
> + PPTT_PACKAGE_INIT (0)
> +};
> +
> +/*
> + * Reference the table being generated to prevent the optimizer from removing
> + * the data structure from the executable
> + */
> +VOID* CONST ReferenceAcpiTable = &Pptt;
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [edk2-platforms][PATCH V3 08/14] Platform/Sgi: ACPI PPTT table for RD-E1-Edge platform
2021-05-11 11:05 ` Sami Mujawar
@ 2021-05-11 11:25 ` Pranav Madhu
0 siblings, 0 replies; 20+ messages in thread
From: Pranav Madhu @ 2021-05-11 11:25 UTC (permalink / raw)
To: Sami Mujawar, devel@edk2.groups.io; +Cc: Ard Biesheuvel, Pierre Gondois
Hi Sami,
Please find my response:
>
> Hi Pranav,
>
> Please find my response inline marked [SAMI].
>
> Regards,
>
> Sami Mujawar
>
>
> On 10/05/2021 09:06 PM, Pranav Madhu wrote:
> > The RD-E1-Edge platform includes two clusters with eight multi-thread
> > CPUs. Each of the CPUs include 32KB L1 Data cache, 32KB L1 Instruction
> > cache and 256KB L2 cache. Each cluster includes a 2MB L3 cache. The
> > platform also includes a system level cache of 8MB. Add PPTT table for
> > RD-E1-Edge platform with this information.
> >
<...>
> \
> > + PPTT_PROCESSOR_CLUSTER_THREADED_FLAGS, /* Flag */
> \
> [SAMI] I see that PPTT_PROCESSOR_CLUSTER_THREADED_FLAGS sets the
> ACPI ID flag to invalid. Is there a reason for doing this?
> Also, it looks like the DSDT for RD-E1-Edge platform does not have the
> clusters definitions. Am I missing something here?
> Can you take a look, please?
> [/SAMI]
ACPI CPU container (ACPI0010) is introduced to support combined idles state for CPU core and container. Idle states are not supported for RDE1, and hence container is not added.
> > + OFFSET_OF
> (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
<...>
Regards,
Pranav
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
^ permalink raw reply [flat|nested] 20+ messages in thread
* [edk2-platforms][PATCH V3 09/14] Platform/Sgi: Add CPU container for RD-V1 platform
2021-05-10 20:06 [edk2-platforms][PATCH V3 00/14] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms Pranav Madhu
` (7 preceding siblings ...)
2021-05-10 20:06 ` [edk2-platforms][PATCH V3 08/14] Platform/Sgi: ACPI PPTT table for RD-E1-Edge platform Pranav Madhu
@ 2021-05-10 20:06 ` Pranav Madhu
2021-05-10 20:06 ` [edk2-platforms][PATCH V3 10/14] Platform/Sgi: ACPI PPTT Table " Pranav Madhu
` (6 subsequent siblings)
15 siblings, 0 replies; 20+ messages in thread
From: Pranav Madhu @ 2021-05-10 20:06 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar, Pierre Gondois
The RD-V1 platform is a sixteen core platform with each core contained
in a minimal cluster logic. Update the processor device entries
accordingly in the DSDT ACPI table by moving each of the processor
device entries into a separate processor container device.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl | 176 ++++++++++++++------
1 file changed, 128 insertions(+), 48 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl
index f3e31e4085a3..05e8601290e2 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl
@@ -13,100 +13,180 @@
DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
EFI_ACPI_ARM_OEM_REVISION) {
Scope (_SB) {
- Device (CP00) { // Neoverse V1 core 0
- Name (_HID, "ACPI0007")
+ Device (CL00) { // Cluster 0
+ Name (_HID, "ACPI0010")
Name (_UID, 0)
- Name (_STA, 0xF)
+
+ Device (CP00) { // Neoverse V1 core 0
+ Name (_HID, "ACPI0007")
+ Name (_UID, 0)
+ Name (_STA, 0xF)
+ }
}
- Device (CP01) { // Neoverse V1 core 1
- Name (_HID, "ACPI0007")
+ Device (CL01) { // Cluster 1
+ Name (_HID, "ACPI0010")
Name (_UID, 1)
- Name (_STA, 0xF)
+
+ Device (CP01) { // Neoverse V1 core 1
+ Name (_HID, "ACPI0007")
+ Name (_UID, 1)
+ Name (_STA, 0xF)
+ }
}
- Device (CP02) { // Neoverse V1 core 2
- Name (_HID, "ACPI0007")
+ Device (CL02) { // Cluster 2
+ Name (_HID, "ACPI0010")
Name (_UID, 2)
- Name (_STA, 0xF)
+
+ Device (CP02) { // Neoverse V1 core 2
+ Name (_HID, "ACPI0007")
+ Name (_UID, 2)
+ Name (_STA, 0xF)
+ }
}
- Device (CP03) { // Neoverse V1 core 3
- Name (_HID, "ACPI0007")
+ Device (CL03) { // Cluster 3
+ Name (_HID, "ACPI0010")
Name (_UID, 3)
- Name (_STA, 0xF)
+
+ Device (CP03) { // Neoverse V1 core 3
+ Name (_HID, "ACPI0007")
+ Name (_UID, 3)
+ Name (_STA, 0xF)
+ }
}
- Device (CP04) { // Neoverse V1 core 4
- Name (_HID, "ACPI0007")
+ Device (CL04) { // Cluster 4
+ Name (_HID, "ACPI0010")
Name (_UID, 4)
- Name (_STA, 0xF)
+
+ Device (CP04) { // Neoverse V1 core 4
+ Name (_HID, "ACPI0007")
+ Name (_UID, 4)
+ Name (_STA, 0xF)
+ }
}
- Device (CP05) { // Neoverse V1 core 5
- Name (_HID, "ACPI0007")
+ Device (CL05) { // Cluster 5
+ Name (_HID, "ACPI0010")
Name (_UID, 5)
- Name (_STA, 0xF)
+
+ Device (CP05) { // Neoverse V1 core 5
+ Name (_HID, "ACPI0007")
+ Name (_UID, 5)
+ Name (_STA, 0xF)
+ }
}
- Device (CP06) { // Neoverse V1 core 6
- Name (_HID, "ACPI0007")
+ Device (CL06) { // Cluster 6
+ Name (_HID, "ACPI0010")
Name (_UID, 6)
- Name (_STA, 0xF)
+
+ Device (CP06) { // Neoverse V1 core 6
+ Name (_HID, "ACPI0007")
+ Name (_UID, 6)
+ Name (_STA, 0xF)
+ }
}
- Device (CP07) { // Neoverse V1 core 7
- Name (_HID, "ACPI0007")
+ Device (CL07) { // Cluster 7
+ Name (_HID, "ACPI0010")
Name (_UID, 7)
- Name (_STA, 0xF)
+
+ Device (CP07) { // Neoverse V1 core 7
+ Name (_HID, "ACPI0007")
+ Name (_UID, 7)
+ Name (_STA, 0xF)
+ }
}
- Device (CP08) { // Neoverse V1 core 8
- Name (_HID, "ACPI0007")
+ Device (CL08) { // Cluster 8
+ Name (_HID, "ACPI0010")
Name (_UID, 8)
- Name (_STA, 0xF)
+
+ Device (CP08) { // Neoverse V1 core 8
+ Name (_HID, "ACPI0007")
+ Name (_UID, 8)
+ Name (_STA, 0xF)
+ }
}
- Device (CP09) { // Neoverse V1 core 9
- Name (_HID, "ACPI0007")
+ Device (CL09) { // Cluster 9
+ Name (_HID, "ACPI0010")
Name (_UID, 9)
- Name (_STA, 0xF)
+
+ Device (CP09) { // Neoverse V1 core 9
+ Name (_HID, "ACPI0007")
+ Name (_UID, 9)
+ Name (_STA, 0xF)
+ }
}
- Device (CP10) { // Neoverse V1 core 10
- Name (_HID, "ACPI0007")
+ Device (CL10) { // Cluster 10
+ Name (_HID, "ACPI0010")
Name (_UID, 10)
- Name (_STA, 0xF)
+
+ Device (CP10) { // Neoverse V1 core 10
+ Name (_HID, "ACPI0007")
+ Name (_UID, 10)
+ Name (_STA, 0xF)
+ }
}
- Device (CP11) { // Neoverse V1 core 11
- Name (_HID, "ACPI0007")
+ Device (CL11) { // Cluster 11
+ Name (_HID, "ACPI0010")
Name (_UID, 11)
- Name (_STA, 0xF)
+
+ Device (CP11) { // Neoverse V1 core 11
+ Name (_HID, "ACPI0007")
+ Name (_UID, 11)
+ Name (_STA, 0xF)
+ }
}
- Device (CP12) { // Neoverse V1 core 12
- Name (_HID, "ACPI0007")
+ Device (CL12) { // Cluster 12
+ Name (_HID, "ACPI0010")
Name (_UID, 12)
- Name (_STA, 0xF)
+
+ Device (CP12) { // Neoverse V1 core 12
+ Name (_HID, "ACPI0007")
+ Name (_UID, 12)
+ Name (_STA, 0xF)
+ }
}
- Device (CP13) { // Neoverse V1 core 13
- Name (_HID, "ACPI0007")
+ Device (CL13) { // Cluster 13
+ Name (_HID, "ACPI0010")
Name (_UID, 13)
- Name (_STA, 0xF)
+
+ Device (CP13) { // Neoverse V1 core 13
+ Name (_HID, "ACPI0007")
+ Name (_UID, 13)
+ Name (_STA, 0xF)
+ }
}
- Device (CP14) { // Neoverse V1 core 14
- Name (_HID, "ACPI0007")
+ Device (CL14) { // Cluster 14
+ Name (_HID, "ACPI0010")
Name (_UID, 14)
- Name (_STA, 0xF)
+
+ Device (CP14) { // Neoverse V1 core 14
+ Name (_HID, "ACPI0007")
+ Name (_UID, 14)
+ Name (_STA, 0xF)
+ }
}
- Device (CP15) { // Neoverse V1 core 15
- Name (_HID, "ACPI0007")
+ Device (CL15) { // Cluster 15
+ Name (_HID, "ACPI0010")
Name (_UID, 15)
- Name (_STA, 0xF)
+
+ Device (CP15) { // Neoverse V1 core 15
+ Name (_HID, "ACPI0007")
+ Name (_UID, 15)
+ Name (_STA, 0xF)
+ }
}
} // Scope(_SB)
}
--
2.17.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [edk2-platforms][PATCH V3 10/14] Platform/Sgi: ACPI PPTT Table for RD-V1 platform
2021-05-10 20:06 [edk2-platforms][PATCH V3 00/14] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms Pranav Madhu
` (8 preceding siblings ...)
2021-05-10 20:06 ` [edk2-platforms][PATCH V3 09/14] Platform/Sgi: Add CPU container for RD-V1 platform Pranav Madhu
@ 2021-05-10 20:06 ` Pranav Madhu
2021-05-10 20:06 ` [edk2-platforms][PATCH V3 11/14] Platform/Sgi: Add CPU container for RD-V1 quad-chip platform Pranav Madhu
` (5 subsequent siblings)
15 siblings, 0 replies; 20+ messages in thread
From: Pranav Madhu @ 2021-05-10 20:06 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar, Pierre Gondois
The RD-V1 platform includes sixteen single-thread CPUs. Each of the
CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB
L2 cache. The platform also includes a system level cache of 16MB.
Add PPTT table for RD-V1 platform with this information.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf | 3 +-
Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc | 175 ++++++++++++++++++++
2 files changed, 177 insertions(+), 1 deletion(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf
index a21dcfafef1a..a3e558cf1535 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf
@@ -1,7 +1,7 @@
## @file
# ACPI table data and ASL sources required to boot the platform.
#
-# Copyright (c) 2020, Arm Ltd. All rights reserved.
+# Copyright (c) 2020-2021, Arm Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -23,6 +23,7 @@
Mcfg.aslc
RdV1/Dsdt.asl
RdV1/Madt.aslc
+ RdV1/Pptt.aslc
Spcr.aslc
Ssdt.asl
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc
new file mode 100644
index 000000000000..e494b101e338
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc
@@ -0,0 +1,175 @@
+/** @file
+* Processor Properties Topology Table (PPTT) for RD-V1 single-chip platform
+*
+* This file describes the topological structure of the processor block on the
+* RD-V1 single-chip platform in the form as defined by ACPI PPTT table. The
+* RD-V1 single-chip platform includes sixteen single-thread CPUS. Each of the
+* CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB L2 cache.
+* The platform also includes a system level cache of 16MB.
+*
+* Copyright (c) 2021, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+
+/*!
+ \brief Define helper macro for populating processor core information.
+ \param PackageId Package instance number.
+ \param ClusterId Cluster instance number.
+ \param CpuId CPU instance number.
+*/
+#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) \
+ { \
+ /* Parameters for CPU Core */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ \
+ PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[ClusterId]), /* Parent */ \
+ ((PackageId << 4) | ClusterId), /* ACPI Id */ \
+ 2 /* Num of private resource */ \
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ { \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[ClusterId].Core[CpuId].DCache), \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[ClusterId].Core[CpuId].ICache) \
+ }, \
+ \
+ /* L1 data cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[ClusterId].Core[CpuId].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_64KB, /* Size */ \
+ 256, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_DATA_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L1 instruction cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[ClusterId].Core[CpuId].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_64KB, /* Size */ \
+ 256, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_INST_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L2 cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_1MB, /* Size */ \
+ 2048, /* Num of sets */ \
+ 8, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ }
+
+/*!
+ \brief Define helper macro for populating processor container information.
+ \param PackageId Package instance number.
+ \param ClusterId Cluster instance number.
+*/
+#define PPTT_CLUSTER_INIT(PackageId, ClusterId) \
+ { \
+ /* Parameters for Cluster */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ OFFSET_OF (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ \
+ PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package), /* Parent */ \
+ ((PackageId << 4) | ClusterId), /* ACPI Id */ \
+ 0 /* Num of private resource */ \
+ ), \
+ \
+ /* Initialize child core */ \
+ { \
+ PPTT_CORE_INIT (PackageId, ClusterId, 0) \
+ } \
+ }
+
+#pragma pack(1)
+/*
+ * Processor Properties Topology Table
+ */
+typedef struct {
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ RD_PPTT_SLC_PACKAGE Package;
+} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+#pragma pack ()
+
+STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ )
+ },
+
+ {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (
+ OFFSET_OF (RD_PPTT_SLC_PACKAGE, Slc),
+ PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 1),
+
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ Package.Slc),
+
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT (
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */
+ 0, /* Next level of cache */
+ SIZE_16MB, /* Size */
+ 16384, /* Num of sets */
+ 16, /* Associativity */
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */
+ 64 /* Line size */
+ ),
+
+ {
+ PPTT_CLUSTER_INIT (0, 0),
+ PPTT_CLUSTER_INIT (0, 1),
+ PPTT_CLUSTER_INIT (0, 2),
+ PPTT_CLUSTER_INIT (0, 3),
+ PPTT_CLUSTER_INIT (0, 4),
+ PPTT_CLUSTER_INIT (0, 5),
+ PPTT_CLUSTER_INIT (0, 6),
+ PPTT_CLUSTER_INIT (0, 7),
+ PPTT_CLUSTER_INIT (0, 8),
+ PPTT_CLUSTER_INIT (0, 9),
+ PPTT_CLUSTER_INIT (0, 10),
+ PPTT_CLUSTER_INIT (0, 11),
+ PPTT_CLUSTER_INIT (0, 12),
+ PPTT_CLUSTER_INIT (0, 13),
+ PPTT_CLUSTER_INIT (0, 14),
+ PPTT_CLUSTER_INIT (0, 15)
+ }
+ }
+};
+
+/*
+ * Reference the table being generated to prevent the optimizer from removing
+ * the data structure from the executable
+ */
+VOID* CONST ReferenceAcpiTable = &Pptt;
--
2.17.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [edk2-platforms][PATCH V3 11/14] Platform/Sgi: Add CPU container for RD-V1 quad-chip platform
2021-05-10 20:06 [edk2-platforms][PATCH V3 00/14] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms Pranav Madhu
` (9 preceding siblings ...)
2021-05-10 20:06 ` [edk2-platforms][PATCH V3 10/14] Platform/Sgi: ACPI PPTT Table " Pranav Madhu
@ 2021-05-10 20:06 ` Pranav Madhu
2021-05-10 20:06 ` [edk2-platforms][PATCH V3 12/14] Platform/Sgi: ACPI PPTT Table " Pranav Madhu
` (4 subsequent siblings)
15 siblings, 0 replies; 20+ messages in thread
From: Pranav Madhu @ 2021-05-10 20:06 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar, Pierre Gondois
The RD-V1 quad-chip platform is composed of four RD-V1 platforms
connected over a coherent link. Each chip has four CPU cores with each
core contained in a minimal cluster logic. Update the processor device
entries accordingly in the DSDT ACPI table by moving each of the
processor device entries into a separate processor container devices.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl | 177 ++++++++++++++------
1 file changed, 128 insertions(+), 49 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl
index b1e88587080c..16919cc5aaa0 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl
@@ -13,101 +13,180 @@
DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
EFI_ACPI_ARM_OEM_REVISION) {
Scope (_SB) {
-
- Device (CP00) { // Neoverse V1 core 0
- Name (_HID, "ACPI0007")
+ Device (CL00) { // Cluster 0
+ Name (_HID, "ACPI0010")
Name (_UID, 0)
- Name (_STA, 0xF)
+
+ Device (CP00) { // Neoverse V1 core 0
+ Name (_HID, "ACPI0007")
+ Name (_UID, 0)
+ Name (_STA, 0xF)
+ }
}
- Device (CP01) { // Neoverse V1 core 1
- Name (_HID, "ACPI0007")
+ Device (CL01) { // Cluster 1
+ Name (_HID, "ACPI0010")
Name (_UID, 1)
- Name (_STA, 0xF)
+
+ Device (CP01) { // Neoverse V1 core 1
+ Name (_HID, "ACPI0007")
+ Name (_UID, 1)
+ Name (_STA, 0xF)
+ }
}
- Device (CP02) { // Neoverse V1 core 2
- Name (_HID, "ACPI0007")
+ Device (CL02) { // Cluster 2
+ Name (_HID, "ACPI0010")
Name (_UID, 2)
- Name (_STA, 0xF)
+
+ Device (CP02) { // Neoverse V1 core 2
+ Name (_HID, "ACPI0007")
+ Name (_UID, 2)
+ Name (_STA, 0xF)
+ }
}
- Device (CP03) { // Neoverse V1 core 3
- Name (_HID, "ACPI0007")
+ Device (CL03) { // Cluster 3
+ Name (_HID, "ACPI0010")
Name (_UID, 3)
- Name (_STA, 0xF)
+
+ Device (CP03) { // Neoverse V1 core 3
+ Name (_HID, "ACPI0007")
+ Name (_UID, 3)
+ Name (_STA, 0xF)
+ }
}
- Device (CP04) { // Neoverse V1 core 4
- Name (_HID, "ACPI0007")
+ Device (CL04) { // Cluster 4
+ Name (_HID, "ACPI0010")
Name (_UID, 4)
- Name (_STA, 0xF)
+
+ Device (CP04) { // Neoverse V1 core 4
+ Name (_HID, "ACPI0007")
+ Name (_UID, 4)
+ Name (_STA, 0xF)
+ }
}
- Device (CP05) { // Neoverse V1 core 5
- Name (_HID, "ACPI0007")
+ Device (CL05) { // Cluster 5
+ Name (_HID, "ACPI0010")
Name (_UID, 5)
- Name (_STA, 0xF)
+
+ Device (CP05) { // Neoverse V1 core 5
+ Name (_HID, "ACPI0007")
+ Name (_UID, 5)
+ Name (_STA, 0xF)
+ }
}
- Device (CP06) { // Neoverse V1 core 6
- Name (_HID, "ACPI0007")
+ Device (CL06) { // Cluster 6
+ Name (_HID, "ACPI0010")
Name (_UID, 6)
- Name (_STA, 0xF)
+
+ Device (CP06) { // Neoverse V1 core 6
+ Name (_HID, "ACPI0007")
+ Name (_UID, 6)
+ Name (_STA, 0xF)
+ }
}
- Device (CP07) { // Neoverse V1 core 7
- Name (_HID, "ACPI0007")
+ Device (CL07) { // Cluster 7
+ Name (_HID, "ACPI0010")
Name (_UID, 7)
- Name (_STA, 0xF)
+
+ Device (CP07) { // Neoverse V1 core 7
+ Name (_HID, "ACPI0007")
+ Name (_UID, 7)
+ Name (_STA, 0xF)
+ }
}
- Device (CP08) { // Neoverse V1 core 8
- Name (_HID, "ACPI0007")
+ Device (CL08) { // Cluster 8
+ Name (_HID, "ACPI0010")
Name (_UID, 8)
- Name (_STA, 0xF)
+
+ Device (CP08) { // Neoverse V1 core 8
+ Name (_HID, "ACPI0007")
+ Name (_UID, 8)
+ Name (_STA, 0xF)
+ }
}
- Device (CP09) { // Neoverse V1 core 9
- Name (_HID, "ACPI0007")
+ Device (CL09) { // Cluster 9
+ Name (_HID, "ACPI0010")
Name (_UID, 9)
- Name (_STA, 0xF)
+
+ Device (CP09) { // Neoverse V1 core 9
+ Name (_HID, "ACPI0007")
+ Name (_UID, 9)
+ Name (_STA, 0xF)
+ }
}
- Device (CP10) { // Neoverse V1 core 10
- Name (_HID, "ACPI0007")
+ Device (CL10) { // Cluster 10
+ Name (_HID, "ACPI0010")
Name (_UID, 10)
- Name (_STA, 0xF)
+
+ Device (CP10) { // Neoverse V1 core 10
+ Name (_HID, "ACPI0007")
+ Name (_UID, 10)
+ Name (_STA, 0xF)
+ }
}
- Device (CP11) { // Neoverse V1 core 11
- Name (_HID, "ACPI0007")
+ Device (CL11) { // Cluster 11
+ Name (_HID, "ACPI0010")
Name (_UID, 11)
- Name (_STA, 0xF)
+
+ Device (CP11) { // Neoverse V1 core 11
+ Name (_HID, "ACPI0007")
+ Name (_UID, 11)
+ Name (_STA, 0xF)
+ }
}
- Device (CP12) { // Neoverse V1 core 12
- Name (_HID, "ACPI0007")
+ Device (CL12) { // Cluster 12
+ Name (_HID, "ACPI0010")
Name (_UID, 12)
- Name (_STA, 0xF)
+
+ Device (CP12) { // Neoverse V1 core 12
+ Name (_HID, "ACPI0007")
+ Name (_UID, 12)
+ Name (_STA, 0xF)
+ }
}
- Device (CP13) { // Neoverse V1 core 13
- Name (_HID, "ACPI0007")
+ Device (CL13) { // Cluster 13
+ Name (_HID, "ACPI0010")
Name (_UID, 13)
- Name (_STA, 0xF)
+
+ Device (CP13) { // Neoverse V1 core 13
+ Name (_HID, "ACPI0007")
+ Name (_UID, 13)
+ Name (_STA, 0xF)
+ }
}
- Device (CP14) { // Neoverse V1 core 14
- Name (_HID, "ACPI0007")
+ Device (CL14) { // Cluster 14
+ Name (_HID, "ACPI0010")
Name (_UID, 14)
- Name (_STA, 0xF)
+
+ Device (CP14) { // Neoverse V1 core 14
+ Name (_HID, "ACPI0007")
+ Name (_UID, 14)
+ Name (_STA, 0xF)
+ }
}
- Device (CP15) { // Neoverse V1 core 15
- Name (_HID, "ACPI0007")
+ Device (CL15) { // Cluster 15
+ Name (_HID, "ACPI0010")
Name (_UID, 15)
- Name (_STA, 0xF)
+
+ Device (CP15) { // Neoverse V1 core 15
+ Name (_HID, "ACPI0007")
+ Name (_UID, 15)
+ Name (_STA, 0xF)
+ }
}
} // Scope(_SB)
}
--
2.17.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [edk2-platforms][PATCH V3 12/14] Platform/Sgi: ACPI PPTT Table for RD-V1 quad-chip platform
2021-05-10 20:06 [edk2-platforms][PATCH V3 00/14] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms Pranav Madhu
` (10 preceding siblings ...)
2021-05-10 20:06 ` [edk2-platforms][PATCH V3 11/14] Platform/Sgi: Add CPU container for RD-V1 quad-chip platform Pranav Madhu
@ 2021-05-10 20:06 ` Pranav Madhu
2021-05-10 20:06 ` [edk2-platforms][PATCH V3 13/14] Platform/Sgi: Add CPU container for RD-N2 platform Pranav Madhu
` (3 subsequent siblings)
15 siblings, 0 replies; 20+ messages in thread
From: Pranav Madhu @ 2021-05-10 20:06 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar, Pierre Gondois
The RD-V1 quad-chip platform consists of four chips connected over cache
coherent interconnect. Each chip on the platform includes four single-
thread CPUS. Each of the CPUs include 64KB L1 Data cache, 64KB L1
Instruction cache and 1MB L2 cache. The platform also includes a system
level cache of 16MB per chip. Add PPTT table for RD-V1 quad-chip
platform with this information.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf | 1 +
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc | 184 ++++++++++++++++++++
2 files changed, 185 insertions(+)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf
index c49546ec0b27..ffda4f925b19 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf
@@ -24,6 +24,7 @@
RdV1Mc/Dsdt.asl
RdV1Mc/Hmat.aslc
RdV1Mc/Madt.aslc
+ RdV1Mc/Pptt.aslc
RdV1Mc/Srat.aslc
Spcr.aslc
Ssdt.asl
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc
new file mode 100644
index 000000000000..4b91aa9001cf
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc
@@ -0,0 +1,184 @@
+/** @file
+* Processor Properties Topology Table (PPTT) for RD-V1 quad-chip platform
+*
+* This file describes the topological structure of the processor block on the
+* RD-V1 quad-chip platform in the form as defined by ACPI PPTT table. The RD-V1
+* quad-chip platform is composed of four identical chips connected over cache
+* coherent interconnect. Each of the chip on the platform includes four single
+* thread CPUS. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction
+* cache and 1MB L2 cache. The platform also includes a system level cache of
+* 16MB per chip.
+*
+* Copyright (c) 2021, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+
+#define CHIP_COUNT FixedPcdGet32 (PcdChipCount)
+
+/*!
+ \brief Define helper macro for populating processor core information.
+ \param PackageId Package instance number.
+ \param ClusterId Cluster instance number.
+ \param CpuId CPU instance number.
+*/
+#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) \
+ { \
+ /* Parameters for CPU Core */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ \
+ PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[PackageId].Cluster[ClusterId]), /* Parent */ \
+ ((PackageId << 2) | ClusterId), /* ACPI Id */ \
+ 2 /* Num of private resource */ \
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ { \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[PackageId].Cluster[ClusterId].Core[CpuId].DCache), \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[PackageId].Cluster[ClusterId].Core[CpuId].ICache) \
+ }, \
+ \
+ /* L1 data cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[PackageId].Cluster[ClusterId].Core[CpuId].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_64KB, /* Size */ \
+ 256, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_DATA_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L1 instruction cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[PackageId].Cluster[ClusterId].Core[CpuId].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_64KB, /* Size */ \
+ 256, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_INST_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L2 cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_1MB, /* Size */ \
+ 2048, /* Num of sets */ \
+ 8, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ }
+
+/*!
+ \brief Define helper macro for populating processor container information.
+ \param PackageId Package instance number.
+ \param ClusterId Cluster instance number.
+*/
+#define PPTT_CLUSTER_INIT(PackageId, ClusterId) \
+ { \
+ /* Parameters for Cluster */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ OFFSET_OF (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ \
+ PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[PackageId]), /* Parent */ \
+ ((PackageId << 2) | ClusterId), /* ACPI Id */ \
+ 0 /* Num of private resource */ \
+ ), \
+ \
+ /* Initialize child core */ \
+ { \
+ PPTT_CORE_INIT (PackageId, ClusterId, 0) \
+ } \
+ }
+
+/*!
+ \brief Define helper macro for populating SoC package information.
+ \param PackageId Package instance number.
+*/
+#define PPTT_PACKAGE_INIT(PackageId) \
+ { \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ OFFSET_OF (RD_PPTT_SLC_PACKAGE, Slc), /* Length */ \
+ PPTT_PROCESSOR_PACKAGE_FLAGS, /* Flag */ \
+ 0, /* Parent */ \
+ 0, /* ACPI Id */ \
+ 1 /* Num of private resource */ \
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[PackageId].Slc), \
+ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_16MB, /* Size */ \
+ 16384, /* Num of sets */ \
+ 16, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ { \
+ PPTT_CLUSTER_INIT (PackageId, 0), \
+ PPTT_CLUSTER_INIT (PackageId, 1), \
+ PPTT_CLUSTER_INIT (PackageId, 2), \
+ PPTT_CLUSTER_INIT (PackageId, 3), \
+ } \
+ }
+
+#pragma pack(1)
+/*
+ * Processor Properties Topology Table
+ */
+typedef struct {
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ RD_PPTT_SLC_PACKAGE Package[CHIP_COUNT];
+} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+#pragma pack ()
+
+STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ )
+ },
+
+ {
+ PPTT_PACKAGE_INIT (0),
+ PPTT_PACKAGE_INIT (1),
+ PPTT_PACKAGE_INIT (2),
+ PPTT_PACKAGE_INIT (3)
+ }
+};
+
+/*
+ * Reference the table being generated to prevent the optimizer from removing
+ * the data structure from the executable
+ */
+VOID* CONST ReferenceAcpiTable = &Pptt;
--
2.17.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [edk2-platforms][PATCH V3 13/14] Platform/Sgi: Add CPU container for RD-N2 platform
2021-05-10 20:06 [edk2-platforms][PATCH V3 00/14] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms Pranav Madhu
` (11 preceding siblings ...)
2021-05-10 20:06 ` [edk2-platforms][PATCH V3 12/14] Platform/Sgi: ACPI PPTT Table " Pranav Madhu
@ 2021-05-10 20:06 ` Pranav Madhu
2021-05-10 20:06 ` [edk2-platforms][PATCH V3 14/14] Platform/Sgi: ACPI PPTT table " Pranav Madhu
` (2 subsequent siblings)
15 siblings, 0 replies; 20+ messages in thread
From: Pranav Madhu @ 2021-05-10 20:06 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar, Pierre Gondois
The RD-N2 platform is a sixteen core platform with each core contained
in a minimal cluster logic. Update the processor device entries
accordingly in the DSDT ACPI table by moving each of the processor
device entries into a separate processor container devices.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl | 176 ++++++++++++++------
1 file changed, 128 insertions(+), 48 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl
index 42cb8655b4fb..c5d6f44b3e44 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl
@@ -13,100 +13,180 @@
DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
EFI_ACPI_ARM_OEM_REVISION) {
Scope (_SB) {
- Device (CP00) { // Neoverse N2 core 0
- Name (_HID, "ACPI0007")
+ Device (CL00) { // Cluster 0
+ Name (_HID, "ACPI0010")
Name (_UID, 0)
- Name (_STA, 0xF)
+
+ Device (CP00) { // Neoverse N2 core 0
+ Name (_HID, "ACPI0007")
+ Name (_UID, 0)
+ Name (_STA, 0xF)
+ }
}
- Device (CP01) { // Neoverse N2 core 1
- Name (_HID, "ACPI0007")
+ Device (CL01) { // Cluster 1
+ Name (_HID, "ACPI0010")
Name (_UID, 1)
- Name (_STA, 0xF)
+
+ Device (CP01) { // Neoverse N2 core 1
+ Name (_HID, "ACPI0007")
+ Name (_UID, 1)
+ Name (_STA, 0xF)
+ }
}
- Device (CP02) { // Neoverse N2 core 2
- Name (_HID, "ACPI0007")
+ Device (CL02) { // Cluster 2
+ Name (_HID, "ACPI0010")
Name (_UID, 2)
- Name (_STA, 0xF)
+
+ Device (CP02) { // Neoverse N2 core 2
+ Name (_HID, "ACPI0007")
+ Name (_UID, 2)
+ Name (_STA, 0xF)
+ }
}
- Device (CP03) { // Neoverse N2 core 3
- Name (_HID, "ACPI0007")
+ Device (CL03) { // Cluster 3
+ Name (_HID, "ACPI0010")
Name (_UID, 3)
- Name (_STA, 0xF)
+
+ Device (CP03) { // Neoverse N2 core 3
+ Name (_HID, "ACPI0007")
+ Name (_UID, 3)
+ Name (_STA, 0xF)
+ }
}
- Device (CP04) { // Neoverse N2 core 4
- Name (_HID, "ACPI0007")
+ Device (CL04) { // Cluster 4
+ Name (_HID, "ACPI0010")
Name (_UID, 4)
- Name (_STA, 0xF)
+
+ Device (CP04) { // Neoverse N2 core 4
+ Name (_HID, "ACPI0007")
+ Name (_UID, 4)
+ Name (_STA, 0xF)
+ }
}
- Device (CP05) { // Neoverse N2 core 5
- Name (_HID, "ACPI0007")
+ Device (CL05) { // Cluster 5
+ Name (_HID, "ACPI0010")
Name (_UID, 5)
- Name (_STA, 0xF)
+
+ Device (CP05) { // Neoverse N2 core 5
+ Name (_HID, "ACPI0007")
+ Name (_UID, 5)
+ Name (_STA, 0xF)
+ }
}
- Device (CP06) { // Neoverse N2 core 6
- Name (_HID, "ACPI0007")
+ Device (CL06) { // Cluster 6
+ Name (_HID, "ACPI0010")
Name (_UID, 6)
- Name (_STA, 0xF)
+
+ Device (CP06) { // Neoverse N2 core 6
+ Name (_HID, "ACPI0007")
+ Name (_UID, 6)
+ Name (_STA, 0xF)
+ }
}
- Device (CP07) { // Neoverse N2 core 7
- Name (_HID, "ACPI0007")
+ Device (CL07) { // Cluster 7
+ Name (_HID, "ACPI0010")
Name (_UID, 7)
- Name (_STA, 0xF)
+
+ Device (CP07) { // Neoverse N2 core 7
+ Name (_HID, "ACPI0007")
+ Name (_UID, 7)
+ Name (_STA, 0xF)
+ }
}
- Device (CP08) { // Neoverse N2 core 8
- Name (_HID, "ACPI0007")
+ Device (CL08) { // Cluster 8
+ Name (_HID, "ACPI0010")
Name (_UID, 8)
- Name (_STA, 0xF)
+
+ Device (CP08) { // Neoverse N2 core 8
+ Name (_HID, "ACPI0007")
+ Name (_UID, 8)
+ Name (_STA, 0xF)
+ }
}
- Device (CP09) { // Neoverse N2 core 9
- Name (_HID, "ACPI0007")
+ Device (CL09) { // Cluster 9
+ Name (_HID, "ACPI0010")
Name (_UID, 9)
- Name (_STA, 0xF)
+
+ Device (CP09) { // Neoverse N2 core 9
+ Name (_HID, "ACPI0007")
+ Name (_UID, 9)
+ Name (_STA, 0xF)
+ }
}
- Device (CP10) { // Neoverse N2 core 10
- Name (_HID, "ACPI0007")
+ Device (CL10) { // Cluster 10
+ Name (_HID, "ACPI0010")
Name (_UID, 10)
- Name (_STA, 0xF)
+
+ Device (CP10) { // Neoverse N2 core 10
+ Name (_HID, "ACPI0007")
+ Name (_UID, 10)
+ Name (_STA, 0xF)
+ }
}
- Device (CP11) { // Neoverse N2 core 11
- Name (_HID, "ACPI0007")
+ Device (CL11) { // Cluster 11
+ Name (_HID, "ACPI0010")
Name (_UID, 11)
- Name (_STA, 0xF)
+
+ Device (CP11) { // Neoverse N2 core 11
+ Name (_HID, "ACPI0007")
+ Name (_UID, 11)
+ Name (_STA, 0xF)
+ }
}
- Device (CP12) { // Neoverse N2 core 12
- Name (_HID, "ACPI0007")
+ Device (CL12) { // Cluster 12
+ Name (_HID, "ACPI0010")
Name (_UID, 12)
- Name (_STA, 0xF)
+
+ Device (CP12) { // Neoverse N2 core 12
+ Name (_HID, "ACPI0007")
+ Name (_UID, 12)
+ Name (_STA, 0xF)
+ }
}
- Device (CP13) { // Neoverse N2 core 13
- Name (_HID, "ACPI0007")
+ Device (CL13) { // Cluster 13
+ Name (_HID, "ACPI0010")
Name (_UID, 13)
- Name (_STA, 0xF)
+
+ Device (CP13) { // Neoverse N2 core 13
+ Name (_HID, "ACPI0007")
+ Name (_UID, 13)
+ Name (_STA, 0xF)
+ }
}
- Device (CP14) { // Neoverse N2 core 14
- Name (_HID, "ACPI0007")
+ Device (CL14) { // Cluster 14
+ Name (_HID, "ACPI0010")
Name (_UID, 14)
- Name (_STA, 0xF)
+
+ Device (CP14) { // Neoverse N2 core 14
+ Name (_HID, "ACPI0007")
+ Name (_UID, 14)
+ Name (_STA, 0xF)
+ }
}
- Device (CP15) { // Neoverse N2 core 15
- Name (_HID, "ACPI0007")
+ Device (CL15) { // Cluster 15
+ Name (_HID, "ACPI0010")
Name (_UID, 15)
- Name (_STA, 0xF)
+
+ Device (CP15) { // Neoverse N2 core 15
+ Name (_HID, "ACPI0007")
+ Name (_UID, 15)
+ Name (_STA, 0xF)
+ }
}
} // Scope(_SB)
}
--
2.17.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [edk2-platforms][PATCH V3 14/14] Platform/Sgi: ACPI PPTT table for RD-N2 platform
2021-05-10 20:06 [edk2-platforms][PATCH V3 00/14] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms Pranav Madhu
` (12 preceding siblings ...)
2021-05-10 20:06 ` [edk2-platforms][PATCH V3 13/14] Platform/Sgi: Add CPU container for RD-N2 platform Pranav Madhu
@ 2021-05-10 20:06 ` Pranav Madhu
2021-05-11 11:09 ` [edk2-platforms][PATCH V3 00/14] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms Sami Mujawar
2021-05-11 14:14 ` Sami Mujawar
15 siblings, 0 replies; 20+ messages in thread
From: Pranav Madhu @ 2021-05-10 20:06 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar, Pierre Gondois
The RD-N2 platform includes sixteen single-thread CPUS. Each of the
CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB L2
cache. The platform also includes a system level cache of 32MB. Add PPTT
table for RD-N2 platform with this information.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 3 +-
Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc | 175 ++++++++++++++++++++
2 files changed, 177 insertions(+), 1 deletion(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
index 2ec3e42473a9..c1282a3422ab 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
@@ -1,7 +1,7 @@
## @file
# ACPI table data and ASL sources required to boot the platform.
#
-# Copyright (c) 2020, Arm Ltd. All rights reserved.
+# Copyright (c) 2020-2021, Arm Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -22,6 +22,7 @@
Mcfg.aslc
RdN2/Dsdt.asl
RdN2/Madt.aslc
+ RdN2/Pptt.aslc
Spcr.aslc
Ssdt.asl
SsdtRos.asl
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc
new file mode 100644
index 000000000000..16daf5b7f266
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc
@@ -0,0 +1,175 @@
+/** @file
+* Processor Properties Topology Table (PPTT) for RD-N2 platform
+*
+* This file describes the topological structure of the processor block on the
+* RD-N2 platform in the form as defined by ACPI PPTT table. The RD-N2 platform
+* includes sixteen single-thread CPUS. Each of the CPUs include 64KB L1 Data
+* cache, 64KB L1 Instruction cache and 1MB L2 cache. The platform also includes
+* system level cache of 32MB.
+*
+* Copyright (c) 2021, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+
+/*!
+ \brief Define helper macro for populating processor core information.
+ \param PackageId Package instance number.
+ \param ClusterId Cluster instance number.
+ \param CpuId CPU instance number.
+*/
+#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) \
+ { \
+ /* Parameters for CPU Core */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ \
+ PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[ClusterId]), /* Parent */ \
+ ((PackageId << 4) | ClusterId), /* ACPI Id */ \
+ 2 /* Num of private resource */ \
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ { \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[ClusterId].Core[CpuId].DCache), \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[ClusterId].Core[CpuId].ICache) \
+ }, \
+ \
+ /* L1 data cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[ClusterId].Core[CpuId].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_64KB, /* Size */ \
+ 256, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_DATA_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L1 instruction cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[ClusterId].Core[CpuId].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_64KB, /* Size */ \
+ 256, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_INST_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L2 cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_1MB, /* Size */ \
+ 2048, /* Num of sets */ \
+ 8, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ }
+
+/*!
+ \brief Define helper macro for populating processor container information.
+ \param PackageId Package instance number.
+ \param ClusterId Cluster instance number.
+*/
+#define PPTT_CLUSTER_INIT(PackageId, ClusterId) \
+ { \
+ /* Parameters for Cluster */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ OFFSET_OF (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ \
+ PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package), /* Parent */ \
+ ((PackageId << 4) | ClusterId), /* ACPI Id */ \
+ 0 /* Num of private resource */ \
+ ), \
+ \
+ /* Initialize child core */ \
+ { \
+ PPTT_CORE_INIT (PackageId, ClusterId, 0) \
+ } \
+ }
+
+#pragma pack(1)
+/*
+ * Processor Properties Topology Table
+ */
+typedef struct {
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ RD_PPTT_SLC_PACKAGE Package;
+} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+#pragma pack ()
+
+STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ )
+ },
+
+ {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (
+ OFFSET_OF (RD_PPTT_SLC_PACKAGE, Slc),
+ PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 1),
+
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ Package.Slc),
+
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT (
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */
+ 0, /* Next level of cache */
+ SIZE_32MB, /* Size */
+ 32768, /* Num of sets */
+ 16, /* Associativity */
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */
+ 64 /* Line size */
+ ),
+
+ {
+ PPTT_CLUSTER_INIT (0, 0),
+ PPTT_CLUSTER_INIT (0, 1),
+ PPTT_CLUSTER_INIT (0, 2),
+ PPTT_CLUSTER_INIT (0, 3),
+ PPTT_CLUSTER_INIT (0, 4),
+ PPTT_CLUSTER_INIT (0, 5),
+ PPTT_CLUSTER_INIT (0, 6),
+ PPTT_CLUSTER_INIT (0, 7),
+ PPTT_CLUSTER_INIT (0, 8),
+ PPTT_CLUSTER_INIT (0, 9),
+ PPTT_CLUSTER_INIT (0, 10),
+ PPTT_CLUSTER_INIT (0, 11),
+ PPTT_CLUSTER_INIT (0, 12),
+ PPTT_CLUSTER_INIT (0, 13),
+ PPTT_CLUSTER_INIT (0, 14),
+ PPTT_CLUSTER_INIT (0, 15)
+ }
+ }
+};
+
+/*
+ * Reference the table being generated to prevent the optimizer from removing
+ * the data structure from the executable
+ */
+VOID* CONST ReferenceAcpiTable = &Pptt;
--
2.17.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [edk2-platforms][PATCH V3 00/14] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms
2021-05-10 20:06 [edk2-platforms][PATCH V3 00/14] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms Pranav Madhu
` (13 preceding siblings ...)
2021-05-10 20:06 ` [edk2-platforms][PATCH V3 14/14] Platform/Sgi: ACPI PPTT table " Pranav Madhu
@ 2021-05-11 11:09 ` Sami Mujawar
2021-05-11 11:17 ` Pranav Madhu
2021-05-11 14:14 ` Sami Mujawar
15 siblings, 1 reply; 20+ messages in thread
From: Sami Mujawar @ 2021-05-11 11:09 UTC (permalink / raw)
To: Pranav Madhu, devel; +Cc: Ard Biesheuvel, Pierre Gondois, nd
Hi Pranav,
Comparing with the V2 series, I see that updates to the following files
or corresponding patches are missing in this series.
- RdV1Mc/Pptt.aslc
- RdN2/Pptt.aslc
Is this intentional?
Regards,
Sami Mujawar
On 10/05/2021 09:06 PM, Pranav Madhu wrote:
> Changes since V2:
> - Introduced CPU container object into DSDT
> - Addressed comments from Sami
>
> Changes since V1:
> - Rebase the patches on top of latest master branch
> - Addressed comments from Pierre
>
> Processor Properties Topology Table (PPTT) describes the topological
> structure of processors, and their shared resources such as caches.
> This patch series adds PPTT table for Arm's Neoverse Reference Design
> platforms.
>
> The first patch in this series adds helper macros for PPTT table, and
> the subsequent patches in this series adds PPTT table for Neoverse
> Reference Design platforms which is mandatory as per Arm SystemReady SR
> specification.
>
> Link to github branch with the patches in this series -
> https://github.com/Pranav-Madhu/edk2-platforms/tree/topics/rd_pptt
>
> Pranav Madhu (14):
> Platform/Sgi: Helper macros for PPTT Table
> Platform/Sgi: Add CPU container for SGI-575
> Platform/Sgi: ACPI PPTT table for SGI-575 platform
> Platform/Sgi: Add CPU container for RD-N1-Edge
> Platform/Sgi: ACPI PPTT table for RD-N1-Edge platform
> Platform/Sgi: Add DSDT ACPI table for RD-N1-Edge dual-chip platform
> Platform/Sgi: ACPI PPTT table for RD-N1-Edge dual-chip
> Platform/Sgi: ACPI PPTT table for RD-E1-Edge platform
> Platform/Sgi: Add CPU container for RD-V1 platform
> Platform/Sgi: ACPI PPTT Table for RD-V1 platform
> Platform/Sgi: Add CPU container for RD-V1 quad-chip platform
> Platform/Sgi: ACPI PPTT Table for RD-V1 quad-chip platform
> Platform/Sgi: Add CPU container for RD-N2 platform
> Platform/Sgi: ACPI PPTT table for RD-N2 platform
>
> .../SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf | 3 +-
> .../SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf | 3 +-
> .../AcpiTables/RdN1EdgeX2AcpiTables.inf | 3 +-
> .../ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 3 +-
> .../ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf | 3 +-
> .../SgiPkg/AcpiTables/RdV1McAcpiTables.inf | 1 +
> .../SgiPkg/AcpiTables/Sgi575AcpiTables.inf | 3 +-
> Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 170 ++++++++++++
> .../ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc | 252 ++++++++++++++++++
> .../ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl | 88 +++---
> .../ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc | 186 +++++++++++++
> .../ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl | 136 ++++++++++
> .../SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc | 207 ++++++++++++++
> Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl | 176 ++++++++----
> Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc | 175 ++++++++++++
> Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl | 176 ++++++++----
> Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc | 175 ++++++++++++
> .../ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl | 177 ++++++++----
> .../ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc | 184 +++++++++++++
> .../ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl | 99 +++----
> .../ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc | 172 ++++++++++++
> 21 files changed, 2156 insertions(+), 236 deletions(-)
> create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc
> create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc
> create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl
> create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc
> create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc
> create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc
> create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc
> create mode 100644 Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc
>
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [edk2-platforms][PATCH V3 00/14] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms
2021-05-11 11:09 ` [edk2-platforms][PATCH V3 00/14] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms Sami Mujawar
@ 2021-05-11 11:17 ` Pranav Madhu
0 siblings, 0 replies; 20+ messages in thread
From: Pranav Madhu @ 2021-05-11 11:17 UTC (permalink / raw)
To: Sami Mujawar, devel@edk2.groups.io; +Cc: Ard Biesheuvel, Pierre Gondois, nd
Hi Sami,
Please find my comments inline:
>
> Hi Pranav,
>
> Comparing with the V2 series, I see that updates to the following files or
> corresponding patches are missing in this series.
>
> - RdV1Mc/Pptt.aslc
> - RdN2/Pptt.aslc
>
> Is this intentional?
No
RdN2: https://edk2.groups.io/g/devel/message/74924
RdV1Mc: https://edk2.groups.io/g/devel/message/74922
>
> Regards,
>
> Sami Mujawar
>
> On 10/05/2021 09:06 PM, Pranav Madhu wrote:
> > Changes since V2:
> > - Introduced CPU container object into DSDT
> > - Addressed comments from Sami
<...>
Regards,
Pranav.
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [edk2-platforms][PATCH V3 00/14] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms
2021-05-10 20:06 [edk2-platforms][PATCH V3 00/14] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms Pranav Madhu
` (14 preceding siblings ...)
2021-05-11 11:09 ` [edk2-platforms][PATCH V3 00/14] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms Sami Mujawar
@ 2021-05-11 14:14 ` Sami Mujawar
15 siblings, 0 replies; 20+ messages in thread
From: Sami Mujawar @ 2021-05-11 14:14 UTC (permalink / raw)
To: Pranav Madhu, devel; +Cc: Ard Biesheuvel, Pierre Gondois, nd
Pushed as 67988fb53dbc..8549b1739183 with minor edits to doxygen comment
style.
Thanks.
Regards,
Sami Mujawar
On 10/05/2021 09:06 PM, Pranav Madhu wrote:
> Changes since V2:
> - Introduced CPU container object into DSDT
> - Addressed comments from Sami
>
> Changes since V1:
> - Rebase the patches on top of latest master branch
> - Addressed comments from Pierre
>
> Processor Properties Topology Table (PPTT) describes the topological
> structure of processors, and their shared resources such as caches.
> This patch series adds PPTT table for Arm's Neoverse Reference Design
> platforms.
>
> The first patch in this series adds helper macros for PPTT table, and
> the subsequent patches in this series adds PPTT table for Neoverse
> Reference Design platforms which is mandatory as per Arm SystemReady SR
> specification.
>
> Link to github branch with the patches in this series -
> https://github.com/Pranav-Madhu/edk2-platforms/tree/topics/rd_pptt
>
> Pranav Madhu (14):
> Platform/Sgi: Helper macros for PPTT Table
> Platform/Sgi: Add CPU container for SGI-575
> Platform/Sgi: ACPI PPTT table for SGI-575 platform
> Platform/Sgi: Add CPU container for RD-N1-Edge
> Platform/Sgi: ACPI PPTT table for RD-N1-Edge platform
> Platform/Sgi: Add DSDT ACPI table for RD-N1-Edge dual-chip platform
> Platform/Sgi: ACPI PPTT table for RD-N1-Edge dual-chip
> Platform/Sgi: ACPI PPTT table for RD-E1-Edge platform
> Platform/Sgi: Add CPU container for RD-V1 platform
> Platform/Sgi: ACPI PPTT Table for RD-V1 platform
> Platform/Sgi: Add CPU container for RD-V1 quad-chip platform
> Platform/Sgi: ACPI PPTT Table for RD-V1 quad-chip platform
> Platform/Sgi: Add CPU container for RD-N2 platform
> Platform/Sgi: ACPI PPTT table for RD-N2 platform
>
> .../SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf | 3 +-
> .../SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf | 3 +-
> .../AcpiTables/RdN1EdgeX2AcpiTables.inf | 3 +-
> .../ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 3 +-
> .../ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf | 3 +-
> .../SgiPkg/AcpiTables/RdV1McAcpiTables.inf | 1 +
> .../SgiPkg/AcpiTables/Sgi575AcpiTables.inf | 3 +-
> Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 170 ++++++++++++
> .../ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc | 252 ++++++++++++++++++
> .../ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl | 88 +++---
> .../ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc | 186 +++++++++++++
> .../ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl | 136 ++++++++++
> .../SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc | 207 ++++++++++++++
> Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl | 176 ++++++++----
> Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc | 175 ++++++++++++
> Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl | 176 ++++++++----
> Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc | 175 ++++++++++++
> .../ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl | 177 ++++++++----
> .../ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc | 184 +++++++++++++
> .../ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl | 99 +++----
> .../ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc | 172 ++++++++++++
> 21 files changed, 2156 insertions(+), 236 deletions(-)
> create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc
> create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc
> create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl
> create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc
> create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc
> create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc
> create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc
> create mode 100644 Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc
>
^ permalink raw reply [flat|nested] 20+ messages in thread