* [edk2-platforms][PATCH V2 00/11] Enable idle state and CPPC support for RD platform
@ 2021-05-11 7:47 Pranav Madhu
2021-05-11 7:47 ` [edk2-platforms][PATCH V2 01/11] Platform/Sgi: Macro definitions for ACPI _OSC Pranav Madhu
` (12 more replies)
0 siblings, 13 replies; 14+ messages in thread
From: Pranav Madhu @ 2021-05-11 7:47 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar
Changes since V1:
- Remove patches that add CPU container object into DSDT
- Addressed comments from Sami
Low Power Idle (LPI) and Collaborative Processor Performance Control
(CPPC) are two power management mechanisms described in ACPI 6.4
specification. OSPM uses the _LPI object to select a local power state
for each level of processor hierarchy in the system. Collaborative
processor performance control (CPPC) defines an abstracted and flexible
mechanism for OSPM to collaborate with an entity in the platform to
manage the performance of a processor. In this patch series, CPPC
support depends on the availability of Activity Monitor Unit (AMU)
extension for CPU performance monitoring as defined in the Arm v8.4
architecture reference manuals. So CPPC is supported for RD-V1 and
RD-N2 platforms.
This patch series adds LPI support for all the Neoverse reference
design platforms. CPPC support is added for RD-V1, RD-V1-MC and
RD-N2 platforms.
This patch series should be applied on top of the patch series
https://edk2.groups.io/g/devel/message/74924
Link to github branch with the patches in this series -
https://github.com/Pranav-Madhu/edk2-platforms/tree/topics/rd_power_management
Pranav Madhu (11):
Platform/Sgi: Macro definitions for ACPI _OSC
Platform/Sgi: Low Power Idle states for SGI-575
Platform/Sgi: Low Power Idle states for RD-N1-Edge
Platform/Sgi: Low Power Idle States for RD-N1-Edge dual-chip
Platform/Sgi: Low Power Idle states for RD-V1 platform
Platform/Sgi: Macro definitions for ACPI CPPC
Platform/Sgi: ACPI CPPC support for RD-V1
Platform/Sgi: Low Power Idle States for RD-V1 quad-chip platform
Platform/Sgi: ACPI CPPC support for RD-V1 quad-chip platform
Platform/Sgi: Low Power Idle States for RD-N2
Platform/Sgi: ACPI CPPC support for RD-N2
Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 90 +++++
.../ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl | 132 +++++++
.../ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl | 162 ++++++++
Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl | 364 ++++++++++++++++++
Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl | 294 ++++++++++++++
.../ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl | 306 +++++++++++++++
.../ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl | 132 +++++++
7 files changed, 1480 insertions(+)
--
2.17.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* [edk2-platforms][PATCH V2 01/11] Platform/Sgi: Macro definitions for ACPI _OSC
2021-05-11 7:47 [edk2-platforms][PATCH V2 00/11] Enable idle state and CPPC support for RD platform Pranav Madhu
@ 2021-05-11 7:47 ` Pranav Madhu
2021-05-11 7:47 ` [edk2-platforms][PATCH V2 02/11] Platform/Sgi: Low Power Idle states for SGI-575 Pranav Madhu
` (11 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Pranav Madhu @ 2021-05-11 7:47 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar
Add helper macros required for use with ACPI Operating System
Capabilities (_OSC) control method. The macros for capability DWORD and
return status value DWORD are defined.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
| 16 ++++++++++++++++
1 file changed, 16 insertions(+)
--git a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
index 23e6ee14a761..c23938fe3d4f 100644
--- a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
+++ b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
@@ -23,6 +23,22 @@
#define CORE_COUNT FixedPcdGet32 (PcdCoreCount)
#define CLUSTER_COUNT FixedPcdGet32 (PcdClusterCount)
+// ACPI OSC Status bits
+#define OSC_STS_BIT0_RES (1U << 0)
+#define OSC_STS_FAILURE (1U << 1)
+#define OSC_STS_UNRECOGNIZED_UUID (1U << 2)
+#define OSC_STS_UNRECOGNIZED_REV (1U << 3)
+#define OSC_STS_CAPABILITY_MASKED (1U << 4)
+#define OSC_STS_MASK (OSC_STS_BIT0_RES | \
+ OSC_STS_FAILURE | \
+ OSC_STS_UNRECOGNIZED_UUID | \
+ OSC_STS_UNRECOGNIZED_REV | \
+ OSC_STS_CAPABILITY_MASKED)
+
+// ACPI OSC for Platform-Wide Capability
+#define OSC_CAP_CPPC_SUPPORT (1U << 5)
+#define OSC_CAP_OS_INITIATED_LPI (1U << 8)
+
#pragma pack(1)
// PPTT processor core structure
typedef struct {
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [edk2-platforms][PATCH V2 02/11] Platform/Sgi: Low Power Idle states for SGI-575
2021-05-11 7:47 [edk2-platforms][PATCH V2 00/11] Enable idle state and CPPC support for RD platform Pranav Madhu
2021-05-11 7:47 ` [edk2-platforms][PATCH V2 01/11] Platform/Sgi: Macro definitions for ACPI _OSC Pranav Madhu
@ 2021-05-11 7:47 ` Pranav Madhu
2021-05-11 7:47 ` [edk2-platforms][PATCH V2 03/11] Platform/Sgi: Low Power Idle states for RD-N1-Edge Pranav Madhu
` (10 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Pranav Madhu @ 2021-05-11 7:47 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar
SGI-575 platform supports 2 LPI states, LPI1 (Standby WFI) and LPI3
(Power-down) and the cluster supports LPI2 (Power-down) state. The LPI
implementation also supports combined power state for core and cluster.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl | 132 ++++++++++++++++++++
1 file changed, 132 insertions(+)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl
index 7390849e6231..e879a681fabf 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl
@@ -12,61 +12,193 @@
DefinitionBlock("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", EFI_ACPI_ARM_OEM_REVISION) {
Scope(_SB) {
+ /* _OSC: Operating System Capabilities */
+ Method (_OSC, 4, Serialized) {
+ CreateDWordField (Arg3, 0x00, STS0)
+ CreateDWordField (Arg3, 0x04, CAP0)
+
+ /* Platform-wide Capabilities */
+ If (LEqual (Arg0, ToUUID("0811b06e-4a27-44f9-8d60-3cbbc22e7b48"))) {
+ /* OSC rev 1 supported, for other version, return failure */
+ If (LEqual (Arg1, One)) {
+ And (STS0, Not (OSC_STS_MASK), STS0)
+
+ If (And (CAP0, OSC_CAP_OS_INITIATED_LPI)) {
+ /* OS initiated LPI not supported */
+ And (CAP0, Not (OSC_CAP_OS_INITIATED_LPI), CAP0)
+ Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+ }
+ } Else {
+ And (STS0, Not (OSC_STS_MASK), STS0)
+ Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0)
+ }
+ } Else {
+ And (STS0, Not (OSC_STS_MASK), STS0)
+ Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_UUID), STS0)
+ }
+
+ Return (Arg3)
+ }
+
+ Name (CLPI, Package () { /* LPI for Cluster, support 1 LPI state */
+ 0, // Version
+ 0, // Level Index
+ 1, // Count
+ Package () { // Power Gating state for Cluster
+ 2500, // Min residency (uS)
+ 1150, // Wake latency (uS)
+ 1, // Flags
+ 1, // Arch Context Flags
+ 100, // Residency Counter Frequency
+ 0, // No Parent State
+ 0x00000020, // Integer Entry method
+ ResourceTemplate () { // Null Residency Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ ResourceTemplate () { // Null Usage Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ "LPI2-Cluster"
+ },
+ })
+
+ Name (PLPI, Package () { /* LPI for Processor, support 2 LPI states */
+ 0, // Version
+ 1, // Level Index
+ 2, // Count
+ Package () { // WFI for CPU
+ 1, // Min residency (uS)
+ 1, // Wake latency (uS)
+ 1, // Flags
+ 0, // Arch Context lost Flags (no loss)
+ 100, // Residency Counter Frequency
+ 0, // No parent state
+ ResourceTemplate () { // Register Entry method
+ Register (FFixedHW,
+ 32, // Bit Width
+ 0, // Bit Offset
+ 0xFFFFFFFF, // Address
+ 3, // Access Size
+ )
+ },
+ ResourceTemplate () { // Null Residency Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ ResourceTemplate () { // Null Usage Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ "LPI1-Core"
+ },
+ Package () { // Power Gating state for CPU
+ 150, // Min residency (uS)
+ 350, // Wake latency (uS)
+ 1, // Flags
+ 1, // Arch Context lost Flags (Core context lost)
+ 100, // Residency Counter Frequency
+ 1, // Parent node can be in any shallower state
+ ResourceTemplate () { // Register Entry method
+ Register (FFixedHW,
+ 32, // Bit Width
+ 0, // Bit Offset
+ 0x40000002, // Address (PwrLvl:core, StateTyp:PwrDn)
+ 3, // Access Size
+ )
+ },
+ ResourceTemplate () { // Null Residency Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ ResourceTemplate () { // Null Usage Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ "LPI3-Core"
+ },
+ })
+
Device (CLU0) { // Cluster 0
Name (_HID, "ACPI0010")
Name (_UID, 0)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.CLPI)
+ }
Device (CP00) { // A75-0: Cluster 0, Cpu 0
Name (_HID, "ACPI0007")
Name (_UID, 0)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
Device (CP01) { // A75-0: Cluster 0, Cpu 1
Name (_HID, "ACPI0007")
Name (_UID, 1)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
Device (CP02) { // A75-0: Cluster 0, Cpu 2
Name (_HID, "ACPI0007")
Name (_UID, 2)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
Device (CP03) { // A75-0: Cluster 0, Cpu 3
Name (_HID, "ACPI0007")
Name (_UID, 3)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
Device (CLU1) { // Cluster 1
Name (_HID, "ACPI0010")
Name (_UID, 1)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.CLPI)
+ }
Device (CP04) { // A75-0: Cluster 1, Cpu 0
Name (_HID, "ACPI0007")
Name (_UID, 4)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
Device (CP05) { // A75-0: Cluster 1, Cpu 1
Name (_HID, "ACPI0007")
Name (_UID, 5)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
Device (CP06) { // A75-0: Cluster 1, Cpu 2
Name (_HID, "ACPI0007")
Name (_UID, 6)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
Device (CP07) { // A75-0: Cluster 1, Cpu 3
Name (_HID, "ACPI0007")
Name (_UID, 7)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [edk2-platforms][PATCH V2 03/11] Platform/Sgi: Low Power Idle states for RD-N1-Edge
2021-05-11 7:47 [edk2-platforms][PATCH V2 00/11] Enable idle state and CPPC support for RD platform Pranav Madhu
2021-05-11 7:47 ` [edk2-platforms][PATCH V2 01/11] Platform/Sgi: Macro definitions for ACPI _OSC Pranav Madhu
2021-05-11 7:47 ` [edk2-platforms][PATCH V2 02/11] Platform/Sgi: Low Power Idle states for SGI-575 Pranav Madhu
@ 2021-05-11 7:47 ` Pranav Madhu
2021-05-11 7:47 ` [edk2-platforms][PATCH V2 04/11] Platform/Sgi: Low Power Idle States for RD-N1-Edge dual-chip Pranav Madhu
` (9 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Pranav Madhu @ 2021-05-11 7:47 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar
RD-N1-Edge platform supports 2 LPI states, LPI1 (Standby WFI) and LPI3
(Power-down) and the cluster supports LPI2 (Power-down) state. The LPI
implementation also supports combined power state for core and cluster.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl | 132 ++++++++++++++++++++
1 file changed, 132 insertions(+)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl
index b88344c3a7ba..a2258f61aeca 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl
@@ -13,61 +13,193 @@
DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
EFI_ACPI_ARM_OEM_REVISION) {
Scope (_SB) {
+ /* _OSC: Operating System Capabilities */
+ Method (_OSC, 4, Serialized) {
+ CreateDWordField (Arg3, 0x00, STS0)
+ CreateDWordField (Arg3, 0x04, CAP0)
+
+ /* Platform-wide Capabilities */
+ If (LEqual (Arg0, ToUUID("0811b06e-4a27-44f9-8d60-3cbbc22e7b48"))) {
+ /* OSC rev 1 supported, for other version, return failure */
+ If (LEqual (Arg1, One)) {
+ And (STS0, Not (OSC_STS_MASK), STS0)
+
+ If (And (CAP0, OSC_CAP_OS_INITIATED_LPI)) {
+ /* OS initiated LPI not supported */
+ And (CAP0, Not (OSC_CAP_OS_INITIATED_LPI), CAP0)
+ Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+ }
+ } Else {
+ And (STS0, Not (OSC_STS_MASK), STS0)
+ Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0)
+ }
+ } Else {
+ And (STS0, Not (OSC_STS_MASK), STS0)
+ Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_UUID), STS0)
+ }
+
+ Return (Arg3)
+ }
+
+ Name (CLPI, Package () { /* LPI for Cluster, support 1 LPI state */
+ 0, // Version
+ 0, // Level Index
+ 1, // Count
+ Package () { // Power Gating state for Cluster
+ 2500, // Min residency (uS)
+ 1150, // Wake latency (uS)
+ 1, // Flags
+ 1, // Arch Context Flags
+ 100, // Residency Counter Frequency
+ 0, // No Parent State
+ 0x00000020, // Integer Entry method
+ ResourceTemplate () { // Null Residency Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ ResourceTemplate () { // Null Usage Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ "LPI2-Cluster"
+ },
+ })
+
+ Name (PLPI, Package () { /* LPI for Processor, support 2 LPI states */
+ 0, // Version
+ 1, // Level Index
+ 2, // Count
+ Package () { // WFI for CPU
+ 1, // Min residency (uS)
+ 1, // Wake latency (uS)
+ 1, // Flags
+ 0, // Arch Context lost Flags (no loss)
+ 100, // Residency Counter Frequency
+ 0, // No parent state
+ ResourceTemplate () { // Register Entry method
+ Register (FFixedHW,
+ 32, // Bit Width
+ 0, // Bit Offset
+ 0xFFFFFFFF, // Address
+ 3, // Access Size
+ )
+ },
+ ResourceTemplate () { // Null Residency Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ ResourceTemplate () { // Null Usage Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ "LPI1-Core"
+ },
+ Package () { // Power Gating state for CPU
+ 150, // Min residency (uS)
+ 350, // Wake latency (uS)
+ 1, // Flags
+ 1, // Arch Context lost Flags (Core context lost)
+ 100, // Residency Counter Frequency
+ 1, // Parent node can be in any shallower state
+ ResourceTemplate () { // Register Entry method
+ Register (FFixedHW,
+ 32, // Bit Width
+ 0, // Bit Offset
+ 0x40000002, // Address (PwrLvl:core, StateTyp:PwrDn)
+ 3, // Access Size
+ )
+ },
+ ResourceTemplate () { // Null Residency Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ ResourceTemplate () { // Null Usage Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ "LPI3-Core"
+ },
+ })
+
Device (CLU0) { // Cluster 0
Name (_HID, "ACPI0010")
Name (_UID, 0)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.CLPI)
+ }
Device (CP00) { // Neoverse-N1: Cluster 0, Cpu 0
Name (_HID, "ACPI0007")
Name (_UID, 0)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
Device (CP01) { // Neoverse-N1: Cluster 0, Cpu 1
Name (_HID, "ACPI0007")
Name (_UID, 1)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
Device (CP02) { // Neoverse-N1: Cluster 0, Cpu 2
Name (_HID, "ACPI0007")
Name (_UID, 2)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
Device (CP03) { // Neoverse-N1: Cluster 0, Cpu 3
Name (_HID, "ACPI0007")
Name (_UID, 3)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
Device (CLU1) { // Cluster 1
Name (_HID, "ACPI0010")
Name (_UID, 1)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.CLPI)
+ }
Device (CP04) { // Neoverse-N1: Cluster 1, Cpu 0
Name (_HID, "ACPI0007")
Name (_UID, 4)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
Device (CP05) { // Neoverse-N1: Cluster 1, Cpu 1
Name (_HID, "ACPI0007")
Name (_UID, 5)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
Device (CP06) { // Neoverse-N1: Cluster 1, Cpu 2
Name (_HID, "ACPI0007")
Name (_UID, 6)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
Device (CP07) { // Neoverse-N1: Cluster 1, Cpu 3
Name (_HID, "ACPI0007")
Name (_UID, 7)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
} // Scope(_SB)
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [edk2-platforms][PATCH V2 04/11] Platform/Sgi: Low Power Idle States for RD-N1-Edge dual-chip
2021-05-11 7:47 [edk2-platforms][PATCH V2 00/11] Enable idle state and CPPC support for RD platform Pranav Madhu
` (2 preceding siblings ...)
2021-05-11 7:47 ` [edk2-platforms][PATCH V2 03/11] Platform/Sgi: Low Power Idle states for RD-N1-Edge Pranav Madhu
@ 2021-05-11 7:47 ` Pranav Madhu
2021-05-11 7:47 ` [edk2-platforms][PATCH V2 05/11] Platform/Sgi: Low Power Idle states for RD-V1 platform Pranav Madhu
` (8 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Pranav Madhu @ 2021-05-11 7:47 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar
RD-N1-Edge platform in multi chip configuration supports 2 LPI states,
LPI1 (Standby WFI) and LPI3 (Power-down). The cluster supports LPI2
(Power-down) state. The LPI implementation also supports combined power
state for core and cluster.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl | 162 ++++++++++++++++++++
1 file changed, 162 insertions(+)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl
index 2379f20a79ef..5807658e7815 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl
@@ -15,62 +15,194 @@
DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
EFI_ACPI_ARM_OEM_REVISION) {
Scope (_SB) {
+ /* _OSC: Operating System Capabilities */
+ Method (_OSC, 4, Serialized) {
+ CreateDWordField (Arg3, 0x00, STS0)
+ CreateDWordField (Arg3, 0x04, CAP0)
+
+ /* Platform-wide Capabilities */
+ If (LEqual (Arg0, ToUUID("0811b06e-4a27-44f9-8d60-3cbbc22e7b48"))) {
+ /* OSC rev 1 supported, for other version, return failure */
+ If (LEqual (Arg1, One)) {
+ And (STS0, Not (OSC_STS_MASK), STS0)
+
+ If (And (CAP0, OSC_CAP_OS_INITIATED_LPI)) {
+ /* OS initiated LPI not supported */
+ And (CAP0, Not (OSC_CAP_OS_INITIATED_LPI), CAP0)
+ Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+ }
+ } Else {
+ And (STS0, Not (OSC_STS_MASK), STS0)
+ Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0)
+ }
+ } Else {
+ And (STS0, Not (OSC_STS_MASK), STS0)
+ Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_UUID), STS0)
+ }
+
+ Return (Arg3)
+ }
+
+ Name (CLPI, Package () { /* LPI for Cluster, support 1 LPI state */
+ 0, // Version
+ 0, // Level Index
+ 1, // Count
+ Package () { // Power Gating state for Cluster
+ 2500, // Min residency (uS)
+ 1150, // Wake latency (uS)
+ 1, // Flags
+ 1, // Arch Context Flags
+ 100, // Residency Counter Frequency
+ 0, // No Parent State
+ 0x00000020, // Integer Entry method
+ ResourceTemplate () { // Null Residency Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ ResourceTemplate () { // Null Usage Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ "LPI2-Cluster"
+ },
+ })
+
+ Name (PLPI, Package () { /* LPI for Processor, support 2 LPI states */
+ 0, // Version
+ 1, // Level Index
+ 2, // Count
+ Package () { // WFI for CPU
+ 1, // Min residency (uS)
+ 1, // Wake latency (uS)
+ 1, // Flags
+ 0, // Arch Context lost Flags (no loss)
+ 100, // Residency Counter Frequency
+ 0, // No parent state
+ ResourceTemplate () { // Register Entry method
+ Register (FFixedHW,
+ 32, // Bit Width
+ 0, // Bit Offset
+ 0xFFFFFFFF, // Address
+ 3, // Access Size
+ )
+ },
+ ResourceTemplate () { // Null Residency Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ ResourceTemplate () { // Null Usage Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ "LPI1-Core"
+ },
+ Package () { // Power Gating state for CPU
+ 150, // Min residency (uS)
+ 350, // Wake latency (uS)
+ 1, // Flags
+ 1, // Arch Context lost Flags (Core context lost)
+ 100, // Residency Counter Frequency
+ 1, // Parent node can be in any shallower state
+ ResourceTemplate () { // Register Entry method
+ Register (FFixedHW,
+ 32, // Bit Width
+ 0, // Bit Offset
+ 0x40000002, // Address (PwrLvl:core, StateTyp:PwrDn)
+ 3, // Access Size
+ )
+ },
+ ResourceTemplate () { // Null Residency Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ ResourceTemplate () { // Null Usage Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ "LPI3-Core"
+ },
+ })
+
/* Chip 0 CPUs */
Device (CLU0) { // Cluster 0
Name (_HID, "ACPI0010")
Name (_UID, 0)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.CLPI)
+ }
Device (CP00) { // Neoverse-N1: Cluster 0, Cpu 0
Name (_HID, "ACPI0007")
Name (_UID, 0)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
Device (CP01) { // Neoverse-N1: Cluster 0, Cpu 1
Name (_HID, "ACPI0007")
Name (_UID, 1)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
Device (CP02) { // Neoverse-N1: Cluster 0, Cpu 2
Name (_HID, "ACPI0007")
Name (_UID, 2)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
Device (CP03) { // Neoverse-N1: Cluster 0, Cpu 3
Name (_HID, "ACPI0007")
Name (_UID, 3)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
Device (CLU1) { // Cluster 1
Name (_HID, "ACPI0010")
Name (_UID, 1)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.CLPI)
+ }
Device (CP04) { // Neoverse-N1: Cluster 1, Cpu 0
Name (_HID, "ACPI0007")
Name (_UID, 4)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
Device (CP05) { // Neoverse-N1: Cluster 1, Cpu 1
Name (_HID, "ACPI0007")
Name (_UID, 5)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
Device (CP06) { // Neoverse-N1: Cluster 1, Cpu 2
Name (_HID, "ACPI0007")
Name (_UID, 6)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
Device (CP07) { // Neoverse-N1: Cluster 1, Cpu 3
Name (_HID, "ACPI0007")
Name (_UID, 7)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
@@ -78,58 +210,88 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Device (CLU2) { // Cluster 2
Name (_HID, "ACPI0010")
Name (_UID, 2)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.CLPI)
+ }
Device (CP08) { // Neoverse-N1: Cluster 2, Cpu 0
Name (_HID, "ACPI0007")
Name (_UID, 8)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
Device (CP09) { // Neoverse-N1: Cluster 2, Cpu 1
Name (_HID, "ACPI0007")
Name (_UID, 9)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
Device (CP10) { // Neoverse-N1: Cluster 2, Cpu 2
Name (_HID, "ACPI0007")
Name (_UID, 10)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
Device (CP11) { // Neoverse-N1: Cluster 2, Cpu 3
Name (_HID, "ACPI0007")
Name (_UID, 11)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
Device (CLU3) { // Cluster 3
Name (_HID, "ACPI0010")
Name (_UID, 3)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.CLPI)
+ }
Device (CP12) { // Neoverse-N1: Cluster 3, Cpu 0
Name (_HID, "ACPI0007")
Name (_UID, 12)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
Device (CP13) { // Neoverse-N1: Cluster 3, Cpu 1
Name (_HID, "ACPI0007")
Name (_UID, 13)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
Device (CP14) { // Neoverse-N1: Cluster 3, Cpu 2
Name (_HID, "ACPI0007")
Name (_UID, 14)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
Device (CP15) { // Neoverse-N1: Cluster 3, Cpu 3
Name (_HID, "ACPI0007")
Name (_UID, 15)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
} // Scope(_SB)
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [edk2-platforms][PATCH V2 05/11] Platform/Sgi: Low Power Idle states for RD-V1 platform
2021-05-11 7:47 [edk2-platforms][PATCH V2 00/11] Enable idle state and CPPC support for RD platform Pranav Madhu
` (3 preceding siblings ...)
2021-05-11 7:47 ` [edk2-platforms][PATCH V2 04/11] Platform/Sgi: Low Power Idle States for RD-N1-Edge dual-chip Pranav Madhu
@ 2021-05-11 7:47 ` Pranav Madhu
2021-05-11 7:47 ` [edk2-platforms][PATCH V2 06/11] Platform/Sgi: Macro definitions for ACPI CPPC Pranav Madhu
` (7 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Pranav Madhu @ 2021-05-11 7:47 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar
RD-V1 platform supports 2 LPI states, LPI1 (Standby WFI) and LPI3
(Power-down). Add idle support for RD-V1 platform.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl | 128 ++++++++++++++++++++
1 file changed, 128 insertions(+)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl
index 05e8601290e2..fe33b74e3a5b 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl
@@ -13,6 +13,86 @@
DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
EFI_ACPI_ARM_OEM_REVISION) {
Scope (_SB) {
+ /* _OSC: Operating System Capabilities */
+ Method (_OSC, 4, Serialized) {
+ CreateDWordField (Arg3, 0x00, STS0)
+ CreateDWordField (Arg3, 0x04, CAP0)
+
+ /* Platform-wide Capabilities */
+ If (LEqual (Arg0, ToUUID("0811b06e-4a27-44f9-8d60-3cbbc22e7b48"))) {
+ /* OSC rev 1 supported, for other version, return failure */
+ If (LEqual (Arg1, One)) {
+ And (STS0, Not (OSC_STS_MASK), STS0)
+
+ If (And (CAP0, OSC_CAP_OS_INITIATED_LPI)) {
+ /* OS initiated LPI not supported */
+ And (CAP0, Not (OSC_CAP_OS_INITIATED_LPI), CAP0)
+ Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+ }
+ } Else {
+ And (STS0, Not (OSC_STS_MASK), STS0)
+ Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0)
+ }
+ } Else {
+ And (STS0, Not (OSC_STS_MASK), STS0)
+ Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_UUID), STS0)
+ }
+
+ Return (Arg3)
+ }
+
+ Name (PLPI, Package () { /* LPI for Processor, support 2 LPI states */
+ 0, // Version
+ 1, // Level Index
+ 2, // Count
+ Package () { // WFI for CPU
+ 1, // Min residency (uS)
+ 1, // Wake latency (uS)
+ 1, // Flags
+ 0, // Arch Context lost Flags (no loss)
+ 100, // Residency Counter Frequency
+ 0, // No parent state
+ ResourceTemplate () { // Register Entry method
+ Register (FFixedHW,
+ 32, // Bit Width
+ 0, // Bit Offset
+ 0xFFFFFFFF, // Address
+ 3, // Access Size
+ )
+ },
+ ResourceTemplate () { // Null Residency Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ ResourceTemplate () { // Null Usage Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ "LPI1-Core"
+ },
+ Package () { // Power Gating state for CPU
+ 150, // Min residency (uS)
+ 350, // Wake latency (uS)
+ 1, // Flags
+ 1, // Arch Context lost Flags (Core context lost)
+ 100, // Residency Counter Frequency
+ 1, // Parent node can be in any shallower state
+ ResourceTemplate () { // Register Entry method
+ Register (FFixedHW,
+ 32, // Bit Width
+ 0, // Bit Offset
+ 0x40000002, // Address (PwrLvl:core, StateTyp:PwrDn)
+ 3, // Access Size
+ )
+ },
+ ResourceTemplate () { // Null Residency Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ ResourceTemplate () { // Null Usage Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ "LPI3-Core"
+ },
+ })
+
Device (CL00) { // Cluster 0
Name (_HID, "ACPI0010")
Name (_UID, 0)
@@ -21,6 +101,9 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 0)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
@@ -32,6 +115,9 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 1)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
@@ -43,6 +129,9 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 2)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
@@ -54,6 +143,9 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 3)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
@@ -65,6 +157,9 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 4)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
@@ -76,6 +171,9 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 5)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
@@ -87,6 +185,9 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 6)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
@@ -98,6 +199,9 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 7)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
@@ -109,6 +213,9 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 8)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
@@ -120,6 +227,9 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 9)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
@@ -131,6 +241,9 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 10)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
@@ -142,6 +255,9 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 11)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
@@ -153,6 +269,9 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 12)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
@@ -164,6 +283,9 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 13)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
@@ -175,6 +297,9 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 14)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
@@ -186,6 +311,9 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 15)
Name (_STA, 0xF)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
} // Scope(_SB)
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [edk2-platforms][PATCH V2 06/11] Platform/Sgi: Macro definitions for ACPI CPPC
2021-05-11 7:47 [edk2-platforms][PATCH V2 00/11] Enable idle state and CPPC support for RD platform Pranav Madhu
` (4 preceding siblings ...)
2021-05-11 7:47 ` [edk2-platforms][PATCH V2 05/11] Platform/Sgi: Low Power Idle states for RD-V1 platform Pranav Madhu
@ 2021-05-11 7:47 ` Pranav Madhu
2021-05-11 7:47 ` [edk2-platforms][PATCH V2 07/11] Platform/Sgi: ACPI CPPC support for RD-V1 Pranav Madhu
` (6 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Pranav Madhu @ 2021-05-11 7:47 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar
Add helper macros required for use with ACPI collaborative processor
performance control (CPPC). This patch adds macros for initializing ACPI
_CPC and _PSD control method. The CPC initializer macro initializes _CPC
control method with revision 3 as specified in Arm FFH specification
1.1. The CPC initilizer exposes the reference performance counter and
delivered perfrmance counter (AMU registers) as FFixedHW registers. The
initilizer also expose the fastchannel memories for performance level
set performance limit set protocols as desired performance register and
performance limited register respectively.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
| 74 ++++++++++++++++++++
1 file changed, 74 insertions(+)
--git a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
index c23938fe3d4f..7b8c16b172c0 100644
--- a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
+++ b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
@@ -432,4 +432,78 @@ typedef struct {
LineSize /* Line size in bytes */ \
}
+/** Helper macro for CPPC _CPC object initialization. Use of this macro is
+ restricted to ASL file and not to TDL file.
+
+ @param [in] DesiredPerfReg Fastchannel address for desired performance
+ register.
+ @param [in] PerfLimitedReg Fastchannel address for performance limited
+ register.
+ @param [in] GranularityMHz Granularity of the performance scale.
+ @param [in] HighestPerf Highest performance in linear scale.
+ @param [in] NominalPerf Nominal performance in linear scale.
+ @param [in] LowestNonlinearPerf Lowest non-linear performnce in linear
+ scale.
+ @param [in] LowestPerf Lowest performance in linear scale.
+ @param [in] RefPerf Reference performance in linear scale.
+**/
+#define CPPC_PACKAGE_INIT(DesiredPerfReg, PerfLimitedReg, GranularityMHz, \
+ HighestPerf, NominalPerf, LowestNonlinearPerf, LowestPerf, RefPerf) \
+ { \
+ 23, /* NumEntries */ \
+ 3, /* Revision */ \
+ HighestPerf, /* Highest Performance */ \
+ NominalPerf, /* Nominal Performance */ \
+ LowestNonlinearPerf, /* Lowest Nonlinear Performance */ \
+ LowestPerf, /* Lowest Performance */ \
+ /* Guaranteed Performance Register */ \
+ ResourceTemplate () { Register (SystemMemory, 0, 0, 0, 0) }, \
+ /* Desired Performance Register */ \
+ ResourceTemplate () { Register (SystemMemory, 32, 0, DesiredPerfReg, 3) }, \
+ /* Minimum Performance Register */ \
+ ResourceTemplate () { Register (SystemMemory, 0, 0, 0, 0) }, \
+ /* Maximum Performance Register */ \
+ ResourceTemplate () { Register (SystemMemory, 0, 0, 0, 0) }, \
+ /* Performance Reduction Tolerance Register */ \
+ ResourceTemplate () { Register (SystemMemory, 0, 0, 0, 0) }, \
+ /* Time Window Register */ \
+ ResourceTemplate () { Register (SystemMemory, 0, 0, 0, 0) }, \
+ /* Counter Wraparound Time */ \
+ ResourceTemplate () { Register (SystemMemory, 0, 0, 0, 0) }, \
+ /* Reference Performance Counter Register */ \
+ ResourceTemplate () { Register (FFixedHW, 64, 0, 1, 4) }, \
+ /* Delivered Performance Counter Register */ \
+ ResourceTemplate () { Register (FFixedHW, 64, 0, 0, 4) }, \
+ /* Performance Limited Register */ \
+ ResourceTemplate () { Register (SystemMemory, 32, 0, PerfLimitedReg, 3) }, \
+ /* CPPC Enable Register */ \
+ ResourceTemplate () { Register (SystemMemory, 0, 0, 0, 0) }, \
+ /* Autonomous Selection Enable Register */ \
+ ResourceTemplate () { Register (SystemMemory, 0, 0, 0, 0) }, \
+ /* Autonomous Activity Window Register */ \
+ ResourceTemplate () { Register (SystemMemory, 0, 0, 0, 0) }, \
+ /* Energy Performance Preference Register */ \
+ ResourceTemplate () { Register (SystemMemory, 0, 0, 0, 0) }, \
+ RefPerf, /* Reference Performance */ \
+ (LowestPerf * GranularityMHz), /* Lowest Frequency */ \
+ (NominalPerf * GranularityMHz), /* Nominal Frequency */ \
+ }
+
+// Power state dependancy (_PSD) for CPPC
+
+/** Helper macro to initialize Power state dependancy (_PSD) object required
+ for CPPC. Use of this macro is restricted to ASL file and not to TDL file.
+
+ @param [in] Domain The dependency domain number to which this
+ P-state entry belongs.
+**/
+#define PSD_INIT(Domain) \
+ { \
+ 5, /* Entries */ \
+ 0, /* Revision */ \
+ Domain, /* Domain */ \
+ 0xFD, /* Coord Type- SW_ANY */ \
+ 1 /* Processors */ \
+ }
+
#endif /* __SGI_ACPI_HEADER__ */
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [edk2-platforms][PATCH V2 07/11] Platform/Sgi: ACPI CPPC support for RD-V1
2021-05-11 7:47 [edk2-platforms][PATCH V2 00/11] Enable idle state and CPPC support for RD platform Pranav Madhu
` (5 preceding siblings ...)
2021-05-11 7:47 ` [edk2-platforms][PATCH V2 06/11] Platform/Sgi: Macro definitions for ACPI CPPC Pranav Madhu
@ 2021-05-11 7:47 ` Pranav Madhu
2021-05-11 7:47 ` [edk2-platforms][PATCH V2 08/11] Platform/Sgi: Low Power Idle States for RD-V1 quad-chip platform Pranav Madhu
` (5 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Pranav Madhu @ 2021-05-11 7:47 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar
Enable CPPC mechanism for RD-V1 platform as defined by the ACPI
specification. The implementation uses AMU registers accessible as
Fixed-feature Hardware (FFixedHW) for monitoring the performance.
Non-secure SCMI fastchannels are used to communicate with SCP to set
the desired performance. RD-V1 platform does not support CPPC revision
1 and below. So update the _OSC method to let OSPM know about this fact.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl | 166 ++++++++++++++++++++
1 file changed, 166 insertions(+)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl
index fe33b74e3a5b..0f632673d050 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl
@@ -29,6 +29,12 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
And (CAP0, Not (OSC_CAP_OS_INITIATED_LPI), CAP0)
Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
}
+
+ If (And (CAP0, OSC_CAP_CPPC_SUPPORT)) {
+ /* CPPC revision 1 and below not supported */
+ And (CAP0, Not (OSC_CAP_CPPC_SUPPORT), CAP0)
+ Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+ }
} Else {
And (STS0, Not (OSC_STS_MASK), STS0)
Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0)
@@ -101,6 +107,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 0)
Name (_STA, 0xF)
+
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000500, 0x06000504, 20, 130, 130, 65, 65, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (0)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -115,6 +131,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 1)
Name (_STA, 0xF)
+
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000518, 0x0600051C, 20, 130, 130, 65, 65, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (1)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -129,6 +155,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 2)
Name (_STA, 0xF)
+
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000530, 0x06000534, 20, 130, 130, 65, 65, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (2)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -143,6 +179,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 3)
Name (_STA, 0xF)
+
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000548, 0x0600054C, 20, 130, 130, 65, 65, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (3)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -157,6 +203,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 4)
Name (_STA, 0xF)
+
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000560, 0x06000564, 20, 130, 130, 65, 65, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (4)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -171,6 +227,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 5)
Name (_STA, 0xF)
+
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000578, 0x0600057C, 20, 130, 130, 65, 65, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (5)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -185,6 +251,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 6)
Name (_STA, 0xF)
+
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000590, 0x06000594, 20, 130, 130, 65, 65, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (6)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -199,6 +275,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 7)
Name (_STA, 0xF)
+
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x060005A8, 0x060005AC, 20, 130, 130, 65, 65, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (7)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -213,6 +299,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 8)
Name (_STA, 0xF)
+
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x060005C0, 0x060005C4, 20, 130, 130, 65, 65, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (8)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -227,6 +323,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 9)
Name (_STA, 0xF)
+
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x060005D8, 0x060005DC, 20, 130, 130, 65, 65, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (9)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -241,6 +347,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 10)
Name (_STA, 0xF)
+
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x060005F0, 0x060005F4, 20, 130, 130, 65, 65, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (10)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -255,6 +371,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 11)
Name (_STA, 0xF)
+
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000608, 0x0600060C, 20, 130, 130, 65, 65, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (11)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -269,6 +395,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 12)
Name (_STA, 0xF)
+
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000620, 0x06000624, 20, 130, 130, 65, 65, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (12)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -283,6 +419,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 13)
Name (_STA, 0xF)
+
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000638, 0x0600063C, 20, 130, 130, 65, 65, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (13)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -297,6 +443,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 14)
Name (_STA, 0xF)
+
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000650, 0x06000654, 20, 130, 130, 65, 65, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (14)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -311,6 +467,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 15)
Name (_STA, 0xF)
+
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000668, 0x0600066C, 20, 130, 130, 65, 65, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (15)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [edk2-platforms][PATCH V2 08/11] Platform/Sgi: Low Power Idle States for RD-V1 quad-chip platform
2021-05-11 7:47 [edk2-platforms][PATCH V2 00/11] Enable idle state and CPPC support for RD platform Pranav Madhu
` (6 preceding siblings ...)
2021-05-11 7:47 ` [edk2-platforms][PATCH V2 07/11] Platform/Sgi: ACPI CPPC support for RD-V1 Pranav Madhu
@ 2021-05-11 7:47 ` Pranav Madhu
2021-05-11 7:47 ` [edk2-platforms][PATCH V2 09/11] Platform/Sgi: ACPI CPPC support " Pranav Madhu
` (4 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Pranav Madhu @ 2021-05-11 7:47 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar
RD-V1 quad-chip platform supports two LPI states, LPI1 (Standby WFI) and
LPI3 (Power-down). Add idle support for RD-V1 quad-chip platform.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl | 144 ++++++++++++++++++++
1 file changed, 144 insertions(+)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl
index 16919cc5aaa0..82eb91638426 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl
@@ -13,6 +13,86 @@
DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
EFI_ACPI_ARM_OEM_REVISION) {
Scope (_SB) {
+ /* _OSC: Operating System Capabilities */
+ Method (_OSC, 4, Serialized) {
+ CreateDWordField (Arg3, 0x00, STS0)
+ CreateDWordField (Arg3, 0x04, CAP0)
+
+ /* Platform-wide Capabilities */
+ If (LEqual (Arg0, ToUUID("0811b06e-4a27-44f9-8d60-3cbbc22e7b48"))) {
+ /* OSC rev 1 supported, for other version, return failure */
+ If (LEqual (Arg1, One)) {
+ And (STS0, Not (OSC_STS_MASK), STS0)
+
+ If (And (CAP0, OSC_CAP_OS_INITIATED_LPI)) {
+ /* OS initiated LPI not supported */
+ And (CAP0, Not (OSC_CAP_OS_INITIATED_LPI), CAP0)
+ Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+ }
+ } Else {
+ And (STS0, Not (OSC_STS_MASK), STS0)
+ Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0)
+ }
+ } Else {
+ And (STS0, Not (OSC_STS_MASK), STS0)
+ Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_UUID), STS0)
+ }
+
+ Return (Arg3)
+ }
+
+ Name (PLPI, Package () { /* LPI for Processor, support 2 LPI states */
+ 0, // Version
+ 1, // Level Index
+ 2, // Count
+ Package () { // WFI for CPU
+ 1, // Min residency (uS)
+ 1, // Wake latency (uS)
+ 1, // Flags
+ 0, // Arch Context lost Flags (no loss)
+ 100, // Residency Counter Frequency
+ 0, // No parent state
+ ResourceTemplate () { // Register Entry method
+ Register (FFixedHW,
+ 32, // Bit Width
+ 0, // Bit Offset
+ 0xFFFFFFFF, // Address
+ 3, // Access Size
+ )
+ },
+ ResourceTemplate () { // Null Residency Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ ResourceTemplate () { // Null Usage Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ "LPI1-Core"
+ },
+ Package () { // Power Gating state for CPU
+ 150, // Min residency (uS)
+ 350, // Wake latency (uS)
+ 1, // Flags
+ 1, // Arch Context lost Flags (Core context lost)
+ 100, // Residency Counter Frequency
+ 1, // Parent node can be in any shallower state
+ ResourceTemplate () { // Register Entry method
+ Register (FFixedHW,
+ 32, // Bit Width
+ 0, // Bit Offset
+ 0x40000002, // Address (PwrLvl:core, StateTyp:PwrDn)
+ 3, // Access Size
+ )
+ },
+ ResourceTemplate () { // Null Residency Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ ResourceTemplate () { // Null Usage Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ "LPI3-Core"
+ },
+ })
+
Device (CL00) { // Cluster 0
Name (_HID, "ACPI0010")
Name (_UID, 0)
@@ -21,6 +101,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 0)
Name (_STA, 0xF)
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
@@ -32,6 +116,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 1)
Name (_STA, 0xF)
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
@@ -43,6 +131,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 2)
Name (_STA, 0xF)
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
@@ -54,6 +146,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 3)
Name (_STA, 0xF)
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
@@ -65,6 +161,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 4)
Name (_STA, 0xF)
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
@@ -76,6 +176,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 5)
Name (_STA, 0xF)
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
@@ -87,6 +191,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 6)
Name (_STA, 0xF)
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
@@ -98,6 +206,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 7)
Name (_STA, 0xF)
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
@@ -109,6 +221,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 8)
Name (_STA, 0xF)
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
@@ -120,6 +236,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 9)
Name (_STA, 0xF)
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
@@ -131,6 +251,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 10)
Name (_STA, 0xF)
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
@@ -142,6 +266,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 11)
Name (_STA, 0xF)
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
@@ -153,6 +281,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 12)
Name (_STA, 0xF)
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
@@ -164,6 +296,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 13)
Name (_STA, 0xF)
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
@@ -175,6 +311,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 14)
Name (_STA, 0xF)
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
@@ -186,6 +326,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_HID, "ACPI0007")
Name (_UID, 15)
Name (_STA, 0xF)
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
} // Scope(_SB)
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [edk2-platforms][PATCH V2 09/11] Platform/Sgi: ACPI CPPC support for RD-V1 quad-chip platform
2021-05-11 7:47 [edk2-platforms][PATCH V2 00/11] Enable idle state and CPPC support for RD platform Pranav Madhu
` (7 preceding siblings ...)
2021-05-11 7:47 ` [edk2-platforms][PATCH V2 08/11] Platform/Sgi: Low Power Idle States for RD-V1 quad-chip platform Pranav Madhu
@ 2021-05-11 7:47 ` Pranav Madhu
2021-05-11 7:47 ` [edk2-platforms][PATCH V2 10/11] Platform/Sgi: Low Power Idle States for RD-N2 Pranav Madhu
` (3 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Pranav Madhu @ 2021-05-11 7:47 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar
Enable ACPI CPPC mechanism for RD-V1 quad-chip platform as defined by
the ACPI specification. The implementation uses AMU registers accessible
as Fixed-feature Hardware (FFixedHW) for monitoring the performance.
Non-secure SCMI fastchannels are used to communicate with SCP to set the
desired performance. RD-V1 quad-chip platform does not support CPPC
revision 1 and below. So update the _OSC method to let OSPM know about
this fact.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl | 162 ++++++++++++++++++++
1 file changed, 162 insertions(+)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl
index 82eb91638426..622d522532a3 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl
@@ -29,6 +29,12 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
And (CAP0, Not (OSC_CAP_OS_INITIATED_LPI), CAP0)
Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
}
+
+ If (And (CAP0, OSC_CAP_CPPC_SUPPORT)) {
+ /* CPPC revision 1 and below not supported */
+ And (CAP0, Not (OSC_CAP_CPPC_SUPPORT), CAP0)
+ Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+ }
} Else {
And (STS0, Not (OSC_STS_MASK), STS0)
Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0)
@@ -102,6 +108,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_UID, 0)
Name (_STA, 0xF)
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000500, 0x06000504, 20, 130, 130, 65, 65, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (0)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -117,6 +132,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_UID, 1)
Name (_STA, 0xF)
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000518, 0x0600051C, 20, 130, 130, 65, 65, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (1)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -132,6 +156,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_UID, 2)
Name (_STA, 0xF)
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000530, 0x06000534, 20, 130, 130, 65, 65, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (2)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -147,6 +180,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_UID, 3)
Name (_STA, 0xF)
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000548, 0x0600054C, 20, 130, 130, 65, 65, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (3)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -162,6 +204,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_UID, 4)
Name (_STA, 0xF)
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x040006000500, 0x040006000504, 20, 130, 130, 65,
+ 65, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (4)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -177,6 +229,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_UID, 5)
Name (_STA, 0xF)
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x040006000518, 0x04000600051C, 20, 130, 130, 65,
+ 65, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (5)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -192,6 +254,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_UID, 6)
Name (_STA, 0xF)
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x040006000530, 0x040006000534, 20, 130, 130, 65,
+ 65, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (6)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -207,6 +279,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_UID, 7)
Name (_STA, 0xF)
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x040006000548, 0x04000600054C, 20, 130, 130, 65,
+ 65, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (7)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -222,6 +304,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_UID, 8)
Name (_STA, 0xF)
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x080006000500, 0x080006000504, 20, 130, 130, 65,
+ 65, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (8)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -237,6 +329,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_UID, 9)
Name (_STA, 0xF)
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x080006000518, 0x08000600051C, 20, 130, 130, 65,
+ 65, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (9)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -252,6 +354,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_UID, 10)
Name (_STA, 0xF)
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x080006000530, 0x080006000534, 20, 130, 130, 65,
+ 65, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (10)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -267,6 +379,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_UID, 11)
Name (_STA, 0xF)
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x080006000548, 0x08000600054C, 20, 130, 130, 65,
+ 65, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (11)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -282,6 +404,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_UID, 12)
Name (_STA, 0xF)
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x0C0006000500, 0x0C0006000504, 20, 130, 130, 65,
+ 65, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (12)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -297,6 +429,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_UID, 13)
Name (_STA, 0xF)
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x0C0006000518, 0x0C000600051C, 20, 130, 130, 65,
+ 65, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (13)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -312,6 +454,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_UID, 14)
Name (_STA, 0xF)
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x0C0006000530, 0x0C0006000534, 20, 130, 130, 65,
+ 65, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (14)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -327,6 +479,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_UID, 15)
Name (_STA, 0xF)
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x0C0006000548, 0x0C000600054C, 20, 130, 130, 65,
+ 65, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (15)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [edk2-platforms][PATCH V2 10/11] Platform/Sgi: Low Power Idle States for RD-N2
2021-05-11 7:47 [edk2-platforms][PATCH V2 00/11] Enable idle state and CPPC support for RD platform Pranav Madhu
` (8 preceding siblings ...)
2021-05-11 7:47 ` [edk2-platforms][PATCH V2 09/11] Platform/Sgi: ACPI CPPC support " Pranav Madhu
@ 2021-05-11 7:47 ` Pranav Madhu
2021-05-11 7:47 ` [edk2-platforms][PATCH V2 11/11] Platform/Sgi: ACPI CPPC support " Pranav Madhu
` (2 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Pranav Madhu @ 2021-05-11 7:47 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar
RD-N2 platform supports two LPI states, LPI1 (Standby WFI) and LPI3
(Power-down). The cluster supports LPI2 (Power-down) state. The LPI
implementation also supports combined power state for core and cluster.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl | 214 ++++++++++++++++++++
1 file changed, 214 insertions(+)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl
index c5d6f44b3e44..125b20b64cee 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl
@@ -13,179 +13,393 @@
DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
EFI_ACPI_ARM_OEM_REVISION) {
Scope (_SB) {
+ /* _OSC: Operating System Capabilities */
+ Method (_OSC, 4, Serialized) {
+ CreateDWordField (Arg3, 0x00, STS0)
+ CreateDWordField (Arg3, 0x04, CAP0)
+
+ /* Platform-wide Capabilities */
+ If (LEqual (Arg0, ToUUID("0811b06e-4a27-44f9-8d60-3cbbc22e7b48"))) {
+ /* OSC rev 1 supported, for other version, return failure */
+ If (LEqual (Arg1, One)) {
+ And (STS0, Not (OSC_STS_MASK), STS0)
+
+ If (And (CAP0, OSC_CAP_OS_INITIATED_LPI)) {
+ /* OS initiated LPI not supported */
+ And (CAP0, Not (OSC_CAP_OS_INITIATED_LPI), CAP0)
+ Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+ }
+ } Else {
+ And (STS0, Not (OSC_STS_MASK), STS0)
+ Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0)
+ }
+ } Else {
+ And (STS0, Not (OSC_STS_MASK), STS0)
+ Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_UUID), STS0)
+ }
+
+ Return (Arg3)
+ }
+
+ Name (CLPI, Package () { /* LPI for Cluster, support 1 LPI state */
+ 0, // Version
+ 0, // Level Index
+ 1, // Count
+ Package () { // Power Gating state for Cluster
+ 2500, // Min residency (uS)
+ 1150, // Wake latency (uS)
+ 1, // Flags
+ 1, // Arch Context Flags
+ 100, // Residency Counter Frequency
+ 0, // No Parent State
+ 0x00000020, // Integer Entry method
+ ResourceTemplate () { // Null Residency Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ ResourceTemplate () { // Null Usage Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ "LPI2-Cluster"
+ },
+ })
+
+ Name (PLPI, Package () { /* LPI for Processor, support 2 LPI states */
+ 0, // Version
+ 1, // Level Index
+ 2, // Count
+ Package () { // WFI for CPU
+ 1, // Min residency (uS)
+ 1, // Wake latency (uS)
+ 1, // Flags
+ 0, // Arch Context lost Flags (no loss)
+ 100, // Residency Counter Frequency
+ 0, // No parent state
+ ResourceTemplate () { // Register Entry method
+ Register (FFixedHW,
+ 32, // Bit Width
+ 0, // Bit Offset
+ 0xFFFFFFFF, // Address
+ 3, // Access Size
+ )
+ },
+ ResourceTemplate () { // Null Residency Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ ResourceTemplate () { // Null Usage Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ "LPI1-Core"
+ },
+ Package () { // Power Gating state for CPU
+ 150, // Min residency (uS)
+ 350, // Wake latency (uS)
+ 1, // Flags
+ 1, // Arch Context lost Flags (Core context lost)
+ 100, // Residency Counter Frequency
+ 1, // Parent node can be in any shallower state
+ ResourceTemplate () { // Register Entry method
+ Register (FFixedHW,
+ 32, // Bit Width
+ 0, // Bit Offset
+ 0x40000002, // Address (PwrLvl:core, StateTyp:PwrDn)
+ 3, // Access Size
+ )
+ },
+ ResourceTemplate () { // Null Residency Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ ResourceTemplate () { // Null Usage Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+ },
+ "LPI3-Core"
+ },
+ })
+
Device (CL00) { // Cluster 0
Name (_HID, "ACPI0010")
Name (_UID, 0)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.CLPI)
+ }
Device (CP00) { // Neoverse N2 core 0
Name (_HID, "ACPI0007")
Name (_UID, 0)
Name (_STA, 0xF)
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
Device (CL01) { // Cluster 1
Name (_HID, "ACPI0010")
Name (_UID, 1)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.CLPI)
+ }
Device (CP01) { // Neoverse N2 core 1
Name (_HID, "ACPI0007")
Name (_UID, 1)
Name (_STA, 0xF)
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
Device (CL02) { // Cluster 2
Name (_HID, "ACPI0010")
Name (_UID, 2)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.CLPI)
+ }
Device (CP02) { // Neoverse N2 core 2
Name (_HID, "ACPI0007")
Name (_UID, 2)
Name (_STA, 0xF)
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
Device (CL03) { // Cluster 3
Name (_HID, "ACPI0010")
Name (_UID, 3)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.CLPI)
+ }
Device (CP03) { // Neoverse N2 core 3
Name (_HID, "ACPI0007")
Name (_UID, 3)
Name (_STA, 0xF)
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
Device (CL04) { // Cluster 4
Name (_HID, "ACPI0010")
Name (_UID, 4)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.CLPI)
+ }
Device (CP04) { // Neoverse N2 core 4
Name (_HID, "ACPI0007")
Name (_UID, 4)
Name (_STA, 0xF)
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
Device (CL05) { // Cluster 5
Name (_HID, "ACPI0010")
Name (_UID, 5)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.CLPI)
+ }
Device (CP05) { // Neoverse N2 core 5
Name (_HID, "ACPI0007")
Name (_UID, 5)
Name (_STA, 0xF)
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
Device (CL06) { // Cluster 6
Name (_HID, "ACPI0010")
Name (_UID, 6)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.CLPI)
+ }
Device (CP06) { // Neoverse N2 core 6
Name (_HID, "ACPI0007")
Name (_UID, 6)
Name (_STA, 0xF)
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
Device (CL07) { // Cluster 7
Name (_HID, "ACPI0010")
Name (_UID, 7)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.CLPI)
+ }
Device (CP07) { // Neoverse N2 core 7
Name (_HID, "ACPI0007")
Name (_UID, 7)
Name (_STA, 0xF)
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
Device (CL08) { // Cluster 8
Name (_HID, "ACPI0010")
Name (_UID, 8)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.CLPI)
+ }
Device (CP08) { // Neoverse N2 core 8
Name (_HID, "ACPI0007")
Name (_UID, 8)
Name (_STA, 0xF)
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
Device (CL09) { // Cluster 9
Name (_HID, "ACPI0010")
Name (_UID, 9)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.CLPI)
+ }
Device (CP09) { // Neoverse N2 core 9
Name (_HID, "ACPI0007")
Name (_UID, 9)
Name (_STA, 0xF)
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
Device (CL10) { // Cluster 10
Name (_HID, "ACPI0010")
Name (_UID, 10)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.CLPI)
+ }
Device (CP10) { // Neoverse N2 core 10
Name (_HID, "ACPI0007")
Name (_UID, 10)
Name (_STA, 0xF)
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
Device (CL11) { // Cluster 11
Name (_HID, "ACPI0010")
Name (_UID, 11)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.CLPI)
+ }
Device (CP11) { // Neoverse N2 core 11
Name (_HID, "ACPI0007")
Name (_UID, 11)
Name (_STA, 0xF)
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
Device (CL12) { // Cluster 12
Name (_HID, "ACPI0010")
Name (_UID, 12)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.CLPI)
+ }
Device (CP12) { // Neoverse N2 core 12
Name (_HID, "ACPI0007")
Name (_UID, 12)
Name (_STA, 0xF)
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
Device (CL13) { // Cluster 13
Name (_HID, "ACPI0010")
Name (_UID, 13)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.CLPI)
+ }
Device (CP13) { // Neoverse N2 core 13
Name (_HID, "ACPI0007")
Name (_UID, 13)
Name (_STA, 0xF)
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
Device (CL14) { // Cluster 14
Name (_HID, "ACPI0010")
Name (_UID, 14)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.CLPI)
+ }
Device (CP14) { // Neoverse N2 core 14
Name (_HID, "ACPI0007")
Name (_UID, 14)
Name (_STA, 0xF)
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
Device (CL15) { // Cluster 15
Name (_HID, "ACPI0010")
Name (_UID, 15)
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.CLPI)
+ }
Device (CP15) { // Neoverse N2 core 15
Name (_HID, "ACPI0007")
Name (_UID, 15)
Name (_STA, 0xF)
+
+ Method (_LPI, 0, NotSerialized) {
+ Return (\_SB.PLPI)
+ }
}
}
} // Scope(_SB)
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [edk2-platforms][PATCH V2 11/11] Platform/Sgi: ACPI CPPC support for RD-N2
2021-05-11 7:47 [edk2-platforms][PATCH V2 00/11] Enable idle state and CPPC support for RD platform Pranav Madhu
` (9 preceding siblings ...)
2021-05-11 7:47 ` [edk2-platforms][PATCH V2 10/11] Platform/Sgi: Low Power Idle States for RD-N2 Pranav Madhu
@ 2021-05-11 7:47 ` Pranav Madhu
2021-05-11 18:05 ` [edk2-platforms][PATCH V2 00/11] Enable idle state and CPPC support for RD platform Sami Mujawar
2021-05-11 18:05 ` Sami Mujawar
12 siblings, 0 replies; 14+ messages in thread
From: Pranav Madhu @ 2021-05-11 7:47 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Sami Mujawar
Enable ACPI CPPC mechanism for RD-N2 as defined by the ACPI
specification. The implementation uses AMU registers accessible as
Fixed-feature Hardware (FFixedHW) for monitoring the performance.
Non-secure SCMI fastchannels are used to communicate with SCP to set
the desired performance. RD-N2 platform does not support CPPC revision
1 and below. So update the _OSC method to let OSPM know about this fact.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl | 150 ++++++++++++++++++++
1 file changed, 150 insertions(+)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl
index 125b20b64cee..a318ef48ded9 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl
@@ -29,6 +29,12 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
And (CAP0, Not (OSC_CAP_OS_INITIATED_LPI), CAP0)
Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
}
+
+ If (And (CAP0, OSC_CAP_CPPC_SUPPORT)) {
+ /* CPPC revision 1 and below not supported */
+ And (CAP0, Not (OSC_CAP_CPPC_SUPPORT), CAP0)
+ Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+ }
} Else {
And (STS0, Not (OSC_STS_MASK), STS0)
Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0)
@@ -127,6 +133,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_UID, 0)
Name (_STA, 0xF)
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000500, 0x06000504, 20, 160, 160, 115, 115, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (0)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -145,6 +160,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_UID, 1)
Name (_STA, 0xF)
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000518, 0x0600051C, 20, 160, 160, 115, 115, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (1)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -163,6 +187,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_UID, 2)
Name (_STA, 0xF)
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000530, 0x06000534, 20, 160, 160, 115, 115, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (2)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -181,6 +214,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_UID, 3)
Name (_STA, 0xF)
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000548, 0x0600054C, 20, 160, 160, 115, 115, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (3)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -199,6 +241,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_UID, 4)
Name (_STA, 0xF)
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000560, 0x06000564, 20, 160, 160, 115, 115, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (4)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -217,6 +268,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_UID, 5)
Name (_STA, 0xF)
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000578, 0x0600057C, 20, 160, 160, 115, 115, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (5)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -235,6 +295,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_UID, 6)
Name (_STA, 0xF)
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000590, 0x06000594, 20, 160, 160, 115, 115, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (6)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -253,6 +322,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_UID, 7)
Name (_STA, 0xF)
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x060005A8, 0x060005AC, 20, 160, 160, 115, 115, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (7)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -271,6 +349,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_UID, 8)
Name (_STA, 0xF)
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x060005C0, 0x060005C4, 20, 160, 160, 115, 115, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (8)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -289,6 +376,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_UID, 9)
Name (_STA, 0xF)
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x060005D8, 0x060005DC, 20, 160, 160, 115, 115, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (9)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -307,6 +403,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_UID, 10)
Name (_STA, 0xF)
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x060005F0, 0x060005F4, 20, 160, 160, 115, 115, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (10)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -325,6 +430,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_UID, 11)
Name (_STA, 0xF)
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000608, 0x0600060C, 20, 160, 160, 115, 115, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (11)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -343,6 +457,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_UID, 12)
Name (_STA, 0xF)
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000620, 0x06000624, 20, 160, 160, 115, 115, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (12)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -361,6 +484,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_UID, 13)
Name (_STA, 0xF)
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000638, 0x0600063C, 20, 160, 160, 115, 115, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (13)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -379,6 +511,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_UID, 14)
Name (_STA, 0xF)
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000650, 0x06000654, 20, 160, 160, 115, 115, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (14)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -397,6 +538,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
Name (_UID, 15)
Name (_STA, 0xF)
+ Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000668, 0x0600066C, 20, 160, 160, 115, 115, 5)
+ )
+
+ Name (_PSD, Package () {
+ Package ()
+ PSD_INIT (15)
+ })
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [edk2-platforms][PATCH V2 00/11] Enable idle state and CPPC support for RD platform
2021-05-11 7:47 [edk2-platforms][PATCH V2 00/11] Enable idle state and CPPC support for RD platform Pranav Madhu
` (10 preceding siblings ...)
2021-05-11 7:47 ` [edk2-platforms][PATCH V2 11/11] Platform/Sgi: ACPI CPPC support " Pranav Madhu
@ 2021-05-11 18:05 ` Sami Mujawar
2021-05-11 18:05 ` Sami Mujawar
12 siblings, 0 replies; 14+ messages in thread
From: Sami Mujawar @ 2021-05-11 18:05 UTC (permalink / raw)
To: Pranav Madhu, devel@edk2.groups.io; +Cc: Ard Biesheuvel, nd
For this series.
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Regards,
Sami Mujawar
On 11/05/2021, 08:47, "Pranav Madhu" <pranav.madhu@arm.com> wrote:
Changes since V1:
- Remove patches that add CPU container object into DSDT
- Addressed comments from Sami
Low Power Idle (LPI) and Collaborative Processor Performance Control
(CPPC) are two power management mechanisms described in ACPI 6.4
specification. OSPM uses the _LPI object to select a local power state
for each level of processor hierarchy in the system. Collaborative
processor performance control (CPPC) defines an abstracted and flexible
mechanism for OSPM to collaborate with an entity in the platform to
manage the performance of a processor. In this patch series, CPPC
support depends on the availability of Activity Monitor Unit (AMU)
extension for CPU performance monitoring as defined in the Arm v8.4
architecture reference manuals. So CPPC is supported for RD-V1 and
RD-N2 platforms.
This patch series adds LPI support for all the Neoverse reference
design platforms. CPPC support is added for RD-V1, RD-V1-MC and
RD-N2 platforms.
This patch series should be applied on top of the patch series
https://edk2.groups.io/g/devel/message/74924
Link to github branch with the patches in this series -
https://github.com/Pranav-Madhu/edk2-platforms/tree/topics/rd_power_management
Pranav Madhu (11):
Platform/Sgi: Macro definitions for ACPI _OSC
Platform/Sgi: Low Power Idle states for SGI-575
Platform/Sgi: Low Power Idle states for RD-N1-Edge
Platform/Sgi: Low Power Idle States for RD-N1-Edge dual-chip
Platform/Sgi: Low Power Idle states for RD-V1 platform
Platform/Sgi: Macro definitions for ACPI CPPC
Platform/Sgi: ACPI CPPC support for RD-V1
Platform/Sgi: Low Power Idle States for RD-V1 quad-chip platform
Platform/Sgi: ACPI CPPC support for RD-V1 quad-chip platform
Platform/Sgi: Low Power Idle States for RD-N2
Platform/Sgi: ACPI CPPC support for RD-N2
Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 90 +++++
.../ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl | 132 +++++++
.../ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl | 162 ++++++++
Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl | 364 ++++++++++++++++++
Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl | 294 ++++++++++++++
.../ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl | 306 +++++++++++++++
.../ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl | 132 +++++++
7 files changed, 1480 insertions(+)
--
2.17.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [edk2-platforms][PATCH V2 00/11] Enable idle state and CPPC support for RD platform
2021-05-11 7:47 [edk2-platforms][PATCH V2 00/11] Enable idle state and CPPC support for RD platform Pranav Madhu
` (11 preceding siblings ...)
2021-05-11 18:05 ` [edk2-platforms][PATCH V2 00/11] Enable idle state and CPPC support for RD platform Sami Mujawar
@ 2021-05-11 18:05 ` Sami Mujawar
12 siblings, 0 replies; 14+ messages in thread
From: Sami Mujawar @ 2021-05-11 18:05 UTC (permalink / raw)
To: Pranav Madhu, devel@edk2.groups.io; +Cc: Ard Biesheuvel, nd
Pushed as 8549b1739183..e1efa61c33f7
Thanks,
Regards,
Sami Mujawar
On 11/05/2021, 08:47, "Pranav Madhu" <pranav.madhu@arm.com> wrote:
Changes since V1:
- Remove patches that add CPU container object into DSDT
- Addressed comments from Sami
Low Power Idle (LPI) and Collaborative Processor Performance Control
(CPPC) are two power management mechanisms described in ACPI 6.4
specification. OSPM uses the _LPI object to select a local power state
for each level of processor hierarchy in the system. Collaborative
processor performance control (CPPC) defines an abstracted and flexible
mechanism for OSPM to collaborate with an entity in the platform to
manage the performance of a processor. In this patch series, CPPC
support depends on the availability of Activity Monitor Unit (AMU)
extension for CPU performance monitoring as defined in the Arm v8.4
architecture reference manuals. So CPPC is supported for RD-V1 and
RD-N2 platforms.
This patch series adds LPI support for all the Neoverse reference
design platforms. CPPC support is added for RD-V1, RD-V1-MC and
RD-N2 platforms.
This patch series should be applied on top of the patch series
https://edk2.groups.io/g/devel/message/74924
Link to github branch with the patches in this series -
https://github.com/Pranav-Madhu/edk2-platforms/tree/topics/rd_power_management
Pranav Madhu (11):
Platform/Sgi: Macro definitions for ACPI _OSC
Platform/Sgi: Low Power Idle states for SGI-575
Platform/Sgi: Low Power Idle states for RD-N1-Edge
Platform/Sgi: Low Power Idle States for RD-N1-Edge dual-chip
Platform/Sgi: Low Power Idle states for RD-V1 platform
Platform/Sgi: Macro definitions for ACPI CPPC
Platform/Sgi: ACPI CPPC support for RD-V1
Platform/Sgi: Low Power Idle States for RD-V1 quad-chip platform
Platform/Sgi: ACPI CPPC support for RD-V1 quad-chip platform
Platform/Sgi: Low Power Idle States for RD-N2
Platform/Sgi: ACPI CPPC support for RD-N2
Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 90 +++++
.../ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl | 132 +++++++
.../ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl | 162 ++++++++
Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl | 364 ++++++++++++++++++
Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl | 294 ++++++++++++++
.../ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl | 306 +++++++++++++++
.../ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl | 132 +++++++
7 files changed, 1480 insertions(+)
--
2.17.1
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2021-05-11 18:05 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2021-05-11 7:47 [edk2-platforms][PATCH V2 00/11] Enable idle state and CPPC support for RD platform Pranav Madhu
2021-05-11 7:47 ` [edk2-platforms][PATCH V2 01/11] Platform/Sgi: Macro definitions for ACPI _OSC Pranav Madhu
2021-05-11 7:47 ` [edk2-platforms][PATCH V2 02/11] Platform/Sgi: Low Power Idle states for SGI-575 Pranav Madhu
2021-05-11 7:47 ` [edk2-platforms][PATCH V2 03/11] Platform/Sgi: Low Power Idle states for RD-N1-Edge Pranav Madhu
2021-05-11 7:47 ` [edk2-platforms][PATCH V2 04/11] Platform/Sgi: Low Power Idle States for RD-N1-Edge dual-chip Pranav Madhu
2021-05-11 7:47 ` [edk2-platforms][PATCH V2 05/11] Platform/Sgi: Low Power Idle states for RD-V1 platform Pranav Madhu
2021-05-11 7:47 ` [edk2-platforms][PATCH V2 06/11] Platform/Sgi: Macro definitions for ACPI CPPC Pranav Madhu
2021-05-11 7:47 ` [edk2-platforms][PATCH V2 07/11] Platform/Sgi: ACPI CPPC support for RD-V1 Pranav Madhu
2021-05-11 7:47 ` [edk2-platforms][PATCH V2 08/11] Platform/Sgi: Low Power Idle States for RD-V1 quad-chip platform Pranav Madhu
2021-05-11 7:47 ` [edk2-platforms][PATCH V2 09/11] Platform/Sgi: ACPI CPPC support " Pranav Madhu
2021-05-11 7:47 ` [edk2-platforms][PATCH V2 10/11] Platform/Sgi: Low Power Idle States for RD-N2 Pranav Madhu
2021-05-11 7:47 ` [edk2-platforms][PATCH V2 11/11] Platform/Sgi: ACPI CPPC support " Pranav Madhu
2021-05-11 18:05 ` [edk2-platforms][PATCH V2 00/11] Enable idle state and CPPC support for RD platform Sami Mujawar
2021-05-11 18:05 ` Sami Mujawar
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