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From: "Pranav Madhu" <pranav.madhu@arm.com>
To: devel@edk2.groups.io
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>,
	Sami Mujawar <sami.mujawar@arm.com>
Subject: [edk2-platforms][PATCH V2 06/11] Platform/Sgi: Macro definitions for ACPI CPPC
Date: Tue, 11 May 2021 13:17:09 +0530	[thread overview]
Message-ID: <20210511074714.1894-7-pranav.madhu@arm.com> (raw)
In-Reply-To: <20210511074714.1894-1-pranav.madhu@arm.com>

Add helper macros required for use with ACPI collaborative processor
performance control (CPPC). This patch adds macros for initializing ACPI
_CPC and _PSD control method. The CPC initializer macro initializes _CPC
control method with revision 3 as specified in Arm FFH specification
1.1. The CPC initilizer exposes the reference performance counter and
delivered perfrmance counter (AMU registers) as FFixedHW registers. The
initilizer also expose the fastchannel memories for performance level
set performance limit set protocols as desired performance register and
performance limited register respectively.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
 Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 74 ++++++++++++++++++++
 1 file changed, 74 insertions(+)

diff --git a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
index c23938fe3d4f..7b8c16b172c0 100644
--- a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
+++ b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
@@ -432,4 +432,78 @@ typedef struct {
     LineSize                                          /* Line size in bytes */ \
   }
 
+/** Helper macro for CPPC _CPC object initialization. Use of this macro is
+    restricted to ASL file and not to TDL file.
+
+    @param [in] DesiredPerfReg      Fastchannel address for desired performance
+                                    register.
+    @param [in] PerfLimitedReg      Fastchannel address for performance limited
+                                    register.
+    @param [in] GranularityMHz      Granularity of the performance scale.
+    @param [in] HighestPerf         Highest performance in linear scale.
+    @param [in] NominalPerf         Nominal performance in linear scale.
+    @param [in] LowestNonlinearPerf Lowest non-linear performnce in linear
+                                    scale.
+    @param [in] LowestPerf          Lowest performance in linear scale.
+    @param [in] RefPerf             Reference performance in linear scale.
+**/
+#define CPPC_PACKAGE_INIT(DesiredPerfReg, PerfLimitedReg, GranularityMHz,      \
+  HighestPerf, NominalPerf, LowestNonlinearPerf, LowestPerf, RefPerf)          \
+  {                                                                            \
+    23,                                 /* NumEntries */                       \
+    3,                                  /* Revision */                         \
+    HighestPerf,                        /* Highest Performance */              \
+    NominalPerf,                        /* Nominal Performance */              \
+    LowestNonlinearPerf,                /* Lowest Nonlinear Performance */     \
+    LowestPerf,                         /* Lowest Performance */               \
+    /* Guaranteed Performance Register */                                      \
+    ResourceTemplate () { Register (SystemMemory, 0, 0, 0, 0) },               \
+    /* Desired Performance Register */                                         \
+    ResourceTemplate () { Register (SystemMemory, 32, 0, DesiredPerfReg, 3) }, \
+    /* Minimum Performance Register */                                         \
+    ResourceTemplate () { Register (SystemMemory, 0, 0, 0, 0) },               \
+    /* Maximum Performance Register */                                         \
+    ResourceTemplate () { Register (SystemMemory, 0, 0, 0, 0) },               \
+    /* Performance Reduction Tolerance Register */                             \
+    ResourceTemplate () { Register (SystemMemory, 0, 0, 0, 0) },               \
+    /* Time Window Register */                                                 \
+    ResourceTemplate () { Register (SystemMemory, 0, 0, 0, 0) },               \
+    /* Counter Wraparound Time */                                              \
+    ResourceTemplate () { Register (SystemMemory, 0, 0, 0, 0) },               \
+    /* Reference Performance Counter Register */                               \
+    ResourceTemplate () { Register (FFixedHW, 64, 0, 1, 4) },                  \
+    /* Delivered Performance Counter Register */                               \
+    ResourceTemplate () { Register (FFixedHW, 64, 0, 0, 4) },                  \
+    /* Performance Limited Register */                                         \
+    ResourceTemplate () { Register (SystemMemory, 32, 0, PerfLimitedReg, 3) }, \
+    /* CPPC Enable Register */                                                 \
+    ResourceTemplate () { Register (SystemMemory, 0, 0, 0, 0) },               \
+    /* Autonomous Selection Enable Register */                                 \
+    ResourceTemplate () { Register (SystemMemory, 0, 0, 0, 0) },               \
+    /* Autonomous Activity Window Register */                                  \
+    ResourceTemplate () { Register (SystemMemory, 0, 0, 0, 0) },               \
+    /* Energy Performance Preference Register */                               \
+    ResourceTemplate () { Register (SystemMemory, 0, 0, 0, 0) },               \
+    RefPerf,                            /* Reference Performance */            \
+    (LowestPerf * GranularityMHz),      /* Lowest Frequency */                 \
+    (NominalPerf * GranularityMHz),     /* Nominal Frequency */                \
+  }
+
+// Power state dependancy (_PSD) for CPPC
+
+/** Helper macro to initialize Power state dependancy (_PSD) object required
+    for CPPC. Use of this macro is restricted to ASL file and not to TDL file.
+
+    @param [in] Domain              The dependency domain number to which this
+                                    P-state entry belongs.
+**/
+#define PSD_INIT(Domain)                                                       \
+  {                                                                            \
+    5,              /* Entries */                                              \
+    0,              /* Revision */                                             \
+    Domain,         /* Domain */                                               \
+    0xFD,           /* Coord Type- SW_ANY */                                   \
+    1               /* Processors */                                           \
+  }
+
 #endif /* __SGI_ACPI_HEADER__ */
-- 
2.17.1


  parent reply	other threads:[~2021-05-11  7:47 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-11  7:47 [edk2-platforms][PATCH V2 00/11] Enable idle state and CPPC support for RD platform Pranav Madhu
2021-05-11  7:47 ` [edk2-platforms][PATCH V2 01/11] Platform/Sgi: Macro definitions for ACPI _OSC Pranav Madhu
2021-05-11  7:47 ` [edk2-platforms][PATCH V2 02/11] Platform/Sgi: Low Power Idle states for SGI-575 Pranav Madhu
2021-05-11  7:47 ` [edk2-platforms][PATCH V2 03/11] Platform/Sgi: Low Power Idle states for RD-N1-Edge Pranav Madhu
2021-05-11  7:47 ` [edk2-platforms][PATCH V2 04/11] Platform/Sgi: Low Power Idle States for RD-N1-Edge dual-chip Pranav Madhu
2021-05-11  7:47 ` [edk2-platforms][PATCH V2 05/11] Platform/Sgi: Low Power Idle states for RD-V1 platform Pranav Madhu
2021-05-11  7:47 ` Pranav Madhu [this message]
2021-05-11  7:47 ` [edk2-platforms][PATCH V2 07/11] Platform/Sgi: ACPI CPPC support for RD-V1 Pranav Madhu
2021-05-11  7:47 ` [edk2-platforms][PATCH V2 08/11] Platform/Sgi: Low Power Idle States for RD-V1 quad-chip platform Pranav Madhu
2021-05-11  7:47 ` [edk2-platforms][PATCH V2 09/11] Platform/Sgi: ACPI CPPC support " Pranav Madhu
2021-05-11  7:47 ` [edk2-platforms][PATCH V2 10/11] Platform/Sgi: Low Power Idle States for RD-N2 Pranav Madhu
2021-05-11  7:47 ` [edk2-platforms][PATCH V2 11/11] Platform/Sgi: ACPI CPPC support " Pranav Madhu
2021-05-11 18:05 ` [edk2-platforms][PATCH V2 00/11] Enable idle state and CPPC support for RD platform Sami Mujawar
2021-05-11 18:05 ` Sami Mujawar

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