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ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2021 02:48:45 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Chasel Chiu , Mike Kinney , Isaac Oram , Mohamed Abbas , Michael Kubacki , Zachary Bobroff , Harikrishna Doppalapudi Subject: [edk2-platforms] [PATCH V1 07/18] PurleyRefreshSiliconPkg: Add Uncore files Date: Tue, 11 May 2021 02:48:15 -0700 Message-Id: <20210511094826.12495-8-nathaniel.l.desimone@intel.com> X-Mailer: git-send-email 2.27.0.windows.1 In-Reply-To: <20210511094826.12495-1-nathaniel.l.desimone@intel.com> References: <20210511094826.12495-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Chasel Chiu Cc: Mike Kinney Cc: Isaac Oram Cc: Mohamed Abbas Cc: Michael Kubacki Cc: Zachary Bobroff Cc: Harikrishna Doppalapudi Signed-off-by: Nate DeSimone --- .../Iio/Include/Protocol/IioSystem.h | 58 ++ .../Include/Guid/MemoryConfigData.h | 19 + .../Include/Guid/MemoryMapData.h | 74 ++ .../Include/Guid/PartialMirrorGuid.h | 59 ++ .../Include/Guid/SmramMemoryReserve.h | 43 + .../Include/Guid/SocketCommonRcVariable.h | 41 + .../Include/Guid/SocketIioVariable.h | 264 ++++++ .../Include/Guid/SocketMemoryVariable.h | 321 +++++++ .../Include/Guid/SocketMpLinkVariable.h | 173 ++++ .../Include/Guid/SocketPciResourceData.h | 42 + .../Guid/SocketPowermanagementVariable.h | 227 +++++ .../Guid/SocketProcessorCoreVariable.h | 115 +++ .../Include/Guid/SocketVariable.h | 35 + .../Include/Library/CpuPpmLib.h | 707 +++++++++++++++ .../Include/Library/CsrToPcieAddress.h | 42 + .../Include/Library/MmPciBaseLib.h | 48 ++ .../Include/Library/PcieAddress.h | 80 ++ .../Include/Library/PciePlatformHookLib.h | 27 + .../Include/Library/UsraAccessApi.h | 85 ++ .../Include/MaxSocket.h | 19 + .../Include/Ppi/SiliconRegAccess.h | 162 ++++ .../Include/Protocol/IioUds.h | 44 + .../Include/Protocol/PciCallback.h | 84 ++ .../Include/Protocol/SiliconRegAccess.h | 227 +++++ .../Include/SocketConfiguration.h | 514 +++++++++++ .../Include/UncoreCommonIncludes.h | 354 ++++++++ .../Include/UsraAccessType.h | 195 +++++ .../Chip/Skx/Include/Iio/IioConfig.h | 300 +++++++ .../Chip/Skx/Include/Iio/IioPlatformData.h | 298 +++++++ .../Chip/Skx/Include/Iio/IioRegs.h | 314 +++++++ .../Skx/Include/Iio/IioSetupDefinitions.h | 111 +++ .../Chip/Skx/Include/KtiDisc.h | 26 + .../Chip/Skx/Include/KtiHost.h | 136 +++ .../Chip/Skx/Include/KtiSi.h | 39 + .../Chip/Skx/Include/Protocol/CpuCsrAccess.h | 143 +++ .../Chip/Skx/Include/Setup/IioUniversalData.h | 187 ++++ .../BaseMemoryCoreLib/Core/Include/CpuHost.h | 255 ++++++ .../Core/Include/CsrToPcieAddress.h | 42 + .../Core/Include/DataTypes.h | 111 +++ .../BaseMemoryCoreLib/Core/Include/MemHost.h | 328 +++++++ .../Core/Include/MemHostChipCommon.h | 122 +++ .../BaseMemoryCoreLib/Core/Include/MemRegs.h | 13 + .../Core/Include/MrcCommonTypes.h | 20 + .../Core/Include/PcieAddress.h | 65 ++ .../BaseMemoryCoreLib/Core/Include/Printf.h | 74 ++ .../BaseMemoryCoreLib/Core/Include/SysHost.h | 136 +++ .../Core/Include/SysHostChipCommon.h | 86 ++ .../BaseMemoryCoreLib/Core/Include/SysRegs.h | 68 ++ .../Core/Include/UsbDebugPort.h | 318 +++++++ .../Platform/Purley/Include/MemDefaults.h | 17 + .../Platform/Purley/Include/MemPlatform.h | 81 ++ .../Platform/Purley/Include/PlatformHost.h | 176 ++++ .../Library/CsrToPcieLib/CpuCsrAccessDefine.h | 56 ++ .../Library/CsrToPcieLib/CsrToPcieDxeLib.inf | 85 ++ .../Library/CsrToPcieLib/CsrToPcieLib.c | 179 ++++ .../Library/CsrToPcieLib/CsrToPciePeiLib.inf | 81 ++ .../CsrToPcieLibNull/BaseCsrToPcieLibNull.inf | 67 ++ .../Library/CsrToPcieLibNull/CsrToPcieLib.c | 41 + .../Library/DxeMmPciBaseLib/DxeMmPciBaseLib.c | 89 ++ .../DxeMmPciBaseLib/DxeMmPciBaseLib.inf | 60 ++ .../Library/DxeMmPciBaseLib/SmmMmPciBaseLib.c | 86 ++ .../DxeMmPciBaseLib/SmmMmPciBaseLib.inf | 60 ++ .../Library/MmPciBaseLib/MmPciBaseLib.c | 69 ++ .../Library/MmPciBaseLib/MmPciBaseLib.inf | 55 ++ .../Library/PcieAddressLib/PcieAddressLib.c | 305 +++++++ .../Library/PcieAddressLib/PcieAddressLib.inf | 70 ++ .../Chip/Common/CpuPciAccessCommon.c | 812 ++++++++++++++++++ .../Chip/Include/CpuCsrAccessDefine.h | 52 ++ .../ProcMemInit/Chip/Include/CpuPciAccess.h | 117 +++ .../Chip/Include/CpuPciAccessCommon.h | 83 ++ .../ProcMemInit/Chip/Include/Rc_Revision.h | 13 + .../Library/UsraAccessLib/CsrAccess.c | 118 +++ .../Library/UsraAccessLib/PcieAccess.c | 354 ++++++++ .../Library/UsraAccessLib/UsraAccessLib.c | 235 +++++ .../Library/UsraAccessLib/UsraAccessLib.h | 257 ++++++ .../Library/UsraAccessLib/UsraAccessLib.inf | 62 ++ .../IA32FamilyCpuPkg/IA32FamilyCpuPkg.dec | 609 +++++++++++++ .../Include/Library/CpuConfigLib.h | 667 ++++++++++++++ .../Include/Protocol/IntelCpuPcdsSetDone.h | 18 + 79 files changed, 12225 insertions(+) create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Iio/Include/Protocol/IioSystem.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/MemoryConfigData.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/MemoryMapData.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/PartialMirrorGuid.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SmramMemoryReserve.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketCommonRcVariable.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketIioVariable.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketMemoryVariable.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketMpLinkVariable.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketPciResourceData.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketPowermanagementVariable.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketProcessorCoreVariable.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketVariable.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/CpuPpmLib.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/CsrToPcieAddress.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/MmPciBaseLib.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/PcieAddress.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/PciePlatformHookLib.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/UsraAccessApi.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/MaxSocket.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Ppi/SiliconRegAccess.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Protocol/IioUds.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Protocol/PciCallback.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/Protocol/SiliconRegAccess.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/SocketConfiguration.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/UncoreCommonIncludes.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Include/UsraAccessType.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioConfig.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioPlatformData.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioRegs.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioSetupDefinitions.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/KtiDisc.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/KtiHost.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/KtiSi.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Protocol/CpuCsrAccess.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Setup/IioUniversalData.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/CpuHost.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/CsrToPcieAddress.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/DataTypes.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MemHost.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MemHostChipCommon.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MemRegs.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MrcCommonTypes.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/PcieAddress.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/Printf.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/SysHost.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/SysHostChipCommon.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/SysRegs.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/UsbDebugPort.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Platform/Purley/Include/MemDefaults.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Platform/Purley/Include/MemPlatform.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Platform/Purley/Include/PlatformHost.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcieLib/CpuCsrAccessDefine.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcieLib/CsrToPcieDxeLib.inf create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcieLib/CsrToPcieLib.c create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcieLib/CsrToPciePeiLib.inf create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcieLibNull/BaseCsrToPcieLibNull.inf create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcieLibNull/CsrToPcieLib.c create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/DxeMmPciBaseLib/DxeMmPciBaseLib.c create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/DxeMmPciBaseLib/DxeMmPciBaseLib.inf create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/DxeMmPciBaseLib/SmmMmPciBaseLib.c create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/DxeMmPciBaseLib/SmmMmPciBaseLib.inf create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/MmPciBaseLib/MmPciBaseLib.c create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/MmPciBaseLib/MmPciBaseLib.inf create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/PcieAddressLib/PcieAddressLib.c create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/PcieAddressLib/PcieAddressLib.inf create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/ProcMemInit/Chip/Common/CpuPciAccessCommon.c create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/ProcMemInit/Chip/Include/CpuCsrAccessDefine.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/ProcMemInit/Chip/Include/CpuPciAccess.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/ProcMemInit/Chip/Include/CpuPciAccessCommon.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/ProcMemInit/Chip/Include/Rc_Revision.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/UsraAccessLib/CsrAccess.c create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/UsraAccessLib/PcieAccess.c create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/UsraAccessLib/UsraAccessLib.c create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/UsraAccessLib/UsraAccessLib.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Library/UsraAccessLib/UsraAccessLib.inf create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Override/IA32FamilyCpuPkg/IA32FamilyCpuPkg.dec create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Override/IA32FamilyCpuPkg/Include/Library/CpuConfigLib.h create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Override/IA32FamilyCpuPkg/Include/Protocol/IntelCpuPcdsSetDone.h diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Iio/Include/Protocol/IioSystem.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Iio/Include/Protocol/IioSystem.h new file mode 100644 index 0000000000..0a8d3064c3 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Iio/Include/Protocol/IioSystem.h @@ -0,0 +1,58 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _IIO_SYSTEM_PROTOCOL_H_ +#define _IIO_SYSTEM_PROTOCOL_H_ + +#include +#include + +// +// IIO System driver Protocol GUID +// +// {DDC3080A-2740-4ec2-9AA5-A0ADEFD6FF9C} +#define EFI_IIO_SYSTEM_GUID \ + { \ + 0xDDC3080A, 0x2740, 0x4ec2, 0x9A, 0xA5, 0xA0, 0xAD, 0xEF, 0xD6, 0xFF, 0x9C \ + } + +extern EFI_GUID gEfiIioSystemProtocolGuid; + +typedef struct _PORT_DESCRIPTOR{ + UINT8 Bus; + UINT8 Device; + UINT8 Function; +}PORT_DESCRIPTOR; + +typedef struct _PORT_ATTRIB{ + UINT8 PortWidth; + UINT8 PortSpeed; +}PORT_ATTRIB; + +EFI_STATUS +IioGetCpuUplinkPort ( + UINT8 IioIndex, + PORT_DESCRIPTOR *PortDescriptor, //Bus, Device, function + BOOLEAN *PortStatus, //TRUE if enabled else disabled + PORT_ATTRIB *PortAttrib //width and speed +); + +typedef +EFI_STATUS +(EFIAPI *IIO_GET_CPU_UPLINK_PORT) ( + IN UINT8 IioIndex, + OUT PORT_DESCRIPTOR *PortDescriptor, + OUT BOOLEAN *PortStatus, + OUT PORT_ATTRIB *PortAttrib +); + +typedef struct _EFI_IIO_SYSTEM_PROTOCOL{ + IIO_GLOBALS *IioGlobalData; + IIO_GET_CPU_UPLINK_PORT IioGetCpuUplinkPort; +} EFI_IIO_SYSTEM_PROTOCOL; + +#endif //_IIO_SYSTEM_PROTOCOL_H_ \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/MemoryConfigData.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/MemoryConfigData.h new file mode 100644 index 0000000000..f7c57af8a5 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/MemoryConfigData.h @@ -0,0 +1,19 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _MEMORY_CONFIG_DATA_GUID_H_ +#define _MEMORY_CONFIG_DATA_GUID_H_ + +#define EFI_MEMORY_CONFIG_DATA_GUID \ + { \ + 0x80dbd530, 0xb74c, 0x4f11, {0x8c, 0x03, 0x41, 0x86, 0x65, 0x53, 0x28, 0x31 }\ + } + +extern EFI_GUID gEfiMemoryConfigDataGuid; +extern CHAR16 EfiMemoryConfigVariable[]; + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/MemoryMapData.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/MemoryMapData.h new file mode 100644 index 0000000000..c225624edc --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/MemoryMapData.h @@ -0,0 +1,74 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _MEMORY_MAP_GUID_H_ +#define _MEMORY_MAP_GUID_H_ + +#include "SysHost.h" +#include "UncoreCommonIncludes.h" +#include "PartialMirrorGuid.h" + +// {F8870015-6994-4b98-95A2-BD56DA91C07F} +#define EFI_MEMORY_MAP_GUID \ + { \ + 0xf8870015,0x6994,0x4b98,0x95,0xa2,0xbd,0x56,0xda,0x91,0xc0,0x7f \ + } + +extern EFI_GUID gEfiMemoryMapGuid; +extern CHAR16 EfiMemoryMapVariable[]; + +// +// System Memory Map HOB information +// + +#pragma pack(1) + + +typedef struct SystemMemoryMapElement { + UINT16 Type; // Type of this memory element; Bit0: 1LM Bit1: 2LM Bit2: PMEM Bit3: PMEM-cache Bit4: BLK Window Bit5: CSR/Mailbox/Ctrl region + UINT8 NodeId; // Node ID of the HA Owning the memory + UINT8 SocketId; // Socket Id of socket that has his memory - ONLY IN NUMA + UINT8 SktInterBitmap; // Socket interleave bitmap, if more that on socket then ImcInterBitmap and ChInterBitmap are identical in all sockets + UINT8 ImcInterBitmap; // IMC interleave bitmap for this memory + UINT8 ChInterBitmap[MAX_IMC];//Bit map to denote which channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved + UINT32 BaseAddress; // Base Address of the element in 64MB chunks + UINT32 ElementSize; // Size of this memory element in 64MB chunks +} SYSTEM_MEMORY_MAP_ELEMENT; + +typedef struct SystemMemoryMapHob { + UINT32 lowMemBase; // Mem base in 64MB units for below 4GB mem. + UINT32 lowMemSize; // Mem size in 64MB units for below 4GB mem. + UINT32 highMemBase; // Mem base in 64MB units for above 4GB mem. + UINT32 highMemSize; // Mem size in 64MB units for above 4GB mem. + UINT32 memSize; // Total physical memory size + UINT16 memFreq; // Mem Frequency + UINT8 memMode; // 0 - Independent, 1 - Lockstep + UINT8 volMemMode; // 0 - 1LM, 1 - 2LM + UINT8 DimmType; + UINT16 DramType; + UINT8 DdrVoltage; + UINT8 AepDimmPresent; // If at least one Aep Dimm Present (used by Nfit), then this should get set + UINT8 SADNum; + UINT8 XMPProfilesSup; + UINT8 cpuType; + UINT8 cpuStepping; + UINT8 SystemRasType; + UINT8 RasModesEnabled; // RAS modes that are enabled + UINT8 ExRasModesEnabled; // Extended RAS modes that are enabled + UINT8 RasModesSupported; //RAS modes that are supported by current memory population. + UINT8 sncEnabled; // 0 - SNC disabled for this configuration, 1 - SNC enabled for this configuration + UINT8 NumOfCluster; + UINT8 NumChPerMC; + UINT8 numberEntries; // Number of Memory Map Elements + UINT8 maxIMC; + UINT8 maxCh; + struct SystemMemoryMapElement Element[MAX_SOCKET * SAD_RULES]; +} SYSTEM_MEMORY_MAP_HOB; + +#pragma pack() + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/PartialMirrorGuid.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/PartialMirrorGuid.h new file mode 100644 index 0000000000..16fb0f843e --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/PartialMirrorGuid.h @@ -0,0 +1,59 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PARTIAL_MIRROR_GUID_H_ +#define _PARTIAL_MIRROR_GUID_H_ + +#define ADDRESS_BASED_MIRROR_VARIABLE_GUID { 0x7b9be2e0, 0xe28a, 0x4197, 0xad, 0x3e, 0x32, 0xf0, 0x62, 0xf9, 0x46, 0x2c } + +#define ADDRESS_RANGE_MIRROR_VARIABLE_CURRENT L"MirrorCurrent" +#define ADDRESS_RANGE_MIRROR_VARIABLE_REQUEST L"MirrorRequest" +#define ADDRESS_BASED_MIRROR_VARIABLE_SIZE sizeof(ADDRESS_RANGE_MIRROR_VARIABLE_DATA) +#define ADDRESS_BASED_MIRROR_VARIABLE_ATTRIBUTE (EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS) +#define ADDRESS_RANGE_MIRROR_VARIABLE_VERSION 1 +#define MIRROR_STATUS_SUCCESS 0 +#define MIRROR_STATUS_MIRROR_INCAPABLE 1 +#define MIRROR_STATUS_VERSION_MISMATCH 2 +#define MIRROR_STATUS_INVALID_REQUEST 3 +#define MIRROR_STATUS_UNSUPPORTED_CONFIG 4 +#define MIRROR_STATUS_OEM_SPECIFIC_CONFIGURATION 5 + +extern EFI_GUID gAddressBasedMirrorGuid; + +#pragma pack(1) + +typedef struct { +// +// MirroredAmountAbove4GB is the amount of available memory above 4GB that needs to be mirrored +// measured in basis point (hundredths of percent e.g. 12% = 1275). +// In a multi-socket system, platform is required to distribute the mirrored memory ranges such that the +// amount mirrored is approximately proportional to the amount of memory on each NUMA node. E.g. on +// a two node machine with 64GB on node 0 and 32GB on node 1, a request for 12GB of mirrored memory +// should be allocated with 8GB of mirror on node 0 and 4GB on node 1. +// +// For example, if the total memory in the system is 48GB and 12GB of memory above the 4GB addresses needs to be mirrored then the amount would be: +// Total Memory = 48 GB +// Total Memory above 4GB = 44 GB +// Percentage = 8/44 * 100 = 18.18% = 1818 basis points +// Consider a 2S system with 32 GB of memory attached to socket 0 and 16GB on socket 1, +// then socket 0 should mirror 8 GB of memory and socket 1 mirror 4GB to maintain the requested 18%. +// This ensures that OS has an adequate amount of mirrored memory on each NUMA domain. +// + UINT8 MirrorVersion; + BOOLEAN MirrorMemoryBelow4GB; + UINT16 MirroredAmountAbove4GB; + UINT8 MirrorStatus; +} ADDRESS_RANGE_MIRROR_VARIABLE_DATA; + +typedef struct { + ADDRESS_RANGE_MIRROR_VARIABLE_DATA MirrorCurrentType; + ADDRESS_RANGE_MIRROR_VARIABLE_DATA MirrorRequestType; +} RASMEMORYINFO; +#pragma pack() + + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SmramMemoryReserve.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SmramMemoryReserve.h new file mode 100644 index 0000000000..d7b891f40f --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SmramMemoryReserve.h @@ -0,0 +1,43 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _EFI_SMM_PEI_SMRAM_MEMORY_RESERVE_H_ +#define _EFI_SMM_PEI_SMRAM_MEMORY_RESERVE_H_ + +#define EFI_SMM_PEI_SMRAM_MEMORY_RESERVE \ + { \ + 0x6dadf1d1, 0xd4cc, 0x4910, {0xbb, 0x6e, 0x82, 0xb1, 0xfd, 0x80, 0xff, 0x3d } \ + } + +/** +* GUID specific data structure of HOB for reserving SMRAM regions. +* +* Inconsistent with specification here: +* EFI_HOB_SMRAM_DESCRIPTOR_BLOCK has been changed to EFI_SMRAM_HOB_DESCRIPTOR_BLOCK. +* This inconsistency is kept in code in order for backward compatibility. +**/ +typedef struct { + /// + /// Designates the number of possible regions in the system + /// that can be usable for SMRAM. + /// + /// Inconsistent with specification here: + /// In Framework SMM CIS 0.91 specification, it defines the field type as UINTN. + /// However, HOBs are supposed to be CPU neutral, so UINT32 should be used instead. + /// + UINT32 NumberOfSmmReservedRegions; + /// + /// Used throughout this protocol to describe the candidate + /// regions for SMRAM that are supported by this platform. + /// + EFI_SMRAM_DESCRIPTOR Descriptor[1]; +} EFI_SMRAM_HOB_DESCRIPTOR_BLOCK; + +extern EFI_GUID gEfiSmmPeiSmramMemoryReserveGuid; + +#endif + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketCommonRcVariable.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketCommonRcVariable.h new file mode 100644 index 0000000000..b3ea677612 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketCommonRcVariable.h @@ -0,0 +1,41 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SOCKET_COMMONRC_CONFIG_DATA_H__ +#define __SOCKET_COMMONRC_CONFIG_DATA_H__ + + +#include +#include "SocketConfiguration.h" + +extern EFI_GUID gEfiSocketCommonRcVariableGuid; +#define SOCKET_COMMONRC_CONFIGURATION_NAME L"SocketCommonRcConfig" + +#pragma pack(1) +typedef struct { + // + // Common Section of RC + // + UINT32 MmiohBase; + UINT16 MmiohSize; + UINT8 MmcfgBase; + UINT8 MmcfgSize; + UINT8 IsocEn; + UINT8 NumaEn; + UINT8 MirrorMode; + UINT8 LockStep; + UINT8 CpuStepping; + UINT8 SystemRasType; + UINT32 FpgaPresentBitMap; + UINT8 IssCapable; + UINT8 PbfCapable; +} SOCKET_COMMONRC_CONFIGURATION; +#pragma pack() + +#endif + + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketIioVariable.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketIioVariable.h new file mode 100644 index 0000000000..8ee87eabd1 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketIioVariable.h @@ -0,0 +1,264 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SOCKET_IIO_CONFIG_DATA_H__ +#define __SOCKET_IIO_CONFIG_DATA_H__ + +#include +#include "SocketConfiguration.h" + +extern EFI_GUID gEfiSocketIioVariableGuid; +#define SOCKET_IIO_CONFIGURATION_NAME L"SocketIioConfig" + +#pragma pack(1) + + +typedef struct { + +/** +================================================================================================== +================================== VTd Setup Options ================================== +================================================================================================== +**/ + UINT8 VTdSupport; + UINT8 InterruptRemap; + UINT8 CoherencySupport; + UINT8 ATS; + UINT8 PostedInterrupt; + UINT8 PassThroughDma; +/** +================================================================================================== +================================== PCIE Setup Options ================================== +================================================================================================== +**/ + UINT8 IioPresent[MAX_SOCKET]; + UINT8 VtdAcsWa; + + // Platform data needs to update these PCI Configuration settings + UINT8 SLOTHPCAP[MAX_TOTAL_PORTS]; // Slot Hot Plug capable - Slot Capabilities (D0-10 / F0 / R0xA4 / B6) + UINT8 SLOTHPSUP[MAX_TOTAL_PORTS]; // Hot Plug surprise supported - Slot Capabilities (D0-10 / F0 / R0xA4 / B5) + + // General PCIE Configuration + UINT8 ConfigIOU0[MAX_SOCKET]; // 00-x4x4x4x4, 01-x4x4x8NA, 02-x8NAx4x4, 03-x8NAx8NA, 04-x16 (P5p6p7p8) + UINT8 ConfigIOU1[MAX_SOCKET]; // 00-x4x4x4x4, 01-x4x4x8NA, 02-x8NAx4x4, 03-x8NAx8NA, 04-x16 (P9p10p11p12) + UINT8 ConfigIOU2[MAX_SOCKET]; // 00-x4x4x4x4, 01-x4x4x8NA, 02-x8NAx4x4, 03-x8NAx8NA, 04-x16 (P1p2p3p4) + UINT8 ConfigMCP0[MAX_SOCKET]; // 04-x16 (p13) + UINT8 ConfigMCP1[MAX_SOCKET]; // 04-x16 (p14) + UINT8 CompletionTimeoutGlobal; // + UINT8 CompletionTimeoutGlobalValue; + UINT8 CompletionTimeout[MAX_SOCKET]; // On Setup + UINT8 CompletionTimeoutValue[MAX_SOCKET]; // On Setup + UINT8 CoherentReadPart; + UINT8 CoherentReadFull; + UINT8 PcieGlobalAspm; // + UINT8 StopAndScream; // + UINT8 SnoopResponseHoldOff; // + // + // PCIE capability + // + UINT8 PCIe_LTR; // + UINT8 PcieExtendedTagField; // + UINT8 PCIe_AtomicOpReq; // + UINT8 PcieMaxReadRequestSize; // + + + UINT8 RpCorrectableErrorEsc[MAX_SOCKET]; //on Setup + UINT8 RpUncorrectableNonFatalErrorEsc[MAX_SOCKET]; //on Setup + UINT8 RpUncorrectableFatalErrorEsc[MAX_SOCKET]; //on Setup + + // mixc PCIE configuration + UINT8 PcieLinkDis[MAX_TOTAL_PORTS]; // On Setup + UINT8 PcieAspm[MAX_TOTAL_PORTS]; // On Setup + UINT8 PcieCommonClock[MAX_TOTAL_PORTS]; // On Setup + UINT8 PcieMaxPayload[MAX_TOTAL_PORTS]; // On Setup PRD + UINT8 PcieDState[MAX_TOTAL_PORTS]; // On Setup + UINT8 PcieL0sLatency[MAX_TOTAL_PORTS]; // On Setup + UINT8 PcieL1Latency[MAX_TOTAL_PORTS]; // On Setup + UINT8 MsiEn[MAX_TOTAL_PORTS]; // On Setup + UINT8 ExtendedSync[MAX_TOTAL_PORTS]; // On Setup + UINT8 InbandPresenceDetect[MAX_TOTAL_PORTS]; // Not implemented in code + UINT8 PciePortDisable[MAX_TOTAL_PORTS]; // Not implemented in code + UINT8 PciePmeIntEn[MAX_TOTAL_PORTS]; // Not implemented in code + UINT8 IODC[MAX_TOTAL_PORTS]; // On Setup + + // + // PCIE setup options for Link Control2 + // + UINT8 PciePortLinkSpeed[MAX_TOTAL_PORTS]; //on Setup + UINT8 ComplianceMode[MAX_TOTAL_PORTS]; // On Setup PRD + UINT8 PciePortLinkMaxWidth[MAX_TOTAL_PORTS]; // On Setup + UINT8 DeEmphasis[MAX_TOTAL_PORTS]; // On Setup + + // + // PCIE setup options for MISCCTRLSTS + // + UINT8 EOI[MAX_TOTAL_PORTS]; // On Setup + UINT8 MSIFATEN[MAX_TOTAL_PORTS]; //On Setup. + UINT8 MSINFATEN[MAX_TOTAL_PORTS]; //On Setup. + UINT8 MSICOREN[MAX_TOTAL_PORTS]; //On Setup. + UINT8 ACPIPMEn[MAX_TOTAL_PORTS]; //On Setup + UINT8 DISL0STx[MAX_TOTAL_PORTS]; //On Setup + UINT8 P2PWrtDis[MAX_TOTAL_PORTS]; //On Setup Peer 2 Peer + UINT8 P2PRdDis[MAX_TOTAL_PORTS]; //On Setup Peer 2 peer + UINT8 DisPMETOAck[MAX_TOTAL_PORTS]; //On Setup + UINT8 ACPIHP[MAX_TOTAL_PORTS]; //On Setup + UINT8 ACPIPM[MAX_TOTAL_PORTS]; //On Setup + UINT8 SRIS[MAX_TOTAL_PORTS]; //On Setup + UINT8 TXEQ[MAX_TOTAL_PORTS]; //On Setup + UINT8 ECRC[MAX_TOTAL_PORTS]; //On Setup + // + // PCIE RAS (Errors) + // + + UINT8 PcieUnsupportedRequests[MAX_TOTAL_PORTS]; // Unsupported Request per-port option + + // + // PCIE Link Training Ctrl + // + +/** +================================================================================================== +================================== Crystal Beach 3 Setup Options =========================== +================================================================================================== +**/ + UINT8 Reserved1[MAX_SOCKET]; + UINT8 Cb3DmaEn[TOTAL_CB3_DEVICES]; // on setup + UINT8 Cb3NoSnoopEn[TOTAL_CB3_DEVICES]; // on setup + UINT8 DisableTPH; + UINT8 PrioritizeTPH; + UINT8 CbRelaxedOrdering; + +/** +================================================================================================== +================================== MISC IOH Setup Options ========================== +================================================================================================== +**/ + + // The following are for hiding each individual device and function + UINT8 PEXPHIDE[MAX_TOTAL_PORTS]; // Hide any of the DMI or PCIE devices - SKT 0,1,2,3; Device 0-10 PRD + UINT8 DevPresIoApicIio[TOTAL_IIO_STACKS]; + // Hide IOAPIC Device 5, Function 4 + UINT8 PCUF6Hide; // Hide Device PCU Device 30, Function 6 + UINT8 EN1K; // Enable/Disable 1K granularity of IO for P2P bridges 0:20:0:98 bit 2 + UINT8 DualCvIoFlow; // Dual CV IO Flow + UINT8 Pci64BitResourceAllocation; + UINT8 PcieBiosTrainEnable; // Used as a work around for A0 PCIe + UINT8 MultiCastEnable; // MultiCastEnable test enable + UINT8 McastBaseAddrRegion; // McastBaseAddrRegion + UINT8 McastIndexPosition; // McastIndexPosition + UINT8 McastNumGroup; // McastNumGroup + + + UINT8 HidePEXPMenu[MAX_TOTAL_PORTS]; // to suppress /display the PCIe port menu + +/** +================================================================================================== +================================== NTB Related Setup Options ========================== +================================================================================================== +**/ + UINT8 NtbPpd[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizeOverride[MAX_NTB_PORTS]; //on setup option + UINT8 NtbSplitBar[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizePBar23[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizePBar45[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizePBar4[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizePBar5[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizeSBar23[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizeSBar45[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizeSBar4[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizeSBar5[MAX_NTB_PORTS]; //on setup option + UINT8 NtbSBar01Prefetch[MAX_NTB_PORTS]; //on setup option + UINT8 NtbXlinkCtlOverride[MAX_NTB_PORTS]; //on setup option + +/** +================================================================================================== +================================== VMD Related Setup Options ========================== +================================================================================================== +**/ + UINT8 VMDEnabled[MAX_VMD_STACKS]; + UINT8 VMDPortEnable[MAX_VMD_PORTS]; + UINT8 VMDHotPlugEnable[MAX_VMD_STACKS]; + UINT8 VMDCfgBarSz[MAX_VMD_STACKS]; + UINT8 VMDCfgBarAttr[MAX_VMD_STACKS]; + UINT8 VMDMemBarSz1[MAX_VMD_STACKS]; + UINT8 VMDMemBar1Attr[MAX_VMD_STACKS]; + UINT8 VMDMemBarSz2[MAX_VMD_STACKS]; + UINT8 VMDMemBar2Attr[MAX_VMD_STACKS]; + + + /** + ================================================================================================== + ================================== PCIe SSD Related Setup Options ========================== + ================================================================================================== + **/ + + UINT8 PcieAICEnabled[MAX_VMD_STACKS]; + UINT8 PcieAICPortEnable[MAX_VMD_PORTS]; + UINT8 PcieAICHotPlugEnable[MAX_VMD_STACKS]; + + /** + ================================================================================================== + ================================== PCIe Global Related Setup Options ========================== + ================================================================================================== + **/ + UINT8 NoSnoopRdCfg; //on Setup + UINT8 NoSnoopWrCfg; //on Setup + UINT8 MaxReadCompCombSize; //on Setup + UINT8 ProblematicPort; //on Setup + UINT8 DmiAllocatingFlow; //on Setup + UINT8 PcieAllocatingFlow; //on Setup + UINT8 PcieHotPlugEnable; //on Setup + UINT8 PcieAcpiHotPlugEnable; //on Setup + UINT8 HaltOnDmiDegraded; //on Setup + UINT8 RxClockWA; + UINT8 GlobalPme2AckTOCtrl; //on Setup + UINT8 MctpEn; //On Setup + UINT8 PcieSlotOprom1; //On Setup + UINT8 PcieSlotOprom2; //On Setup + UINT8 PcieSlotOprom3; //On Setup + UINT8 PcieSlotOprom4; //On Setup + UINT8 PcieSlotOprom5; //On Setup + UINT8 PcieSlotOprom6; //On Setup + UINT8 PcieSlotOprom7; //On Setup + UINT8 PcieSlotOprom8; //On Setup + UINT8 PcieSlotItemCtrl; //On Setup + UINT8 PcieRelaxedOrdering; //On Setup + UINT8 PciePhyTestMode; //On setup +/** +================================================================================================== +================================== Iio Related Setup Options ========================== +================================================================================================== +**/ + + UINT8 RtoEnable; + UINT8 RtoLtssmLogger; // On Setup + UINT8 RtoLtssmLoggerStop; // On Setup + UINT8 RtoLtssmLoggerSpeed; // On Setup + UINT8 RtoLtssmLoggerMask; // On Setup + UINT8 RtoJitterLogger; // On Setup + UINT32 RtoSocketDevFuncHide[MAX_DEVHIDE_REGS_PER_SYSTEM]; // On Setup + UINT8 RtoGen3NTBTestCard[MAX_TOTAL_PORTS]; // On Setup + + UINT8 RtoGen3OverrideMode[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3TestCard[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh2_Precursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh2_Cursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh2_Postcursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh3_Precursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh3_Cursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh3_Postcursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoDnTxPreset[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoRxPreset[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoUpTxPreset[MAX_TOTAL_PORTS]; //On Setup + + UINT8 InboundConfiguration[MAX_TOTAL_PORTS]; //On Setup + // Nvram variables for CLX64L CPUs. + UINT8 CLX64LCpuPresent; +} SOCKET_IIO_CONFIGURATION; +#pragma pack() + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketMemoryVariable.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketMemoryVariable.h new file mode 100644 index 0000000000..823e67e3f8 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketMemoryVariable.h @@ -0,0 +1,321 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SOCKET_MEMORY_CONFIG_DATA_H__ +#define __SOCKET_MEMORY_CONFIG_DATA_H__ + + +#include +#include "SocketConfiguration.h" +#include + +extern EFI_GUID gEfiSocketMemoryVariableGuid; +#define SOCKET_MEMORY_CONFIGURATION_NAME L"SocketMemoryConfig" + +#pragma pack(1) +typedef struct { + UINT8 RtoMaxNodeInterleave; + UINT8 MemoryHotPlugBase; + UINT8 MemoryHotPlugLen; + UINT8 Srat; + UINT8 SratMemoryHotPlug; + UINT8 SratCpuHotPlug; + UINT8 PagePolicy; + UINT8 PatrolScrub; + UINT8 PatrolScrubDuration; + UINT8 PatrolScrubAddrMode; + UINT8 partialmirror; + UINT8 partialmirrorsad0; + UINT8 PartialMirrorUefi; + UINT16 PartialMirrorUefiPercent; + UINT16 partialmirrorsize[MAX_PARTIAL_MIRROR]; // Array of sizes of different partial mirrors + UINT8 DemandScrubMode; + UINT8 SddcPlusOneEn; + UINT16 spareErrTh; + UINT8 DieSparing; + UINT8 Reserved1; + UINT8 ADDDCEn; + UINT8 AdddcErrInjEn; + UINT8 leakyBktLo; + UINT8 leakyBktHi; + UINT8 DutyCycleTraining; + UINT8 refreshMode; + UINT8 dllResetTestLoops; + UINT8 DdrMemoryType; + UINT8 HwMemTest; + UINT16 MemTestLoops; + UINT8 EccSupport; + UINT8 SocketInterleaveBelow4GB; + UINT8 Reserved2; + UINT8 Reserved3; + UINT8 Reserved4[16]; + UINT8 volMemMode; + UINT8 Reserved5; + UINT8 memInterleaveGran1LM; + UINT8 RtoMemInterleaveGranPMemUMA; + UINT8 RtoCfgMask2LM; + UINT8 ImcInterleaving; + UINT8 ChannelInterleaving; + UINT8 RankInterleaving; + UINT8 CkeProgramming; + UINT8 Reserved6; + UINT8 PkgcSrefEn; + UINT8 CkeIdleTimer; + UINT8 ApdEn; + UINT8 PpdEn; + UINT8 DdrtCkeEn; + UINT8 OppSrefEn; + UINT8 DdrtSrefEn; + UINT8 MdllOffEn; + UINT8 CkMode; + UINT8 MemTestOnFastBoot; + UINT8 AttemptFastBoot; + UINT8 AttemptFastBootCold; + UINT8 bdatEn; + UINT8 ScrambleEnDDRT; + UINT8 ScrambleEn; // for ddr4 + UINT8 allowCorrectableError; + UINT16 ScrambleSeedLow; + UINT16 ScrambleSeedHigh; + UINT8 CustomRefreshRateEn; + UINT8 CustomRefreshRate; + UINT8 mcBgfThreshold; + UINT8 readVrefCenter; + UINT8 wrVrefCenter; + UINT8 haltOnMemErr; + UINT8 thermalthrottlingsupport; + UINT8 thermalmemtrip; + UINT8 DimmTempStatValue; + UINT8 XMPProfilesSup; + UINT8 XMPMode; + UINT8 tCAS; + UINT8 tRP; + UINT8 tRCD; + UINT8 tRAS; + UINT8 tWR; + UINT16 tRFC; + UINT8 tRRD; + UINT8 tRTP; + UINT8 tWTR; + UINT8 tFAW; + UINT8 tCWL; + UINT8 tRC; + UINT8 commandTiming; + UINT16 tREFI; + UINT8 DdrFreqLimit; + UINT16 Vdd; + UINT8 lrdimmModuleDelay; + UINT32 rmtPatternLength; + UINT32 rmtPatternLengthExt; + UINT8 check_pm_sts; + UINT8 check_platform_detect; + UINT8 MemPwrSave; + UINT8 ElectricalThrottlingMode; + UINT8 MultiThreaded; + UINT8 promoteMrcWarnings; + UINT8 promoteWarnings; + UINT8 oppReadInWmm; + UINT16 normOppInterval; + UINT8 sck0ch0; + UINT8 sck0ch1; + UINT8 sck0ch2; + UINT8 sck0ch3; + UINT8 sck0ch4; + UINT8 sck0ch5; + UINT8 sck1ch0; + UINT8 sck1ch1; + UINT8 sck1ch2; + UINT8 sck1ch3; + UINT8 sck1ch4; + UINT8 sck1ch5; + UINT8 sck2ch0; + UINT8 sck2ch1; + UINT8 sck2ch2; + UINT8 sck2ch3; + UINT8 sck2ch4; + UINT8 sck2ch5; + UINT8 sck3ch0; + UINT8 sck3ch1; + UINT8 sck3ch2; + UINT8 sck3ch3; + UINT8 sck3ch4; + UINT8 sck3ch5; + UINT8 mdllSden; + UINT8 memhotSupport; + UINT8 MemhotOutputOnlyOpt; + UINT8 ADREn; + UINT8 RankMargin; + UINT8 EnableBacksideRMT; + UINT8 EnableBacksideCMDRMT; + UINT8 Reserved_0; + UINT8 rankMaskEn; + UINT8 RankSparing; + UINT8 multiSparingRanks; + UINT8 caParity; + UINT8 dimmIsolation; + UINT8 smbSpeed; + UINT8 EnforcePOR; + UINT8 pda; + UINT8 turnaroundOpt; + UINT8 dramrxeqEnable; + UINT8 rxmodctleEnable; + UINT8 oneRankTimingMode; + UINT8 eyeDiagram; + + UINT8 Reserved9; + UINT8 Reserved10; + UINT8 Reserved11; + UINT8 Reserved12; + UINT8 Reserved13; + UINT8 Reserved14; + UINT8 Reserved15; + UINT8 Reserved16; + UINT8 Reserved17; + UINT8 Reserved18; + UINT8 Reserved19; + UINT8 Reserved20; + UINT8 Reserved21; + UINT8 Reserved22; + UINT8 Reserved23; + UINT8 Reserved24; + UINT8 Reserved25; + UINT8 Reserved26; + UINT8 Reserved27; + UINT8 Reserved28; + UINT8 DramRaplInit; + UINT8 BwLimitTfOvrd; + UINT8 perbitmargin; + UINT8 DramRaplExtendedRange; + UINT8 CmsEnableDramPm; + UINT8 logParsing; + UINT8 WritePreamble; + UINT8 ReadPreamble; + UINT8 WrCRC; + + UINT8 Reserved_1; + UINT8 Reserved_2; + UINT8 Reserved_3; + UINT8 Reserved_4; + UINT8 Reserved_5; + UINT8 Reserved_6; + UINT8 Reserved_7; + UINT8 Reserved_8; + + UINT8 RmtOnColdFastBoot; + UINT8 mrcRepeatTest; + UINT8 RtoLowMemChannel; + UINT8 RtoHighAddressStartBitPosition; + UINT8 staggerref; + UINT32 memFlows; + UINT32 memFlowsExt; + UINT8 Blockgnt2cmd1cyc; + UINT8 Disddrtopprd; + UINT8 Reserved8; + UINT8 setSecureEraseAllDIMMs; + UINT8 setSecureEraseSktCh[MAX_AEP_DIMM_SETUP]; + UINT8 SetSecureEraseSktChHob[MAX_AEP_DIMM_SETUP]; + // + // PPR related + // + UINT8 pprType; + UINT8 pprErrInjTest; + // CR QoS Configuration Profiles + UINT8 FastGoConfig; + UINT8 Reserved_11; + UINT8 Reserved_12; + UINT8 Reserved_13; + UINT8 ADRDataSaveMode; + UINT8 eraseArmNVDIMMS; + UINT8 restoreNVDIMMS; + UINT8 interNVDIMMS; + UINT8 imcBclk; + UINT8 spdCrcCheck; + UINT8 TrainingResultOffsetFunctionEnable; + UINT16 OffsetTxDq; + UINT16 OffsetRxDq; + UINT16 OffsetTxVref; + UINT16 OffsetRxVref; + UINT16 OffsetCmdAll; + UINT16 OffsetCmdVref; + UINT16 OffsetCtlAll; + UINT8 PmemCaching; + UINT8 tRRD_L; + UINT8 turnaroundOptDdrt; + UINT8 NvmdimmPerfConfig; // NVMDIMM Performance related + UINT8 AepOnSystem; + UINT8 NgnEccExitCorr; + UINT8 NgnArsPublish; + UINT16 NgnAveragePower; + UINT8 NgnThrottleTemp; + UINT8 AppDirectMemoryHole; + UINT8 LatchSystemShutdownState; + UINT8 EliminateDirectoryInFarMemory; + UINT8 NvmdimmPowerCyclePolicy; + UINT8 ShortStroke2GB; + UINT8 Reserved29; + UINT8 Reserved30; + UINT8 Reserved31; + UINT8 NvmQos; + UINT8 ExtendedType17; + UINT8 Force1ChWayFM; + UINT8 DisableDirForAppDirect; + UINT8 NvmMediaStatusException; + UINT8 sck4ch0; + UINT8 sck4ch1; + UINT8 sck4ch2; + UINT8 sck4ch3; + UINT8 sck4ch4; + UINT8 sck4ch5; + UINT8 sck5ch0; + UINT8 sck5ch1; + UINT8 sck5ch2; + UINT8 sck5ch3; + UINT8 sck5ch4; + UINT8 sck5ch5; + UINT8 sck6ch0; + UINT8 sck6ch1; + UINT8 sck6ch2; + UINT8 sck6ch3; + UINT8 sck6ch4; + UINT8 sck6ch5; + UINT8 sck7ch0; + UINT8 sck7ch1; + UINT8 sck7ch2; + UINT8 sck7ch3; + UINT8 sck7ch4; + UINT8 sck7ch5; + UINT8 Reserved32; + UINT8 EadrSupport; + UINT8 Reserved33; + UINT8 FactoryResetClear; + UINT8 LsxImplementation; + UINT32 NvdimmSmbusMaxAccessTime; + UINT32 NvdimmSmbusReleaseDelay; + UINT8 Reserved34; + UINT8 Reserved35; + UINT8 TrfcPerfEnable; + UINT8 PanicWm; + UINT32 AdvMemTestOptions; + UINT8 AdvMemTestResetList; + UINT8 AdvMemTestCondition; + UINT16 AdvMemTestCondVdd; + UINT8 AdvMemTestCondTwr; + UINT16 AdvMemTestCondTrefi; + UINT32 AdvMemTestCondPause; + UINT16 OffsetRecEn; + UINT8 RcvenAve; + UINT8 allowCorrectableMemTestError; + UINT8 AdrPatrolScrubDisable; + UINT8 PatrolErrorDowngradeEn; + UINT8 BankXorEnable; + UINT8 AdvMemTestRetryAfterRepair; +} SOCKET_MEMORY_CONFIGURATION; + +#pragma pack() + +#endif + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketMpLinkVariable.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketMpLinkVariable.h new file mode 100644 index 0000000000..79cd5a05ab --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketMpLinkVariable.h @@ -0,0 +1,173 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SOCKET_MP_LINK_CONFIG_DATA_H__ +#define __SOCKET_MP_LINK_CONFIG_DATA_H__ + +#include +#include "SocketConfiguration.h" + +extern EFI_GUID gEfiSocketMpLinkVariableGuid; +#define SOCKET_MP_LINK_CONFIGURATION_NAME L"SocketMpLinkConfig" + +#pragma pack(1) +typedef struct { + // SKXTODO: rename to Kti when removing HSX code + UINT8 QpiSetupNvVariableStartTag; // This must be the very first one of the whole KTI Setup NV variable! + + // + // Used by the PciHostBridge DXE driver, these variables don't need to be exposed through setup options + // The variables are used as a communication vehicle from the PciHostBridge DXE driver to an OEM hook + // which updates the KTI resource map + // + // + // KTI host structure inputs + // + UINT8 BusRatio[MAX_SOCKET]; + UINT8 LegacyVgaSoc; // Socket that claims the legacy VGA range; valid values are 0-3; 0 is default. + UINT8 LegacyVgaStack; // Stack that claims the legacy VGA range; valid values are 0-3; 0 is default. + UINT8 MmioP2pDis; // 1 - Disable; 0 - Enable + UINT8 DebugPrintLevel; // Bit 0 - Fatal, Bit1 - Warning, Bit2 - Info Summary; Bit 3 - Info detailed. 1 - Enable; 0 - Disable + UINT8 DegradePrecedence; // Use DEGRADE_PRECEDENCE definition; TOPOLOGY_PRECEDENCE is default + + // + // Phy/Link Layer Options + // + UINT8 QpiLinkSpeedMode; // Link speed mode selection; 0 - Slow Speed; 1- Full Speed + UINT8 QpiLinkSpeed; // One of SPEED_REC_96GT, SPEED_REC_104GT, MAX_KTI_LINK_SPEED (default), FREQ_PER_LINK + UINT8 KtiLinkL0pEn; // 0 - Disable, 1 - Enable, 2- Auto (default) + UINT8 KtiLinkL1En; // 0 - Disable, 1 - Enable, 2- Auto (default) + UINT8 KtiFailoverEn; // 0 - Disable, 1 - Enable, 2- Auto (default) + UINT8 KtiLbEn; // 0 - Disable(default), 1 - Enable + UINT8 KtiCrcMode; // 0 - 8 bit CRC 1 - 16 bit CRC Mode + UINT8 QpiCpuSktHotPlugEn; // 0 - Disable (default), 1 - Enable + UINT8 KtiCpuSktHotPlugTopology; // 0 - 4S Topology (default), 1 - 8S Topology + UINT8 KtiSkuMismatchCheck; // 0 - No, 1 - Yes (default) + UINT8 KtiLinkVnaOverride; // 0x100 - per link, 0xff - max (default), 0x00 - min + UINT8 SncEn; // 0 - Disable (default), 1 - Enable + UINT8 IoDcMode; // 0 - Disable IODC, 1 - AUTO (default), 2 - IODC_EN_REM_INVITOM_PUSH, 3 - IODC_EN_REM_INVITOM_ALLOCFLOW + // 4 - IODC_EN_REM_INVITOM_ALLOC_NONALLOC, 5 - IODC_EN_REM_INVITOM_AND_WCILF + UINT8 DirectoryModeEn; // 0 - Disable; 1 - Enable (default) + UINT8 XptPrefetchEn; // XPT Prefetch : 1 - Enable (Default); 0 - Disable + UINT8 KtiPrefetchEn; // KTI Prefetch : 1 - Enable (Default); 0 - Disable + UINT8 RdCurForXptPrefetchEn; // RdCur for XPT Prefetch : 0 - Disable, 1 - Enable, 2- Auto (default) + UINT8 IrqThreshold; // KTI IRQ Threshold setting + UINT8 TscSyncEn; // TSC Sync Enable: 0 - Disable; 1 - Enable; 2 - AUTO (default) + UINT8 StaleAtoSOptEn; // HA A to S directory optimization + UINT8 LLCDeadLineAlloc; // Never fill dead lines in LLC: 1 - Enable, 0 - Disable + + UINT8 Reserved1; + UINT8 Reserved2; + UINT8 Reserved3; + UINT8 Reserved4; + UINT8 Reserved5; + UINT8 Reserved6; + UINT8 Reserved7; + UINT8 Reserved8; + UINT8 Reserved9; + UINT8 Reserved10; + UINT8 Reserved11; + UINT8 Reserved12; + UINT8 Reserved13; + UINT8 Reserved14; + UINT8 Reserved15; + UINT8 Reserved16; + UINT8 Reserved17; + UINT8 Reserved18; + + +#define CSICPUPRTVARIABLE(x) x##KtiPortDisable;x##KtiLinkSpeed;x##KtiLinkVnaOverride; + + UINT8 KtiCpuPerPortStartTag; + CSICPUPRTVARIABLE(UINT8 Cpu0P0) + CSICPUPRTVARIABLE(UINT8 Cpu0P1) + CSICPUPRTVARIABLE(UINT8 Cpu0P2) +#if MAX_SOCKET > 1 + CSICPUPRTVARIABLE(UINT8 Cpu1P0) + CSICPUPRTVARIABLE(UINT8 Cpu1P1) + CSICPUPRTVARIABLE(UINT8 Cpu1P2) +#endif +#if MAX_SOCKET > 2 + CSICPUPRTVARIABLE(UINT8 Cpu2P0) + CSICPUPRTVARIABLE(UINT8 Cpu2P1) + CSICPUPRTVARIABLE(UINT8 Cpu2P2) +#endif +#if MAX_SOCKET > 3 + CSICPUPRTVARIABLE(UINT8 Cpu3P0) + CSICPUPRTVARIABLE(UINT8 Cpu3P1) + CSICPUPRTVARIABLE(UINT8 Cpu3P2) +#endif +#if (MAX_SOCKET > 4) + CSICPUPRTVARIABLE(UINT8 Cpu4P0) + CSICPUPRTVARIABLE(UINT8 Cpu4P1) + CSICPUPRTVARIABLE(UINT8 Cpu4P2) +#endif +#if (MAX_SOCKET > 5) + CSICPUPRTVARIABLE(UINT8 Cpu5P0) + CSICPUPRTVARIABLE(UINT8 Cpu5P1) + CSICPUPRTVARIABLE(UINT8 Cpu5P2) +#endif +#if (MAX_SOCKET > 6) + CSICPUPRTVARIABLE(UINT8 Cpu6P0) + CSICPUPRTVARIABLE(UINT8 Cpu6P1) + CSICPUPRTVARIABLE(UINT8 Cpu6P2) +#endif +#if (MAX_SOCKET > 7) + CSICPUPRTVARIABLE(UINT8 Cpu7P0) + CSICPUPRTVARIABLE(UINT8 Cpu7P1) + CSICPUPRTVARIABLE(UINT8 Cpu7P2) +#endif + +#define CSICPUPRTDFXVARIABLE(x) x##ReservedA;x##ReservedB;x##ReservedC;x##ReservedD; + + UINT8 Reserved19; + CSICPUPRTDFXVARIABLE(UINT8 Cpu0P0) + CSICPUPRTDFXVARIABLE(UINT8 Cpu0P1) + CSICPUPRTDFXVARIABLE(UINT8 Cpu0P2) +#if MAX_SOCKET > 1 + CSICPUPRTDFXVARIABLE(UINT8 Cpu1P0) + CSICPUPRTDFXVARIABLE(UINT8 Cpu1P1) + CSICPUPRTDFXVARIABLE(UINT8 Cpu1P2) +#endif +#if MAX_SOCKET > 2 + CSICPUPRTDFXVARIABLE(UINT8 Cpu2P0) + CSICPUPRTDFXVARIABLE(UINT8 Cpu2P1) + CSICPUPRTDFXVARIABLE(UINT8 Cpu2P2) +#endif +#if MAX_SOCKET > 3 + CSICPUPRTDFXVARIABLE(UINT8 Cpu3P0) + CSICPUPRTDFXVARIABLE(UINT8 Cpu3P1) + CSICPUPRTDFXVARIABLE(UINT8 Cpu3P2) +#endif +#if MAX_SOCKET > 4 + CSICPUPRTDFXVARIABLE(UINT8 Cpu4P0) + CSICPUPRTDFXVARIABLE(UINT8 Cpu4P1) + CSICPUPRTDFXVARIABLE(UINT8 Cpu4P2) +#endif +#if MAX_SOCKET > 5 + CSICPUPRTDFXVARIABLE(UINT8 Cpu5P0) + CSICPUPRTDFXVARIABLE(UINT8 Cpu5P1) + CSICPUPRTDFXVARIABLE(UINT8 Cpu5P2) +#endif +#if MAX_SOCKET > 6 + CSICPUPRTDFXVARIABLE(UINT8 Cpu6P0) + CSICPUPRTDFXVARIABLE(UINT8 Cpu6P1) + CSICPUPRTDFXVARIABLE(UINT8 Cpu6P2) +#endif +#if MAX_SOCKET > 7 + CSICPUPRTDFXVARIABLE(UINT8 Cpu7P0) + CSICPUPRTDFXVARIABLE(UINT8 Cpu7P1) + CSICPUPRTDFXVARIABLE(UINT8 Cpu7P2) +#endif + + UINT8 QpiSetupNvVariableEndTag; // This must be the last one of the whole KTI Setup NV variable +} SOCKET_MP_LINK_CONFIGURATION; + +#pragma pack() + +#endif // __SOCKET_MP_LINK_CONFIG_DATA_H__ + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketPciResourceData.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketPciResourceData.h new file mode 100644 index 0000000000..5c8ca9fd74 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketPciResourceData.h @@ -0,0 +1,42 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SOCKET_PCI_RESOURCE_CONFIG_DATA_H__ +#define __SOCKET_PCI_RESOURCE_CONFIG_DATA_H__ + + +#include +#include "SocketConfiguration.h" + +extern EFI_GUID gEfiSocketPciResourceDataGuid; +#define SOCKET_PCI_RESOURCE_CONFIGURATION_DATA_NAME L"SocketPciResourceConfigData" + +#pragma pack(1) +typedef struct { + // + // Used by the PciHostBridge DXE driver, these variables don't need to be exposed through setup options + // The variables are used as a communication vehicle from the PciHostBridge DXE driver to an OEM hook + // which updates the KTI resource map + // + UINT16 PciSocketIoBase[MAX_SOCKET]; + UINT16 PciSocketIoLimit[MAX_SOCKET]; + UINT32 PciSocketMmiolBase[MAX_SOCKET]; + UINT32 PciSocketMmiolLimit[MAX_SOCKET]; + UINT64 PciSocketMmiohBase[MAX_SOCKET]; + UINT64 PciSocketMmiohLimit[MAX_SOCKET]; + UINT16 PciResourceIoBase[TOTAL_IIO_STACKS]; + UINT16 PciResourceIoLimit[TOTAL_IIO_STACKS]; + UINT32 PciResourceMem32Base[TOTAL_IIO_STACKS]; + UINT32 PciResourceMem32Limit[TOTAL_IIO_STACKS]; + UINT64 PciResourceMem64Base[TOTAL_IIO_STACKS]; + UINT64 PciResourceMem64Limit[TOTAL_IIO_STACKS]; +} SOCKET_PCI_RESOURCE_CONFIGURATION_DATA; +#pragma pack() + +#endif // __SOCKET_PCI_RESOURCE_CONFIG_DATA_H__ + + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketPowermanagementVariable.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketPowermanagementVariable.h new file mode 100644 index 0000000000..80491fcf89 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketPowermanagementVariable.h @@ -0,0 +1,227 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SOCKET_POWERMANAGEMENT_CONFIGURATION_DATA_H__ +#define __SOCKET_POWERMANAGEMENT_CONFIGURATION_DATA_H__ + + +#include +#include "SocketConfiguration.h" + +extern EFI_GUID gEfiSocketPowermanagementVarGuid; +#define SOCKET_POWERMANAGEMENT_CONFIGURATION_NAME L"SocketPowerManagementConfig" + +#define NUM_CST_LAT_MSR 3 + +#pragma pack(1) + +typedef struct { + UINT8 LOT26UnusedVrPowerDownEnable; + UINT8 WFRWAEnable; + UINT8 UFSDisable; // Allow Mailbox Command to PCU_MISC_CONFIG Bit[28] + UINT8 ProcessorEistEnable; // EIST or GV3 setup option + + // Config TDP + UINT8 ConfigTDP; + UINT8 ConfigTDPLevel; + + // Individual controls for ACPI sleep states + // ** These can be overridden by AcpiSleepState because these knobs are not available to CRB ** + // + UINT8 AcpiS3Enable; + UINT8 AcpiS4Enable; + + // + //HWPM starts + // + UINT8 ProcessorHWPMEnable; + UINT8 ProcessorAutonomousCstateEnable; + UINT8 ProcessorHWPMInterrupt; + UINT8 ProcessorEPPEnable; + UINT8 ProcessorEppProfile; + UINT8 ProcessorAPSrocketing; + UINT8 ProcessorScalability; + UINT8 ProcessorRaplPrioritization; + UINT8 ProcessorOutofBandAlternateEPB; + // + //HWPM ends + // + UINT8 PStateDomain; // P State Domain + UINT8 ProcessorEistPsdFunc; // EIST/PSD Function select option + UINT8 ProcessorSinglePCTLEn; // PCPS - SINGLE_PCTL select option + UINT8 ProcessorSPD; // PCPS - SPD select option + UINT8 BootPState; // Boot Performance Mode + + // + // Prioritized Base Frequency + // + UINT8 ProcessorActivePbf; // PBF + UINT8 ProcessorConfigurePbf; // PBF High Priority Cores + + // + // Processor Control + // + UINT8 TurboMode; + UINT8 EnableXe; + + //OverClocking + UINT8 OverclockingLock; + + UINT8 TurboRatioLimitRatio[8]; + UINT8 TurboRatioLimitCores[8]; + + UINT8 C2C3TT; + UINT8 DynamicL1; // Enabling Dynamic L1 + UINT8 ProcessorCcxEnable; // Enabling CPU C states of processor + UINT8 PackageCState; // Package C-State Limit + UINT8 C3Enable; // Enable/Disable NHM C3(ACPI C2) report to OS + UINT8 C6Enable; // Enable/Disable NHM C6(ACPI C3) report to OS + UINT8 ProcessorC1eEnable; // Enabling C1E state of processor + UINT8 OSCx; // ACPI C States + + UINT8 CStateLatencyCtrlValid[NUM_CST_LAT_MSR]; // C_STATE_LATENCY_CONTROL_x.Valid + UINT8 CStateLatencyCtrlMultiplier[NUM_CST_LAT_MSR]; // C_STATE_LATENCY_CONTROL_x.Multiplier + UINT16 CStateLatencyCtrlValue[NUM_CST_LAT_MSR]; // C_STATE_LATENCY_CONTROL_x.Value + + UINT8 TStateEnable; // T states enable? + UINT8 OnDieThermalThrottling; // Throtte ratio + UINT8 ProchotLock; + UINT8 EnableProcHot; + UINT8 EnableThermalMonitor; + UINT8 ProchotResponse; + UINT8 EETurboDisable; + UINT8 SapmctlValCtl; + UINT8 PwrPerfTuning; + UINT8 AltEngPerfBIAS; + UINT8 PwrPerfSwitch; + UINT8 WorkLdConfig; + UINT16 EngAvgTimeWdw1; + + UINT8 ProchotResponseRatio; + UINT8 TCCActivationOffset; + + UINT8 P0TtlTimeLow1; + UINT8 P0TtlTimeHigh1; + + UINT8 PkgCLatNeg; + UINT8 LTRSwInput; + UINT8 SAPMControl; + UINT8 CurrentConfig; + UINT8 PriPlnCurCfgValCtl; + UINT8 Psi3Code; + UINT16 CurrentLimit; + + UINT8 Psi3Thshld; + UINT8 Psi2Code; + UINT8 Psi2Thshld; + UINT8 Psi1Code; + UINT8 Psi1Thshld; + + //Power Management Setup options + UINT8 PkgCstEntryValCtl; + + // PRIMARY_PLANE_CURRENT_CONFIG_CONTROL 0x601 + UINT8 PpcccLock; + + UINT8 SnpLatVld; + UINT8 SnpLatOvrd; + UINT8 SnpLatMult; + UINT16 SnpLatVal; + UINT16 NonSnpLatVld; + UINT8 NonSnpLatOvrd; + UINT8 NonSnpLatMult; + UINT16 NonSnpLatVal; + + // DYNAMIC_PERF_POWER_CTL (CSR 1:30:2:0x64) + UINT8 EepLOverride; + UINT8 EepLOverrideEn; + UINT8 ITurboOvrdEn; + UINT8 CstDemotOvrdEN; + UINT8 TrboDemotOvrdEn; + UINT8 UncrPerfPlmtOvrdEn; + UINT8 EetOverrideEn; + UINT8 IoBwPlmtOvrdEn; + UINT8 ImcApmOvrdEn; // unused + UINT8 IomApmOvrdEn; + UINT8 QpiApmOvrdEn; + UINT8 PerfPLmtThshld; + + // SAPMCTL_CFG (CSR 1:30:1:0xB0) + UINT8 Iio0PkgcClkGateDis[MAX_SOCKET]; //Bit[0] + UINT8 Iio1PkgcClkGateDis[MAX_SOCKET]; //Bit[1] + UINT8 Iio2PkgcClkGateDis[MAX_SOCKET]; //Bit[2] + UINT8 Kti01PkgcClkGateDis[MAX_SOCKET]; //Bit[3] + UINT8 Kti23PkgcClkGateDis[MAX_SOCKET]; //Bit[4] + UINT8 P0pllOffEna[MAX_SOCKET]; //Bit[16] + UINT8 P1pllOffEna[MAX_SOCKET]; //Bit[17] + UINT8 P2pllOffEna[MAX_SOCKET]; //Bit[18] + UINT8 Mc0pllOffEna[MAX_SOCKET]; //Bit[22] + UINT8 Mc1pllOffEna[MAX_SOCKET]; //Bit[23] + UINT8 Mc0PkgcClkGateDis[MAX_SOCKET]; //Bit[6] + UINT8 Mc1PkgcClkGateDis[MAX_SOCKET]; //Bit[7] + UINT8 Kti01pllOffEna[MAX_SOCKET]; //Bit[19] + UINT8 Kti23pllOffEna[MAX_SOCKET]; //Bit[20] + UINT8 SetvidDecayDisable[MAX_SOCKET]; //Bit[30]; + UINT8 SapmCtlLock[MAX_SOCKET]; //Bit[31]; + + // PERF_P_LIMIT_CONTROL (CSR 1:30:2:0xe4) + UINT8 PerfPLimitClip; + UINT8 PerfPLimitEn; + + // PERF_P_LIMIT_CONTROL (CSR 1:30:2:0xe4) >= HSX C stepping + UINT8 PerfPlimitDifferential; + UINT8 PerfPLimitClipC; + + // SKX: PKG_CST_ENTRY_CRITERIA_MASK2 (CSR 1:30:2:0x90) + UINT8 Kti0In[MAX_SOCKET]; + UINT8 Kti1In[MAX_SOCKET]; + UINT8 Kti2In[MAX_SOCKET]; + + // SKX: PKG_CST_ENTRY_CRITERIA_MASK (CSR 1:30:2:0x8c) + UINT8 PcieIio0In[MAX_SOCKET]; + UINT8 PcieIio1In[MAX_SOCKET]; + UINT8 PcieIio2In[MAX_SOCKET]; + UINT8 PcieIio3In[MAX_SOCKET]; + UINT8 PcieIio4In[MAX_SOCKET]; + UINT8 PcieIio5In[MAX_SOCKET]; + + UINT8 FastRaplDutyCycle; + UINT8 TurboPowerLimitLock; + UINT8 TurboPowerLimitCsrLock; + UINT8 PowerLimit1En; + UINT32 PowerLimit1Power; + UINT8 PowerLimit1Time; + UINT8 PkgClmpLim1; + UINT8 PowerLimit2En; + UINT32 PowerLimit2Power; + UINT8 PkgClmpLim2; + UINT8 PowerLimit2Time; + + UINT8 UsePmaxOffsetTable; + UINT8 PmaxSign; + UINT8 PmaxOffset; + + //XTU 3.0 + + UINT8 MaxEfficiencyRatio[MAX_SOCKET]; + UINT8 MaxNonTurboRatio[MAX_SOCKET]; + + // use SPT workarounds - B2P cmd MISC_WORKAROUND_ENABLE + UINT8 SPTWorkaround; + UINT8 VccSAandVccIOdisable; + + UINT8 AvxIccpLevel; + UINT8 IntelSpeedSelectSupport; // Intel Speed Select (ISS) + +} SOCKET_POWERMANAGEMENT_CONFIGURATION; +#pragma pack() + +#endif + + + + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketProcessorCoreVariable.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketProcessorCoreVariable.h new file mode 100644 index 0000000000..e164967fba --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketProcessorCoreVariable.h @@ -0,0 +1,115 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SOCKET_PROCESSORCORE_CONFIGURATION_DATA_H__ +#define __SOCKET_PROCESSORCORE_CONFIGURATION_DATA_H__ + + +#include +#include "SocketConfiguration.h" + +extern EFI_GUID gEfiSocketProcessorCoreVarGuid; +#define SOCKET_PROCESSORCORE_CONFIGURATION_NAME L"SocketProcessorCoreConfig" + +#pragma pack(1) + +typedef struct { + + UINT8 CpuidMaxValue; + UINT8 ExecuteDisableBit; + + UINT8 PchTraceHubEn; // PCH TRACE HUB + UINT8 C1AutoDemotion; // C1 Auto Demotion + UINT8 C3AutoDemotion; // C3 Auto Demotion + UINT8 ProcessorHyperThreadingDisable; // Hyper Threading [ALL] + UINT8 ProcessorLtsxEnable; // Enabling TXT + UINT8 ProcessorVmxEnable; // Enabling VMX + UINT8 ProcessorSmxEnable; // Enabling SMX + UINT8 ProcessorMsrLockControl; // MSR Lock Bit Control + UINT8 DebugInterface; // IA32_DEBUG_INTERFACE_MSR + UINT8 ThreeStrikeTimer; // Disable 3strike timer + UINT8 FastStringEnable; // Fast String + UINT8 MachineCheckEnable; // Machine Check + UINT8 MlcStreamerPrefetcherEnable; // Hardware Prefetch + UINT8 MlcSpatialPrefetcherEnable; // Adjacent Cache Line Prefetch + UINT8 DCUStreamerPrefetcherEnable; // DCU Streamer Prefetcher + UINT8 DCUIPPrefetcherEnable; // DCU IP Prefetcher + UINT8 DCUModeSelection; // DCU Mode Selection + UINT8 ProcessorX2apic; // Enable Processor XAPIC + UINT8 ForceX2ApicIds; // Force to use > 8bit ApicId + UINT8 BspSelection; // Select BSP + UINT8 IedSize; // IED size + UINT8 IedTraceSize; // IED trace size + UINT8 TsegSize; // TSEG size + UINT8 AllowMixedPowerOnCpuRatio; // Allow Mixed PowerOn CpuRatio + UINT8 CheckCpuBist; // check and disable BIST faile core or ignore + UINT8 ProcessorFlexibleRatio; // Non-Turbo Mode Processor Core Ratio Multiplier + UINT8 ProcessorFlexibleRatioOverrideEnable; // Non-Turbo Mode Processor Core Ratio Multiplier Enable + UINT8 Reserved2; // Reserved 2 + UINT8 ForcePhysicalModeEnable; // Force physical destionation mode + UINT8 LlcPrefetchEnable; // LLC Prefetch + UINT8 ProcessorVirtualWireMode; + + UINT8 AesEnable; + UINT8 PpinControl; // PPIN Control MSR + UINT8 LockChipset; // Lock Chipset + UINT8 SkipStopPbet; // Skip StopPbet + + UINT8 BiosAcmErrorReset; // Disable LT-SX and reset system when BIOS ACM error occurs + UINT8 AcmType; // 0x80 = debug signed ACM; 0x40 = NPW production signed ACM; 0x00 = PW production signed ACM + + + UINT64 CoreDisableMask[MAX_SOCKET]; // one for each CPU socket + // IOT/OCLA configs +#ifndef OCLA_TOR_ENTRY_MAX + #define OCLA_TOR_ENTRY_MIN 0 + #define OCLA_TOR_ENTRY_MAX 0x11 // 15 or 17 depending on Isoch on/off + #define OCLA_TOR_ENTRY_DEFAULT 1 + #define OCLA_WAY_MIN 0 + #define OCLA_WAY_MAX 8 // max 8 LLC ways out of 11 can be reserved for OCLA + #define OCLA_WAY_DEFAULT 1 +#endif + UINT8 IotEn[MAX_SOCKET]; + UINT8 OclaMaxTorEntry[MAX_SOCKET]; + UINT8 OclaMinWay[MAX_SOCKET]; + UINT32 IioLlcWaysMask; // MSR CBO_SLICE0_CR_IIO_LLC_WAYS bitmask. - Only Bits[22:0] are used + UINT32 ExpandedIioLlcWaysMask; // MSR INGRESS_SPARE[10:0] bitmask. - Only Bits[10:0] are used + UINT32 RemoteWaysMask; // MSR INGRESS_SPARE[26:16] bitmask. - Only Bits[10:0] are used + UINT32 QlruCfgMask_Lo; // MSR VIRTUAL_MSR_CR_QLRU_CONFIG bitmask - Lower 32-bit + UINT32 QlruCfgMask_Hi; // MSR VIRTUAL_MSR_CR_QLRU_CONFIG bitmask - Higher 32-bit + + + UINT8 PCIeDownStreamPECIWrite; + +// +// Targeted Smi Support +// + UINT8 TargetedSmi; +// +// eSMM Save State Mode +// + UINT8 eSmmSaveState; + + UINT8 PeciInTrustControlBit; //On Setup + + UINT8 Poison; + UINT8 Viral; + UINT8 EVMode; + UINT8 SmbusErrorRecovery; + UINT8 RdtCatOpportunisticTuning; + UINT8 CpuDbpEnable; // Enable/Disable DBP-F + UINT8 L2RfoPrefetchDisable; // L2 RFO Prefetch + UINT8 MonitorMwaitEnabled; + UINT8 MonitorMwaitSwitchPresent; +} SOCKET_PROCESSORCORE_CONFIGURATION; +#pragma pack() + +#endif + + + + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketVariable.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketVariable.h new file mode 100644 index 0000000000..391bfb4e1e --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Guid/SocketVariable.h @@ -0,0 +1,35 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SOCKET_CONFIG_DATA_H__ +#define __SOCKET_CONFIG_DATA_H__ + +#include +#include "SocketConfiguration.h" +#include +#include +#include +#include +#include +#include + +#pragma pack(1) + +typedef struct { + SOCKET_IIO_CONFIGURATION IioConfig; + SOCKET_COMMONRC_CONFIGURATION CommonRcConfig; + SOCKET_MP_LINK_CONFIGURATION CsiConfig; + SOCKET_MEMORY_CONFIGURATION MemoryConfig; + SOCKET_POWERMANAGEMENT_CONFIGURATION PowerManagementConfig; + SOCKET_PROCESSORCORE_CONFIGURATION SocketProcessorCoreConfiguration; +} SOCKET_CONFIGURATION; + + + +#pragma pack() +#endif + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/CpuPpmLib.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/CpuPpmLib.h new file mode 100644 index 0000000000..4773837042 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/CpuPpmLib.h @@ -0,0 +1,707 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _CPU_PPM_LIB_H_ +#define _CPU_PPM_LIB_H_ + + +#include +#include +#include +#include "SysHost.h" +#include "UncoreCommonIncludes.h" + +#define NUM_CST_LAT_MSR 3 + +// +// Value definition for CpuPCPSCtrl +// +#define PCD_CPU_PCPS_SINGLEPCTL 0x00000004 +#define PCD_CPU_PCPS_SPD 0x00000008 +#define PCD_CPU_PCPS_PSTATEDOMAIN 0x00000010 + +// Bits configuration for PcdAdvPwrMgtFlags +#define PCD_CPU_PKG_CST_ENTRY_VAL_CTL 0x00000001 +#define PCD_CPU_SAPM_CTL_VAL_CTL 0x00000002 +#define PCD_CPU_SKIP_PKG_CST_ENTRY 0x00000004 +#define PCD_CPU_SW_LTR_OVRD_CTL 0x00000008 +#define PCD_CPU_PRI_PLN_CURR_CFG_CTL 0x00000010 +#define PCD_CPU_CURRENT_CONFIG 0x00000020 +#define PCU_CPU_EFFICIENT_BOOT 0x00000040 +#define CPU_MSR_LOCK 0x00000080 +#define MPLL_OFF_ENA_AUTO 0x00000100 +#define DYNAMIC_L1_DISABLE 0x00000200 +#define SPT_PCH_WORKAROUND 0x00000400 +#define TURBO_LIMIT_CSR_LOCK 0x00000800 +#define VCCSA_VCCIO_DISABLE 0x00001000 + + +// PCU_CR_PMAX_CONFIG bit definition +#define PCU_CR_PMAX_CFG_OFFSET_SHIFT 0 +#define PCU_CR_PMAX_CFG_LOCK_SHIFT 31 +#define PCU_CR_PMAX_CFG_OFFSET (0x1f << PCU_CR_PMAX_CFG_OFFSET_SHIFT) // Bits 4:0 +#define USER_PMAX_USE_OFFSET_TABLE BIT5 +#define USER_PMAX_NEGATIVE_BIT BIT4 +#define USER_PMAX_VALUE_BIT_MASK 0x0F // Bits 3:0 +#define PCU_CR_PMAX_CFG_LOCK (0x1 << PCU_CR_PMAX_CFG_LOCK_SHIFT) // Bit 31 + +// DYNAMIC_PERF_POWER_CTL bit definition +#define EEP_L_OVERRIDE_SHIFT 26 // Bit 29:26 +#define EEP_L_OVERRIDE_ENABLE_SHIFT 25 // Bit 25 +#define I_TURBO_OVERRIDE_ENABLE_SHIFT 24 // Bit 24 +#define CST_DEMOTION_OVERRIDE_ENABLE_SHIFT 23 // Bit 23 +#define TURBO_DEMOTION_OVERRIDE_ENABLE_SHIFT 22 // Bit 22 +#define UNCORE_PERF_PLIMIT_OVERRIDE_ENABLE_SHIFT 20 // Bit 20 +#define EET_OVERRIDE_ENABLE_SHIFT 18 // Bit 18 +#define IO_BW_PLIMIT_OVERRIDE_ENABLE_SHIFT 15 // Bit 15 +#define IMC_APM_OVERRIDE_ENABLE_SHIFT 10 // Bit 10 +#define IOM_APM_OVERRIDE_ENABLE_SHIFT 5 // Bit 5 +#define QPI_APM_OVERRIDE_ENABLE_SHIFT 0 // Bit 0 +#define EEP_L_OVERRIDE (0xf << EEP_L_OVERRIDE_SHIFT) // Bit 29:26 +#define EEP_L_OVERRIDE_ENABLE (1 << EEP_L_OVERRIDE_ENABLE_SHIFT) // Bit 25 +#define I_TURBO_OVERRIDE_ENABLE (1 << I_TURBO_OVERRIDE_ENABLE_SHIFT) // Bit 24 +#define CST_DEMOTION_OVERRIDE_ENABLE (1 << CST_DEMOTION_OVERRIDE_ENABLE_SHIFT) // Bit 23 +#define TURBO_DEMOTION_OVERRIDE_ENABLE (1 << TURBO_DEMOTION_OVERRIDE_ENABLE_SHIFT) // Bit 22 +#define UNOCRE_PERF_PLIMIT_OVERRIDE_ENABLE (1 << UNCORE_PERF_PLIMIT_OVERRIDE_ENABLE_SHIFT) // Bit 20 +#define EET_OVERRIDE_ENABLE (1 << EET_OVERRIDE_ENABLE_SHIFT) // Bit 18 +#define IO_BW_PLIMIT_OVERRIDE_ENABLE (1 << IO_BW_PLIMIT_OVERRIDE_ENABLE_SHIFT) // Bit 15 +#define IMC_APM_OVERRIDE_ENABLE (1 << IMC_APM_OVERRIDE_ENABLE_SHIFT) // Bit 10 +#define IOM_APM_OVERRIDE_ENABLE (1 << IOM_APM_OVERRIDE_ENABLE_SHIFT) // Bit 5 +#define QPI_APM_OVERRIDE_ENABLE (1 << QPI_APM_OVERRIDE_ENABLE_SHIFT) // Bit 0 +#define DYNAMIC_PERF_POWER_CTL_MASK (0x3C000000 + UNOCRE_PERF_PLIMIT_OVERRIDE_ENABLE + EET_OVERRIDE_ENABLE + IO_BW_PLIMIT_OVERRIDE_ENABLE + IMC_APM_OVERRIDE_ENABLE + IOM_APM_OVERRIDE_ENABLE + QPI_APM_OVERRIDE_ENABLE) + +// CSR_PCIE_ILTR_OVRD (CSR 1:10:1:78) +// SW_LTR_OVRD (MSR 0xa02) -- not used +//CSR_PCIE_ILTR_OVRD bit definition +#define SNOOP_LATENCY_VLD_SHIFT 31 // Bits 31 +#define FORCE_SNOOP_OVRD_SHIFT 30 // Bits 30 +#define SNOOP_LATENCY_MUL_SHIFT 26 // Bits 28:26 +#define SNOOP_LATENCY_Value_SHIFT 16 // Bits 25:16 +#define NON_SNOOP_LATENCY_VLD_SHIFT 15 // Bits 15 +#define FORCE_NON_SNOOP_OVRD_SHIFT 14 // Bits 14 +#define NON_SNOOP_LATENCY_MUL_SHIFT 10 // Bits 12:10 +#define NON_SNOOP_LATENCY_Value_SHIFT 0 // Bits 9:0 +#define SNOOP_LATENCY_VLD_MASK (1 << SNOOP_LATENCY_VLD_SHIFT) // Bits 31 +#define FORCE_SNOOP_OVRD_MASK (1 << FORCE_SNOOP_OVRD_SHIFT) // Bits 30 +#define SNOOP_LATENCY_MUL_MASK (0x7 << SNOOP_LATENCY_MUL_SHIFT) // Bits 28:26 +#define SNOOP_LATENCY_Value_MASK (0x3FF << SNOOP_LATENCY_Value_SHIFT) // Bits 25:16 +#define NON_SNOOP_LATENCY_VLD_MASK (1 << NON_SNOOP_LATENCY_VLD_SHIFT) // Bits 15 +#define FORCE_NON_SNOOP_OVRD_MASK (1 << FORCE_NON_SNOOP_OVRD_SHIFT) // Bits 14 +#define NON_SNOOP_LATENCY_MUL_MASK (0x7 << NON_SNOOP_LATENCY_MUL_SHIFT) // Bits 12:10 +#define NON_SNOOP_LATENCY_Value_MASK (0x3FF << NON_SNOOP_LATENCY_Value_SHIFT) // Bits 9:0 +#define SW_LTR_OVRD_CTL_MASK (SNOOP_LATENCY_VLD_MASK + FORCE_SNOOP_OVRD_MASK + SNOOP_LATENCY_MUL_MASK + SNOOP_LATENCY_Value_MASK + \ + NON_SNOOP_LATENCY_VLD_MASK + FORCE_NON_SNOOP_OVRD_MASK + NON_SNOOP_LATENCY_MUL_MASK + NON_SNOOP_LATENCY_Value_MASK) + +//CSR_PKG_CST_ENTRY_CRITERIA_MASK bit definition +#define DRAM_IN_SR_SHIFT 28 +#define QPI_2_IN_L1_SHIFT 27 +#define QPI_1_IN_L1_SHIFT 26 +#define QPI_0_IN_L1_SHIFT 25 +#define QPI_2_IN_L0S_SHIFT 24 +#define QPI_1_IN_L0S_SHIFT 23 +#define QPI_0_IN_L0S_SHIFT 22 +#define PCIE_IN_L1_SHIFT 11 +#define PCIE_IN_L0S_SHIFT 0 +#define DRAM_IN_SR (1 << DRAM_IN_SR_SHIFT) +#define QPI_2_IN_L1 (1 << QPI_2_IN_L1_SHIFT) +#define QPI_1_IN_L1 (1 << QPI_1_IN_L1_SHIFT) +#define QPI_0_IN_L1 (1 << QPI_0_IN_L1_SHIFT) +#define QPI_2_IN_L0S (1 << QPI_2_IN_L0S_SHIFT) +#define QPI_1_IN_L0S (1 << QPI_1_IN_L0S_SHIFT) +#define QPI_0_IN_L0S (1 << QPI_0_IN_L0S_SHIFT) +#define PCIE_IN_L1 (1 << PCIE_IN_L1_SHIFT) +#define PCIE_IN_L0S (1 << PCIE_IN_L0S_SHIFT) +#define PCIE_IN_LX_MASK 0x7FF // Bit[10:0] +#define MASK_PCIE_BITS 0xFFC00000 // clear bits 21:0 +// For SKX +#define KTI_2_IN_L1_SHIFT 2 +#define KTI_1_IN_L1_SHIFT 1 +#define KTI_0_IN_L1_SHIFT 0 +#define KTI_2_IN_L1 (1 << KTI_2_IN_L1_SHIFT) +#define KTI_1_IN_L1 (1 << KTI_1_IN_L1_SHIFT) +#define KTI_0_IN_L1 (1 << KTI_0_IN_L1_SHIFT) +#define MASK_PCIE_IN_L1_BITS 0xFF000000 // clear bits 23:0 +#define SET_KTI_INPKGCENTRY (KTI_0_IN_L1 + KTI_1_IN_L1 + KTI_2_IN_L1) +#define SET_PCIE_INPKGCENTRY 0xFFFFFF // set bits 23:0 +#define SET_PCIEx_MASK 0xF +#define SET_DMI_MASK 0x1 + + +// CSR Perf PLIMIT bit definition for HSX <= B Stepping +#define I_TURBO_WAIT_PERIOD_SHIFT 19 // Bits 31:19 +#define PERF_P_LIMIT_THRESHOLD_SHIFT 13 // Bits 18:13 +#define I_TURBO_EN_SHIFT 12 // Bit 12 +#define PERF_P_LIMIT_CLIP_SHIFT 6 // Bits 11:6 +#define DISABLE_PERF_P_INPUT_SHIFT 5 // Bit 5 +#define RESOLUTION_MODE_SHIFT 1 // Bits 2:1 +#define REPERF_P_LIMIT_EN_SHIFT 0 // Bit 0 +#define I_TURBO_WAIT_PERIOD (0x1fff << I_TURBO_WAIT_PERIOD_SHIFT) // Bits 31:19 +#define PERF_P_LIMIT_THRESHOLD (0x3f << PERF_P_LIMIT_THRESHOLD_SHIFT) // Bits 18:13 +#define I_TURBO_EN (1 << I_TURBO_EN_SHIFT) // Bit 12 +#define PERF_P_LIMIT_CLIP (0x3f << PERF_P_LIMIT_CLIP_SHIFT) // Bits 11:6 +#define DISABLE_PERF_P_INPUT (1 << DISABLE_PERF_P_INPUT_SHIFT) // Bit 5 +#define RESOLUTION_MODE (3 << RESOLUTION_MODE_SHIFT) // Bits 2:1 +#define REPERF_P_LIMIT_EN (1 << REPERF_P_LIMIT_EN_SHIFT) // Bit 0 + +// CSR Perf PLIMIT bit definition for HSX >= C Stepping & SKX +#define PERF_PLIMIT_DIFFERENTIAL_SHIFT 15 // Bits 17:15 +#define PERF_PLIMIT_DIFFERENTIAL (7 << PERF_PLIMIT_DIFFERENTIAL_SHIFT) // Bits 17:15 +#define PERF_PLIMIT_CLIP_SHIFT 7 // Bits 11:7 +#define PERF_PLIMIT_CLIP (0x1f << PERF_P_LIMIT_CLIP_SHIFT) // Bits 11:7 +#define PERF_PLIMIT_THRESHOLD_SHIFT 1 // Bits 5:1 +#define PERF_PLIMIT_THRESHOLD (0x1f << PERF_P_LIMIT_THRESHOLD_SHIFT) // Bits 5:1 +#define REPERF_PLIMIT_EN_SHIFT 0 // Bit 0 +#define REPERF_PLIMIT_EN (1 << REPERF_P_LIMIT_EN_SHIFT) // Bit 0 +#define PERF_P_LIMIT_CTRL_MASK (PERF_PLIMIT_THRESHOLD + PERF_PLIMIT_CLIP + PERF_PLIMIT_DIFFERENTIAL + REPERF_PLIMIT_EN) + +//CSR SAPMCTLbit definition +#define SAPMCTL_LOCK_SHIFT 31 // Bit 31 for IVT/HSX/SKX +#define SETVID_DECAY_DISABLE_SHIFT 30 // Bit 30 for IVT/KSX/SKX +#define QPI_L0S_PLL_SEN_ENABLE_SHIFT 29 // Bit 29//Only for IVT +#define QPI_L0_PLL_SEN_ENABLE_SHIFT 28 // Bit 28//Only for IVT +#define IIO_L0S_PLL_SEN_ENABLE_SHIFT 27 // Bit 27//Only for IVT +#define IIO_L0_PLL_SEN_ENABLE_SHIFT 26 // Bit 26//Only for IVT +#define QPI2_L0S_PLL_SEN_ENABLE_SHIFT 25 // Bit 25//Only for IVT +#define QPI2_L0_PLL_SEN_ENABLE_SHIFT 24 // Bit 24//Only for IVT +#define QPI2_PKGC_CLOCK_GATE_DISABLE_SHIFT 18 // Bit 18//IVT/HSX +#define QPI01_PKGC_CLOCK_GATE_DISABLE_SHIFT 17 // Bit 17//IVT/HSX +#define IIO_PKGC_CLOCK_GATE_DISABLE_SHIFT 16 // Bit 16//IVT/HSX +#define MDLL_ON_DE_SHIFT 15 // Bit 15//IVT/HSX +#define MPLL_ON_DE_SHIFT 14 // Bit 14//IVT/HSX +#define SACG_MPLL_SHIFT 13 // Bit 13//Only for IVT +#define NSWAKE_SREXIT_SHIFT 12 // Bit 12//IVT/HSX +#define SACG_SREXIT_SHIFT 11 // Bit 11//Only for IVT +#define MDLL_OFF_SEN_SHIFT 10 // Bit 10//Only for IVT +#define MPLL_OFF_SEN_SHIFT 9 // Bit 9//Only for IVT +#define SACG_SEN_SHIFT 8 // Bit 8//Only for IVT +#define FORCE_PPLL_OFF_SHIFT 4 // Bit 4 //IVT/HSX +#define QPLL_OFF_ENA_SHIFT 3 // Bit 3//Only for IVT +#define PPLL_OFF_ENA_SHIFT 2 // Bit 2//IVT/HSX +#define MPLL_OFF_ENA_SHIFT 1 // Bit 1//IVT/HSX +#define SACG_ENA_SHIFT 0 // Bit 0//Only for IVT +#define SAPMCTL_LOCK (1 << SAPMCTL_LOCK_SHIFT) // Bit 31 +#define SETVID_DECAY_DISABLE (1 << SETVID_DECAY_DISABLE_SHIFT) // Bit 30 +#define QPI_L0S_PLL_SEN_ENABLE (1 << QPI_L0S_PLL_SEN_ENABLE_SHIFT) // Bit 29 +#define QPI_L0_PLL_SEN_ENABLE (1 << QPI_L0_PLL_SEN_ENABLE_SHIFT) // Bit 28 +#define IIO_L0S_PLL_SEN_ENABLE (1 << IIO_L0S_PLL_SEN_ENABLE_SHIFT) // Bit 27 +#define IIO_L0_PLL_SEN_ENABLE (1 << IIO_L0_PLL_SEN_ENABLE_SHIFT) // Bit 26 +#define QPI2_L0S_PLL_SEN_ENABLE (1 << QPI2_L0S_PLL_SEN_ENABLE_SHIFT) // Bit 25 +#define QPI2_L0_PLL_SEN_ENABLE (1 << QPI2_L0_PLL_SEN_ENABLE_SHIFT) // Bit 24 +#define QPI2_PKGC_CLOCK_GATE_DISABLE (1 << QPI2_PKGC_CLOCK_GATE_DISABLE_SHIFT) // Bit 18//IVT +#define QPI01_PKGC_CLOCK_GATE_DISABLE (1 << QPI01_PKGC_CLOCK_GATE_DISABLE_SHIFT) // Bit 17//IVT +#define IIO_PKGC_CLOCK_GATE_DISABLE (1 << IIO_PKGC_CLOCK_GATE_DISABLE_SHIFT) // Bit 16//IVT +#define MDLL_ON_DE (1 << MDLL_ON_DE_SHIFT) // Bit 15 +#define MPLL_ON_DE (1 << MPLL_ON_DE_SHIFT) // Bit 14 +#define SACG_MPLL (1 << SACG_MPLL_SHIFT) // Bit 13 +#define NSWAKE_SREXIT (1 << NSWAKE_SREXIT_SHIFT) // Bit 12 +#define SACG_SREXIT (1 << SACG_SREXIT_SHIFT) // Bit 11 +#define MDLL_OFF_SEN (1 << MDLL_OFF_SEN_SHIFT) // Bit 10 +#define MPLL_OFF_SEN (1 << MPLL_OFF_SEN_SHIFT) // Bit 9 +#define SACG_SEN (1 << SACG_SEN_SHIFT) // Bit 8 +#define FORCE_PPLL_OFF (1 << FORCE_PPLL_OFF_SHIFT) // Bit 4 //IVT +#define QPLL_OFF_ENA (1 << QPLL_OFF_ENA_SHIFT) // Bit 3 +#define PPLL_OFF_ENA (1 << PPLL_OFF_ENA_SHIFT) // Bit 2 +#define MPLL_OFF_ENA (1 << MPLL_OFF_ENA_SHIFT) // Bit 1 +#define SACG_ENA (1 << SACG_ENA_SHIFT) // Bit 0 + +//CSR SAPMCTLbit definition for SKX +#define MC1_PKGC_DIG_VOLTAGE_REDUCTION_DISABLE_SHIFT 27 // Bit 27, SKX +#define MC0_PKGC_DIG_VOLTAGE_REDUCTION_DISABLE_SHIFT 26 // Bit 26, SKX +#define MC1_PKGC_IO_VOLTAGE_REDUCTION_DISABLE_SHIFT 25 // Bit 25, SKX +#define MC0_PKGC_IO_VOLTAGE_REDUCTION_DISABLE_SHIFT 24 // Bit 24, SKX +#define MEM_PLL_OFF_EN_SHIFT 22 // Bit 22,23, SKX +#define KTI_PLL_OFF_EN_SHIFT 19 // Bit 19,20, SKX +#define IIO_PLL_OFF_EN_SHIFT 16 // Bit 16,17,18, SKX +#define MC1_PKGC_CLK_GATE_DISABLE_SHIFT 7 // Bit 7, SKX +#define MC0_PKGC_CLK_GATE_DISABLE_SHIFT 6 // Bit 6, SKX +#define KTI23_PKGC_CLK_GATE_DISABLE_SHIFT 4 // Bit 4, SKX +#define KTI01_PKGC_CLK_GATE_DISABLE_SHIFT 3 // Bit 3, SKX +#define IIO012_PKGC_CLK_GATE_DISABLE_SHIFT 0 // Bit 0,1,2, SKX +#define MC1_PKGC_DIG_VOLTAGE_REDUCTION_DISABLE (1 << MC1_PKGC_DIG_VOLTAGE_REDUCTION_DISABLE_SHIFT) // Bit 27, SKX +#define MC0_PKGC_DIG_VOLTAGE_REDUCTION_DISABLE (1 << MC0_PKGC_DIG_VOLTAGE_REDUCTION_DISABLE_SHIFT) // Bit 26, SKX +#define MC1_PKGC_IO_VOLTAGE_REDUCTION_DISABLE (1 << MC1_PKGC_IO_VOLTAGE_REDUCTION_DISABLE_SHIFT) // Bit 25, SKX +#define MC0_PKGC_IO_VOLTAGE_REDUCTION_DISABLE (1 << MC0_PKGC_IO_VOLTAGE_REDUCTION_DISABLE_SHIFT) // Bit 24, SKX +#define MEM_PLL_OFF_EN (3 << MEM_PLL_OFF_EN_SHIFT) // Bit 22,23, SKX +#define KTI_PLL_OFF_EN (3 << KTI_PLL_OFF_EN_SHIFT) // Bit 19,20, SKX +#define IIO_PLL_OFF_EN (7 << IIO_PLL_OFF_EN_SHIFT) // Bit 16,17,18, SKX +#define MC1_PKGC_CLK_GATE_DISABLE (1 << MC1_PKGC_CLK_GATE_DISABLE_SHIFT) // Bit 7, SKX +#define MC0_PKGC_CLK_GATE_DISABLE (1 << MC0_PKGC_CLK_GATE_DISABLE_SHIFT) // Bit 6, SKX +#define KTI23_PKGC_CLK_GATE_DISABLE (1 << KTI23_PKGC_CLK_GATE_DISABLE_SHIFT) // Bit 4, SKX +#define KTI01_PKGC_CLK_GATE_DISABLE (1 << KTI01_PKGC_CLK_GATE_DISABLE_SHIFT) // Bit 3, SKX +#define IIO012_PKGC_CLK_GATE_DISABLE (7 << IIO012_PKGC_CLK_GATE_DISABLE_SHIFT) // Bit 0,1,2, SKX +#define SAPMCTL_MASK (IIO012_PKGC_CLK_GATE_DISABLE + KTI01_PKGC_CLK_GATE_DISABLE + KTI23_PKGC_CLK_GATE_DISABLE + MC0_PKGC_CLK_GATE_DISABLE \ + + MC1_PKGC_CLK_GATE_DISABLE + IIO_PLL_OFF_EN + KTI_PLL_OFF_EN + MEM_PLL_OFF_EN + SETVID_DECAY_DISABLE + SAPMCTL_LOCK \ + + MC1_PKGC_IO_VOLTAGE_REDUCTION_DISABLE + MC0_PKGC_IO_VOLTAGE_REDUCTION_DISABLE + MC1_PKGC_DIG_VOLTAGE_REDUCTION_DISABLE + MC0_PKGC_DIG_VOLTAGE_REDUCTION_DISABLE) + +//Config TDP +#define CONFIG_TDP_LEVEL (3 << CONFIG_TDP_LEVEL_SHIFT) +#define CONFIG_TDP_LEVEL_SHIFT 1 // Bit [2:1] +#define CONFIG_TDP_SHIFT 0 // Bit 0 + +// MSR 0x1FC +#define MSR_POWER_CTL 0x1FC +#define PCH_NEG_DISABLE (1 << 30) +#define PCH_NEG_DISABLE_SHIFT 30 +#define LTR_SW_DISABLE (1 << 29) //LTR_IIO_DISABLE +#define LTR_SW_DISABLE_SHIFT 29 +#define PROCHOT_LOCK (1 << 27) +#define PROCHOT_LOCK_SHIFT 27 +#define PROCHOT_RESPONSE (1 << 26) +#define PROCHOT_RESPONSE_SHIFT 26 +#define PWR_PERF_TUNING_CFG_MODE (1 << 25) +#define PWR_PERF_TUNING_CFG_MODE_SHIFT 25 +#define PWR_PERF_TUNING_ENABLE_DYN_SWITCHING (1 << 24) +#define PWR_PERF_TUNING_ENABLE_DYN_SHIFT 24 +#define PWR_PERF_TUNING_DISABLE_EEP_CTRL (1 << 23) +#define PWR_PERF_TUNING_DISABLE_EEP_SHIFT 23 +#define PWR_PERF_TUNING_DISABLE_SAPM_CTRL (1 << 22) +#define PWR_PERF_TUNING_DISABLE_SAPM_SHIFT 22 +#define DIS_PROCHOT_OUT (1 << 21) +#define DIS_PROCHOT_OUT_SHIFT 21 +#define EE_TURBO_DISABLE (1 << 19) +#define EE_TURBO_DISABLE_SHIFT 19 +#define ENERGY_EFFICIENT_PSTATE_ENABLE (1 << 18) +#define ENERGY_EFFICIENT_PSTATE_ENABLE_SHIFT 18 +#define PHOLD_SR_DISABLE (1 << 17) +#define PHOLD_SR_DISABLE_SHIFT 17 +#define PHOLD_CST_PREVENTION_INIT (1 << 16) +#define PHOLD_CST_PREVENTION_INIT_SHIFT 16 +#define FAST_BRK_INT_EN (1 << 4) +#define FAST_BRK_INT_EN_SHIFT 4 +#define FAST_BRK_SNP_EN (1 << 3) +#define FAST_BRK_SNP_EN_SHIFT 3 +#define SAPM_IMC_C2_POLICY_EN (1 << 2) +#define SAPM_IMC_C2_POLICY_SHIFT 2 +#define C1E_ENABLE (1 << 1) +#define C1E_ENABLE_SHIFT 1 +#define ENABLE_BIDIR_PROCHOT_EN (1 << 0) +#define ENABLE_BIDIR_PROCHOT_EN_SHIFT 0 +#define POWER_CTL_MASK (PCH_NEG_DISABLE + LTR_SW_DISABLE + PWR_PERF_TUNING_CFG_MODE + \ + PWR_PERF_TUNING_ENABLE_DYN_SWITCHING + PWR_PERF_TUNING_DISABLE_EEP_CTRL + \ + PWR_PERF_TUNING_DISABLE_SAPM_CTRL + DIS_PROCHOT_OUT + ENABLE_BIDIR_PROCHOT_EN + C1E_ENABLE) + +// PRIMARY_PLANE_CURRENT_CONFIG_CONTROL 0x601 +#define PSI3_CODE_SHIFT 27 // (Bits 61:59 actully) we operate on a 32 bit register +#define PSI3_THSHLD_SHIFT 20 // (Bits 58:52 actully) we operate on a 32 bit register +#define PSI2_CODE_SHIFT 17 // (Bits 51:49 actully) we operate on a 32 bit register +#define PSI2_THSHLD_SHIFT 10 // (Bits 48:42 actully) we operate on a 32 bit register +#define PSI1_CODE_SHIFT 7 // (Bits 41:39 actully) we operate on a 32 bit register +#define PSI1_THSHLD_SHIFT 0 // (Bits 38:32 actully) we operate on a 32 bit register +#define PPCCC_LOCK_SHIFT 31 +#define CURRENT_LIMIT_SHIFT 0 +#define PSI3_CODE (0x7 << PSI3_CODE_SHIFT) // (Bits 61:59 actully) we operate on a 32 bit register +#define PSI3_THSHLD (0x7f << PSI3_THSHLD_SHIFT) // (Bits 58:52 actully) we operate on a 32 bit register +#define PSI2_CODE (0x7 << PSI2_CODE_SHIFT) // (Bits 51:49 actully) we operate on a 32 bit register +#define PSI2_THSHLD (0x7f << PSI2_THSHLD_SHIFT) // (Bits 48:42 actully) we operate on a 32 bit register +#define PSI1_CODE (0x7 << PSI1_CODE_SHIFT) // (Bits 41:39 actully) we operate on a 32 bit register +#define PSI1_THSHLD (0x7f << PSI1_THSHLD_SHIFT) // (Bits 38:32 actully) we operate on a 32 bit register +#define PPCCC_LOCK (1 << PPCCC_LOCK_SHIFT) +#define CURRENT_LIMIT (0x1fff << CURRENT_LIMIT_SHIFT) + +#define B_PCPS_DISABLE (1 << 25) // Bit 25 + +// MSR_C_STATE_LATENCY_CONTROL_0 0x60a, 60b, 60c +#define VALID_SHIFT 15 +#define MULTIPLIER_SHIFT 10 +#define VALUE_SHIFT 0 + +// MSR_TURBO_POWER_LIMIT 0x610 +// CSR_TURBO_POWER_LIMIT +#define POWER_LIMIT_ENABLE_SHIFT 15 +#define POWER_LIMIT_ENABLE (1 << POWER_LIMIT_ENABLE_SHIFT) // Used as Bit 15 and Bit 47 +#define PKG_CLMP_LIM_SHIFT 16 +#define PKG_CLMP_LIM (1 << PKG_CLMP_LIM_SHIFT) // used as Bit 16 and Bit48 +#define POWER_LIMIT_MASK (0x7FFF) // Bits 14:0 and 46:32 +#define POWER_LIMIT_1_TIME_SHIFT 17 +#define POWER_LIMIT_1_TIME_MASK (0xFE0000) // Bits 23:17 +#define POWER_LIMIT_LOCK_SHIFT 31 +#define POWER_LIMIT_LOCK (1 << POWER_LIMIT_LOCK_SHIFT) // Bit 63 + +// MSR_ENERGY_PERF_BIAS_CONFIG 0xA01 +#define AVG_TIME_Window (0xff << AVG_TIME_Window_SHIFT) // Bits 31:24 +#define PO_TOTAL_TIME_THSHLD_LOW (0x3f << PO_TOTAL_TIME_THSHLD_LOW_SHIFT) // Bits 23:18 +#define PO_TOTAL_TIME_THSHLD_HIGH (0x3f << PO_TOTAL_TIME_THSHLD_HIGH_SHIFT) // Bis 17:12 +#define ALT_ENERGY_PERF_BIAS (0xf << ALT_ENERGY_PERF_BIAS_SHIFT) // Bits 6:3 +#define WORKLD_CONFIG (0x7 << WORKLD_CONFIG_SHIFT) // Bits 2:0 +#define AVG_TIME_Window_SHIFT 24 // Bits 31:24 +#define PO_TOTAL_TIME_THSHLD_LOW_SHIFT 18 // Bits 23:18 +#define PO_TOTAL_TIME_THSHLD_HIGH_SHIFT 12 // Bis 17:12 +#define ALT_ENERGY_PERF_BIAS_SHIFT 3 // Bits 6:3 +#define WORKLD_CONFIG_SHIFT 0 // Bits 2:0 +#define ENERGY_PERF_BIAS_CTRL_MASK (AVG_TIME_Window + PO_TOTAL_TIME_THSHLD_LOW + PO_TOTAL_TIME_THSHLD_HIGH + WORKLD_CONFIG + ALT_ENERGY_PERF_BIAS) + +// +// Cross over Mode +// +#define XOVER_MODE_2TO2 1 +#define XOVER_MODE_1TO1 2 + +// HWPM features +#define HWP_ENABLE 0x01 +#define ACC_ENABLE 0x02 + +// SPT workarounds +#define SPT_WA_ENABLE 0x03 + +// ratio in Performance Control MSR (MSR_IA32_PERF_CTL) +#define B_IA32_PERF_CTRLP_STATE_TARGET (0x7F << 8) + +#pragma pack(1) + +/************************** + Processor Power Management Data structs +***************************/ + +typedef struct _PPM_FROM_PPMINFO_HOB { + UINT8 NumberOfSockets; // # of populated sockets in the system + UINT8 SocketNumber; // which socket + UINT32 SocketPresentBitMap; // bitmap for present CPU packages/nodes + UINT8 IioBusNumber[MAX_SOCKET]; // Bus# for IIO, indexed by CPU Socket/Node ID + UINT8 UncoreBusNumber[MAX_SOCKET]; // Bus# for Uncore, indexed by CPU Socket/Node ID + UINT32 mmCfgBase; + UINT8 DdrXoverMode; // DDR 2.2 Mode + UINT32 OutKtiPerLinkL1En[MAX_SOCKET]; // output kti link enabled status for PM + UINT32 OutPciePerLinkL1En[MAX_SOCKET]; // output PCIe (IIO) link enabled status for PM + UINT8 KtiPortCnt; // num KTI ports residing on each Socket + UINT8 ProcessorPowerUnit[MAX_SOCKET]; // + UINT8 ProcessorTimeUnit[MAX_SOCKET]; // + UINT16 PackageTdp[MAX_SOCKET]; // Package TDP + UINT32 CapId4; //CapId CSR value + UINT32 CpuType; // CpuType + UINT8 CpuStepping; // CpuStepping + UINT32 mNumOfBitShift; // # Bits to shift right APIC ID to get next level APIC ID + UINTN NumberOfProcessors; // number of active threads + BOOLEAN EistCap; // EIST Capability + UINT8 Bios_Reset_Cpl_Phase; + UINT8 HwpmSupport; //HWPM support flag +}PPM_FROM_PPMINFO_HOB; + +typedef struct { + UINT8 Major; // Major Vesion + UINT8 Minor; // Minor Vesion + UINT8 Rev; // Release Version + UINT8 Build; // +} PPM_VERSION; + +typedef union _MSR_REGISTER { + UINT64 Qword; + + struct _DWORDS { + UINT32 Low; + UINT32 High; + } Dwords; + + struct _BYTES { + UINT8 FirstByte; + UINT8 SecondByte; + UINT8 ThirdByte; + UINT8 FouthByte; + UINT8 FifthByte; + UINT8 SixthByte; + UINT8 SeventhByte; + UINT8 EighthByte; + } Bytes; + +} MSR_REGISTER; + +typedef struct { + BOOLEAN C1e; + + UINT32 PkgCstEntryCriteriaMaskKti[MAX_SOCKET]; + UINT32 PkgCstEntryCriteriaMaskPcie[MAX_SOCKET]; + MSR_REGISTER LatencyCtrl[NUM_CST_LAT_MSR]; + +} CSTATE_STRUCT; + +typedef struct { + + BOOLEAN EistEnabled; // option to enable GV3 + UINT8 ConfigTdpLevel; // Config TDP Level + UINT16 CurrentPackageTdp; // Package TDP + UINT8 PcpsCtrl; + +} PSTATE_STRUCT; + +typedef struct { + BOOLEAN Enable; + UINT32 Voltage; + UINT16 RatioLimit[MAX_CORE]; +} XE_STRUCT; + +typedef struct { + UINT8 RatioLimitRatio[8]; + UINT8 RatioLimitRatioMask[8]; + UINT8 RatioLimitCores[8]; + UINT8 RatioLimitCoresMask[8]; +} TURBO_RATIO_LIMIT_RATIO_CORES; + +typedef struct { + UINT8 HWPMEnable; + UINT8 HWPMNative; + UINT8 HWPMOOB; + UINT8 HWPMInterrupt; + UINT8 AutoCState; + UINT8 EPPEnable; + UINT8 EPPProfile; + UINT8 APSrocketing; + UINT8 Scalability; + UINT8 ProcessorRaplPrioritization; + UINT8 OutofBandAlternateEPB; + UINT8 PbfEnabled; + UINT8 ConfigurePbf; + UINT64 PbfHighPriCoreMap[MAX_SOCKET]; // PBF High Priority Cores Bitmap + UINT8 PbfP1HighRatio[MAX_SOCKET]; // PBF P1_High Ratio + UINT8 PbfP1LowRatio[MAX_SOCKET]; // PBF P1_Low Ratio +} HWPM_STRUCT; + +typedef struct { + + UINT8 FastRaplDutyCycle; + UINT8 FuseTjMaxOffset; + + UINT8 OverclockingLock; + UINT8 AvxIccpLevel; + UINT32 AdvPwrMgtCtlFlags; + + MSR_REGISTER PowerCtl; + MSR_REGISTER TurboPowerLimit; + MSR_REGISTER PP0CurrentCfg; + MSR_REGISTER PerfBiasConfig; + + UINT32 ProchotRatio; + UINT32 PmaxConfig; + UINT32 SapmCtl[MAX_SOCKET]; + UINT32 PerPLimitCtl; + UINT32 C2C3TT; + UINT32 DynamicPerPowerCtl; + UINT32 PcieIltrOvrd; + + CSTATE_STRUCT Cst; + PSTATE_STRUCT Pst; + XE_STRUCT Xe; + HWPM_STRUCT Hwpm; + TURBO_RATIO_LIMIT_RATIO_CORES TurboRatioLimitRatioCores; + + UINT8 TCCActivationOffset; + UINT8 IsOppSrefEn; + +} EFI_PPM_STRUCT; + + +typedef struct { + + PPM_VERSION Version; + + EFI_CPU_CSR_ACCESS_PROTOCOL *CpuCsrAccess; + + PPM_FROM_PPMINFO_HOB *Info; + + EFI_PPM_STRUCT *Setup; + + UINTN ProcessorNumber; + +} EFI_CPU_PM_STRUCT; + + +#pragma pack() + +VOID +PStateTransition ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +InitializeCpuPPMLib ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +PpmSetBiosInitDone ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +PpmSetCsrLockBit ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +PpmSetMsrLockBit ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramCSRTurboPowerLimit ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramCsrDynamicPerfPowerCtl ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramCsrSapmCtl ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramCsrSwLtrOvrd ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramCsrPkgCstEntryCriteriaMask( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramCsrResponseRatioCfg( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +EFIAPI +SetupPCIEPkgCstEntryCriteria ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramCsrPerfPlimitControl ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramCsrPmaxConfig ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramMsrPowerCtl ( + EFI_CPU_PM_STRUCT *ppm, + UINTN ProcessorNumber + ); + +VOID +ProgramMsrTurboPowerLimit ( + EFI_CPU_PM_STRUCT *ppm, + UINTN ProcessorNumber + ); + +VOID +ProgramEnergyPerfBiasConfigMsr ( + EFI_CPU_PM_STRUCT *ppm, + UINTN ProcessorNumber + ); + +VOID +ProgMsrPriPlaneCurtCfgCtrL ( + EFI_CPU_PM_STRUCT *ppm, + UINTN ProcessorNumber + ); + +VOID +ProgramMsrTurboRatioLimit ( + EFI_CPU_PM_STRUCT *ppm, + UINTN ProcessorNumber + ); + +VOID +ProgramMsrTemperatureTarget ( + EFI_CPU_PM_STRUCT *ppm, + UINTN ProcessorNumber + ); + +VOID +GetMsrTemperatureTarget ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramMsrMiscPwrMgmt ( + EFI_CPU_PM_STRUCT *ppm, + UINTN ProcessorNumber + ); + +VOID +Program_Bios_Reset_Cpl ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramB2PFastRaplDutyCycle ( + EFI_CPU_PM_STRUCT *ppm + ); + +UINT8 +EFIAPI +GetHwpmSupport ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +HWPMInterfaceReg ( + EFI_CPU_PM_STRUCT *ppm, + UINTN ProcessorNumber + ); + +VOID +EnableAutonomousCStateControl ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +EFIAPI +EnableHwpLvtThermalInterrupt( + EFI_CPU_PM_STRUCT *ppm, + UINTN ProcessorNumber + ); + +VOID +EFIAPI +EnableHwpFeatures( + EFI_CPU_PM_STRUCT *ppm, + UINTN ProcessorNumber + ); + +VOID +ProgramB2PPcuMiscConfig ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramB2PHWPMMiscConfig ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramMsrCLatency ( + EFI_CPU_PM_STRUCT *ppm, + UINTN ProcessorNumber + ); + +VOID +ProgramB2PDynamicL1 ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +PpmSetMsrCstConfigCtrlLockBit ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramB2PForceUncoreAndMeshRatio ( + EFI_CPU_PM_STRUCT *ppm + ); + +VOID +ProgramB2PMiscWorkaroundEnable ( + EFI_CPU_PM_STRUCT *ppm + ); + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/CsrToPcieAddress.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/CsrToPcieAddress.h new file mode 100644 index 0000000000..1eef535d91 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/CsrToPcieAddress.h @@ -0,0 +1,42 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __CSR_TO_PCIE_ADDRESS_H__ +#define __CSR_TO_PCIE_ADDRESS_H__ + + +#include + +////////////////////////////////////////////////////////////////////////// +// +// CSR to Pcie Address Library +// This Lib provide the way use platform Library instance +// +////////////////////////////////////////////////////////////////////////// + +/** + This Lib Convert the logical address (CSR type, e.g. CPU ID, Boxtype, Box instance etc.) into physical address + + @param[in] Global Global pointer + @param[in] Virtual Virtual address + @param[in] Address A pointer of the address of the USRA Address Structure + @param[out] AlignedAddress A pointer of aligned address converted from USRA address + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +UINTN +EFIAPI +CsrGetPcieAlignAddress ( + IN VOID *Global, + IN BOOLEAN Virtual, + IN USRA_ADDRESS *Address, + OUT UINTN *AlignedAddress + ); + + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/MmPciBaseLib.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/MmPciBaseLib.h new file mode 100644 index 0000000000..16205126a6 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/MmPciBaseLib.h @@ -0,0 +1,48 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _MM_PCIE_BASE_LIB_H_ +#define _MM_PCIE_BASE_LIB_H_ + +#include + +/** + This procedure will get PCIE address + + @param[in] Bus Pci Bus Number + @param[in] Device Pci Device Number + @param[in] Function Pci Function Number + + @retval PCIE address +**/ +UINTN +MmPciBase ( + IN UINT32 Bus, + IN UINT32 Device, + IN UINT32 Function +); + +/** + This procedure will get PCIE address + + @param[in] Seg Pcie Segment Number + @param[in] Bus Pcie Bus Number + @param[in] Device Pcie Device Number + @param[in] Function Pcie Function Number + + @retval PCIE address +**/ +UINTN +MmPciAddress( +IN UINT32 Seg, +IN UINT32 Bus, +IN UINT32 Device, +IN UINT32 Function, +IN UINT32 Register +); + +#endif // _MM_PCIE_BASE_LIB_H_ diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/PcieAddress.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/PcieAddress.h new file mode 100644 index 0000000000..ec5c364e0c --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/PcieAddress.h @@ -0,0 +1,80 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PCIE_MMCFG_H__ +#define __PCIE_MMCFG_H__ + +#include + + +////////////////////////////////////////////////////////////////////////// +// +// PCIE MMCFG Table definition +// This table was based on PCI Firmware Spec Rev 3.1 +// +////////////////////////////////////////////////////////////////////////// + +typedef struct + { + UINT8 Signature[4]; // "MCFG" Signature For this Table + UINT32 Length; // Length, in bytes, include base address allocation structures. + UINT8 Revision; // "1" + UINT8 SegMax; // The Maximum number of Segments + UINT16 ValidSegMap; // Valid Segment Bit Map, LSB Bit0 for Seg0, bit1 for seg1 ... + UINT8 Reserved[4]; // Reserved +} PCIE_MMCFG_HEADER_TYPE; + +typedef struct + { + UINT32 BaseAddressL; // Processor-relative Base Address (Lower 32-bit) for the Enhanced Configuration Access Mechanism + UINT32 BaseAddressH; // Processor-relative Base Address (Upper 32-bit) for the Enhanced Configuration Access Mechanism + UINT16 Segment; // PCI Segment Group Number. Default is 0. + UINT8 StartBus; // Start PCI Bus number decoded by the host bridge + UINT8 EndBus; // End PCI Bus number decoded by the host bridge + UINT8 Reserved[4]; // Reserved +} PCIE_MMCFG_BASE_ADDRESS_TYPE; + + +typedef struct + { + PCIE_MMCFG_HEADER_TYPE Header; // The header of MMCFG Table + PCIE_MMCFG_BASE_ADDRESS_TYPE MmcfgBase[1]; // First Array of base address allocation structures. +} PCIE_MMCFG_TABLE_TYPE; + + +/** + This Lib is used for platform to set platform specific Pcie MMCFG Table + + @param[in] MmcfgTable A pointer of the MMCFG Table structure for PCIE_MMCFG_TABLE_TYPE type + @param[in] NumOfSeg Number of Segments in the table + + @retval <>NULL The function completed successfully. + @retval NULL Return Error +**/ +UINTN +EFIAPI +SetPcieSegMmcfgTable ( + IN PCIE_MMCFG_TABLE_TYPE *MmcfgTable, + IN UINT32 NumOfSeg +); + +/** + This Lib return PCIE MMCFG Base Address + + @param[in] Address A pointer of the address of the USRA Address Structure for PCIE type + + @retval <>NULL The function completed successfully. + @retval NULL Return Error +**/ +UINTN +EFIAPI +GetPcieSegMmcfgBaseAddress ( + IN USRA_ADDRESS *Address + ); + + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/PciePlatformHookLib.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/PciePlatformHookLib.h new file mode 100644 index 0000000000..8ff5251627 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/PciePlatformHookLib.h @@ -0,0 +1,27 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PCIE_PLATFORM_HOOK_LIB_H__ +#define __PCIE_PLATFORM_HOOK_LIB_H__ + +typedef enum { + PcieInitStart, + BeforeBifurcation, + AfterBifurcation, + BeforePortInit, + AfterPortInit, + PcieInitEnd +} PCIE_HOOK_EVENT; + +EFI_STATUS +EFIAPI +PciePlatformHookEvent ( + IN PCIE_HOOK_EVENT Event, + IN VOID *Context + ); + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/UsraAccessApi.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/UsraAccessApi.h new file mode 100644 index 0000000000..148ca6c5b2 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Library/UsraAccessApi.h @@ -0,0 +1,85 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __USRA_ACCESS_API_H__ +#define __USRA_ACCESS_API_H__ + + +#include + +////////////////////////////////////////////////////////////////////////// +// +// USRA Silicon Access Library +// +////////////////////////////////////////////////////////////////////////// + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register read operations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + @param[in] Buffer A pointer of buffer for the value read from the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +EFIAPI +RegisterRead ( + IN USRA_ADDRESS *Address, + OUT VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register write operations. + It transfers data from a naturally aligned data buffer into a silicon register. + + @param[in] Address A pointer of the address of the USRA Address Structure to be written + @param[in] Buffer A pointer of buffer for the value write to the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +EFIAPI +RegisterWrite ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register AND then OR operations. It read data from a + register, And it with the AndBuffer, then Or it with the OrBuffer, and write the result back to the register + + @param[in] Address A pointer of the address of the silicon register to be written + @param[in] AndBuffer A pointer of buffer for the value used for AND operation + A NULL pointer means no AND operation. RegisterModify() equivalents to RegisterOr() + @param[in] OrBuffer A pointer of buffer for the value used for OR operation + A NULL pointer means no OR operation. RegisterModify() equivalents to RegisterAnd() + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +EFIAPI +RegisterModify ( + IN USRA_ADDRESS *Address, + IN VOID *AndBuffer, + IN VOID *OrBuffer + ); + +/** + This API get the flat address from the given USRA Address. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + + @retval The flat address +**/ +INTN +EFIAPI +GetRegisterAddress ( + IN USRA_ADDRESS *Address + ); + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/MaxSocket.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/MaxSocket.h new file mode 100644 index 0000000000..8552d20191 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/MaxSocket.h @@ -0,0 +1,19 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +// This defines the maximum number of sockets supported by some modules. +// It is generally better to use a dynamic solution. +// This is also defined by build tools for some special build +// environments used in validation that do not support EDK II build +// and thus can't use PCD. +// + +#ifndef MAX_SOCKET +#define MAX_SOCKET (FixedPcdGet32 (PcdMaxCpuSocketCount)) +#endif + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Ppi/SiliconRegAccess.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Ppi/SiliconRegAccess.h new file mode 100644 index 0000000000..9fc9b400c6 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Ppi/SiliconRegAccess.h @@ -0,0 +1,162 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SILICON_REG_ACCESS_PPI_H__ +#define __SILICON_REG_ACCESS_PPI_H__ + +#include + +extern EFI_GUID gUsraPpiGuid; + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register read operations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + @param[in] Buffer A pointer of buffer for the value read from the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +typedef +INTN +(EFIAPI *USRA_PPI_REG_READ)( + IN USRA_ADDRESS *Address, + OUT VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register write operations. + It transfers data from a naturally aligned data buffer into a silicon register. + + @param[in] Address A pointer of the address of the USRA Address Structure to be written + @param[in] Buffer A pointer of buffer for the value write to the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +typedef +INTN +(EFIAPI *USRA_PPI_REG_WRITE)( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register AND then OR operations. It read data from a + register, And it with the AndBuffer, then Or it with the OrBuffer, and write the result back to the register + + @param[in] Address A pointer of the address of the silicon register to be written + @param[in] AndBuffer A pointer of buffer for the value used for AND operation + A NULL pointer means no AND operation. RegisterModify() equivalents to RegisterOr() + @param[in] OrBuffer A pointer of buffer for the value used for OR operation + A NULL pointer means no OR operation. RegisterModify() equivalents to RegisterAnd() + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +typedef +INTN +(EFIAPI *USRA_PPI_REG_MODIFY)( + IN USRA_ADDRESS *Address, + IN VOID *AndBuffer, + IN VOID *OrBuffer + ); + +/** + This API get the flat address from the given USRA Address. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + + @retval The flat address +**/ +typedef +INTN +(EFIAPI *USRA_PPI_GET_ADDR)( + IN USRA_ADDRESS *Address + ); + +/// +/// This service abstracts the ability to read/write silicon register. +/// +typedef struct { + USRA_PPI_REG_READ RegRead; + USRA_PPI_REG_WRITE RegWrite; + + USRA_PPI_REG_MODIFY RegModify; + USRA_PPI_GET_ADDR GetRegAddr; +} USRA_PPI; + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register read operations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + @param[in] Buffer A pointer of buffer for the value read from the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +INTN +EFIAPI +PeiRegRead ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register write operations. + It transfers data from a naturally aligned data buffer into a silicon register. + + @param[in] Address A pointer of the address of the USRA Address Structure to be written + @param[in] Buffer A pointer of buffer for the value write to the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +INTN +EFIAPI +PeiRegWrite ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit Pcie silicon register AND then OR operations. It read data from a + register, And it with the AndBuffer, then Or it with the OrBuffer, and write the result back to the register + + @param[in] Address A pointer of the address of the silicon register to be written + @param[in] AndBuffer A pointer of buffer for the value used for AND operation + A NULL pointer means no AND operation. RegisterModify() equivalents to RegisterOr() + @param[in] OrBuffer A pointer of buffer for the value used for OR operation + A NULL pointer means no OR operation. RegisterModify() equivalents to RegisterAnd() + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +INTN +EFIAPI +PeiRegModify ( + IN USRA_ADDRESS *Address, + IN VOID *AndBuffer, + IN VOID *OrBuffer + ); + +/** + This API get the flat address from the given USRA Address. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + + @retval The flat address +**/ +INTN +EFIAPI +PeiGetRegAddr ( + IN USRA_ADDRESS *Address + ); + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Protocol/IioUds.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Protocol/IioUds.h new file mode 100644 index 0000000000..96913ebe31 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Protocol/IioUds.h @@ -0,0 +1,44 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _EFI_IIO_UDS_PROTOCOL_H_ +#define _EFI_IIO_UDS_PROTOCOL_H_ + +#include + +#define EFI_IIO_UDS_PROTOCOL_GUID \ + { 0xa7ced760, 0xc71c, 0x4e1a, 0xac, 0xb1, 0x89, 0x60, 0x4d, 0x52, 0x16, 0xcb } + +typedef struct _EFI_IIO_UDS_PROTOCOL EFI_IIO_UDS_PROTOCOL; + +typedef +EFI_STATUS +(EFIAPI *IIH_ENABLE_VC) ( + IN EFI_IIO_UDS_PROTOCOL *This, + IN UINT32 VcCtrlData + ); +/** + + Enables the requested VC in IIO + + @param This Pointer to the EFI_IOH_UDS_PROTOCOL instance. + @param VcCtrlData Data read from VC resourse control reg. + +**/ + + +typedef struct _EFI_IIO_UDS_PROTOCOL { + IIO_UDS *IioUdsPtr; + IIH_ENABLE_VC EnableVc; +} EFI_IIO_UDS_PROTOCOL; + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gEfiIioUdsProtocolGuid; + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Protocol/PciCallback.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Protocol/PciCallback.h new file mode 100644 index 0000000000..7da7fa3c77 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Protocol/PciCallback.h @@ -0,0 +1,84 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _EFI_PCI_CALLBACK_H +#define _EFI_PCI_CALLBACK_H + +#include +#include +#include + + +// +// Global Id for PCI callback +// +#define EFI_PCI_CALLBACK_PROTOCOL_GUID \ + { \ + 0x1ca0e202, 0xfe9e, 0x4776, 0x9f, 0xaa, 0x57, 0xc, 0x19, 0x61, 0x7a, 0x06 \ + } + +typedef struct _EFI_PCI_CALLBACK_PROTOCOL EFI_PCI_CALLBACK_PROTOCOL; + +typedef enum { + EfiPciEnumerationDeviceScanning = 1, + EfiPciEnumerationBusNumberAssigned = 2, + EfiPciEnumerationResourceAssigned = 4, +} EFI_PCI_ENUMERATION_PHASE; + +typedef struct { + PCI_TYPE00 PciHeader; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo; + EFI_CPU_IO2_PROTOCOL *CpuIo; +} EFI_PCI_CALLBACK_CONTEXT; + +typedef +VOID +(EFIAPI *EFI_PCI_CALLBACK_FUNC) ( + IN EFI_HANDLE RootBridgeHandle, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, + IN EFI_PCI_ENUMERATION_PHASE Phase, + IN EFI_PCI_CALLBACK_CONTEXT *Context +); + +typedef +EFI_STATUS +(EFIAPI *EFI_REGISTER_PCI_CALLBACK) ( + IN EFI_PCI_CALLBACK_PROTOCOL *This, + IN EFI_PCI_CALLBACK_FUNC Function, + IN EFI_PCI_ENUMERATION_PHASE Phase +) +/*++ + +Routine Description: + + Register a callback during PCI bus enumeration + +Arguments: + + This - Protocol instance pointer. + Function - Callback function pointer. + Phase - PCI enumeration phase. + +Returns: + + EFI_SUCCESS - Function has registed successfully + EFI_UNSUPPORTED - The function has been regisered + EFI_InVALID_PARAMETER - The parameter is incorrect + +--*/ +; + +// +// Protocol definition +// +typedef struct _EFI_PCI_CALLBACK_PROTOCOL { + EFI_REGISTER_PCI_CALLBACK RegisterPciCallback; +} EFI_PCI_CALLBACK_PROTOCOL; + +extern EFI_GUID gEfiPciCallbackProtocolGuid; + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Protocol/SiliconRegAccess.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Protocol/SiliconRegAccess.h new file mode 100644 index 0000000000..425f44e9c7 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/Protocol/SiliconRegAccess.h @@ -0,0 +1,227 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SILICON_REG_ACCESS_PROTOCOL_H__ +#define __SILICON_REG_ACCESS_PROTOCOL_H__ + +#include + +extern EFI_GUID gUsraProtocolGuid; + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register read operations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + @param[in] Buffer A pointer of buffer for the value read from the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +typedef +INTN +(EFIAPI *USRA_PROTOCOL_REG_READ)( + IN USRA_ADDRESS *Address, + OUT VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register write operations. + It transfers data from a naturally aligned data buffer into a silicon register. + + @param[in] Address A pointer of the address of the USRA Address Structure to be written + @param[in] Buffer A pointer of buffer for the value write to the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +typedef +INTN +(EFIAPI *USRA_PROTOCOL_REG_WRITE)( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register write operations. + It transfers data from a naturally aligned data buffer into a silicon register. + + @param[in] Address A pointer of the address of the USRA Address Structure to be written + @param[in] Buffer A pointer of buffer for the value write to the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +typedef +INTN +(EFIAPI *USRA_PROTOCOL_REG_MODIFY)( + IN USRA_ADDRESS *Address, + IN VOID *AndBuffer, + IN VOID *OrBuffer + ); + +/** + This API get the flat address from the given USRA Address. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + + @retval The flat address +**/ +typedef +INTN +(EFIAPI *USRA_PROTOCOL_GET_ADDR)( + IN USRA_ADDRESS *Address + ); + +/// +/// This service abstracts the ability to read/write silicon register. +/// +typedef struct { + USRA_PROTOCOL_REG_READ RegRead; + USRA_PROTOCOL_REG_WRITE RegWrite; + USRA_PROTOCOL_REG_MODIFY RegModify; + USRA_PROTOCOL_GET_ADDR GetRegAddr; +} USRA_PROTOCOL; + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register read operations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + @param[in] Buffer A pointer of buffer for the value read from the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +INTN +EFIAPI +DxeRegRead ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register write operations. + It transfers data from a naturally aligned data buffer into a silicon register. + + @param[in] Address A pointer of the address of the USRA Address Structure to be written + @param[in] Buffer A pointer of buffer for the value write to the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +INTN +EFIAPI +DxeRegWrite ( + IN USRA_ADDRESS *Address, + OUT VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register AND then OR operations. It read data from a + register, And it with the AndBuffer, then Or it with the OrBuffer, and write the result back to the register + + @param[in] Address A pointer of the address of the silicon register to be written + @param[in] AndBuffer A pointer of buffer for the value used for AND operation + A NULL pointer means no AND operation. RegisterModify() equivalents to RegisterOr() + @param[in] OrBuffer A pointer of buffer for the value used for OR operation + A NULL pointer means no OR operation. RegisterModify() equivalents to RegisterAnd() + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +INTN +EFIAPI +DxeRegModify ( + IN USRA_ADDRESS *Address, + IN VOID *AndBuffer, + IN VOID *OrBuffer + ); + +/** + This API get the flat address from the given USRA Address. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + + @retval The flat address +**/ +INTN +EFIAPI +DxeGetRegAddr ( + IN USRA_ADDRESS *Address + ); + + /** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register read operations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + @param[in] Buffer A pointer of buffer for the value read from the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +INTN +EFIAPI +SmmRegRead ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register write operations. + It transfers data from a naturally aligned data buffer into a silicon register. + + @param[in] Address A pointer of the address of the USRA Address Structure to be written + @param[in] Buffer A pointer of buffer for the value write to the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +INTN +EFIAPI +SmmRegWrite ( + IN USRA_ADDRESS *Address, + OUT VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register AND then OR operations. It read data from a + register, And it with the AndBuffer, then Or it with the OrBuffer, and write the result back to the register + + @param[in] Address A pointer of the address of the silicon register to be written + @param[in] AndBuffer A pointer of buffer for the value used for AND operation + A NULL pointer means no AND operation. RegisterModify() equivalents to RegisterOr() + @param[in] OrBuffer A pointer of buffer for the value used for OR operation + A NULL pointer means no OR operation. RegisterModify() equivalents to RegisterAnd() + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +INTN +EFIAPI +SmmRegModify ( + IN USRA_ADDRESS *Address, + IN VOID *AndBuffer, + IN VOID *OrBuffer + ); + +/** + This API get the flat address from the given USRA Address. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + + @retval The flat address +**/ +INTN +EFIAPI +SmmGetRegAddr ( + IN USRA_ADDRESS *Address + ); + + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/SocketConfiguration.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/SocketConfiguration.h new file mode 100644 index 0000000000..ea1f5e3827 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/SocketConfiguration.h @@ -0,0 +1,514 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SOCKET_CONFIGURATION_H__ +#define __SOCKET_CONFIGURATION_H__ + +#define SOCKET_CONFIG_CLASS_ID 44 +#define SOCKET_CONFIG_SUBCLASS_ID 0x00 + +#define VFR_BLANK_LINE subtitle text = STRING_TOKEN(STR_NULL_STRING); +#define VFR_END_FORM endform; +#define VFR_END_FORMSET endformset; +#define VFR_HORIZ_LINE subtitle text = STRING_TOKEN(STR_HORIZONTAL_LINE); + + + +#define SOCKET_IIO_CONFIG_KEY 0xFAFB +#define SOCKET_COMMONRC_CONFIG_KEY 0xFAFA +#define SOCKET_MP_LINK_CONFIG_KEY 0xFAF9 +#define SOCKET_MEMORY_CONFIG_KEY 0xFAF8 +#define SOCKET_MISC_CONFIG_KEY 0xFAF7 +#define SOCKET_CONFIG_KEY 0xF00A +#define SOCKET_POWERMANAGEMENT_CONFIGURATION_KEY 0xF00B +#define SOCKET_PROCESSORCORE_CONFIGURATION_KEY 0xF00C + + + +#define KEY_XMP_PROFILE 0x1DC0 +#define KEY_XMP_PROFILE1 0x1DC1 +#define KEY_CPU_ONLINE 0x10B8 + +// {26A69232-ABF8-4597-8876-A7DC0A7CA602} +#define SOCKET_CONFIG_SETUP_GUID {0x26a69232, 0xabf8, 0x4597, 0x88, 0x76, 0xa7, 0xdc, 0xa, 0x7c, 0xa6, 0x2} + + + +#define VFR_FORMID_SOCKET 0x510 +#define VFR_FORMID_COMMONRC 0x511 +#define VFR_FORMID_KTI 0x512 +#define VFR_FORMID_PROCESSOR 0x513 +#define VFR_FORMID_KTI_STATUS 0x514 + +#define VFR_FORMID_SOCKET_IIO_CONFIGURATION 0x517 + +#define VFR_FORMID_IIO 0x518 +#define VFR_FORMID_IIO2 0x519 +#define VFR_FORMID_IIO3 0x51A +#define VFR_FORMID_IIO4 0x51B +#define VFR_FORMID_PWRMGT 0x51C + +// +// KTI Form for SV +// + +#define VFR_FORMID_KTI_GENERAL 0x521 +#define VFR_FORMID_KTISYSTEMWIDE 0x522 +#define VFR_FORMID_KTISYSTEM_PHY_LINK 0x523 +#define VFR_FORMID_KTISYSTEM_OSB 0x524 +#define VFR_FORMID_KTIPERSOCKET 0x525 +#define VFR_FID_KTI_CPU0 0x526 +#define VFR_FID_KTI_CPU1 0x527 +#define VFR_FID_KTI_CPU2 0x528 +#define VFR_FID_KTI_CPU3 0x529 +#define VFR_FID_KTI_CPU4 0x52A +#define VFR_FID_KTI_CPU5 0x52B +#define VFR_FID_KTI_CPU6 0x52C +#define VFR_FID_KTI_CPU7 0x52D +// +// KTI Form IDs +// +#define VFR_FORMID_CPU_KTII 0x530 +#define VFR_FID_KTI_STATUS 0x531 +#define VFR_FID_KTI_TOPOLOGY 0x532 +#define VFR_FID_KTI_TOPOLOGY_MATRIX 0x533 +#define VFR_FID_IIO_DEV_HIDE 0x534 +#define VFR_FID_KTI_SOCKET_RES 0x535 +#define VFR_FID_KTI_SOCKET_RES_REQUEST 0x536 +#define VFR_FID_KTI_SOCKET_RES_STATUS 0x537 +#define VFR_FORMID_MEMORY 0x540 +#define VFR_FORMID_MEMORY_RAS 0x541 +#define VFR_FID_KTI_CPU0_LINK0 0x542 +#define VFR_FID_KTI_CPU0_LINK1 0x543 +#define VFR_FID_KTI_CPU0_LINK2 0x544 +#define VFR_FID_KTI_CPU1_LINK0 0x545 +#define VFR_FID_KTI_CPU1_LINK1 0x546 +#define VFR_FID_KTI_CPU1_LINK2 0x547 +#define VFR_FID_KTI_CPU2_LINK0 0x548 +#define VFR_FID_KTI_CPU2_LINK1 0x549 +#define VFR_FID_KTI_CPU2_LINK2 0x54A +#define VFR_FID_KTI_CPU3_LINK0 0x54B +#define VFR_FID_KTI_CPU3_LINK1 0x54C +#define VFR_FID_KTI_CPU3_LINK2 0x54D +#define VFR_FID_KTI_CPU4_LINK0 0x54E +#define VFR_FID_KTI_CPU4_LINK1 0x54F +#define VFR_FORMID_BRANCH_RANK_CONFIG 0x571 +#define VFR_FORMID_VALHOOKS_CONFIG 0x572 +#define VFR_FORMID_THERMTHRT_CONFIG 0x573 +#define VFR_FORMID_MEMTOPOLOGY_DISPLAY 0x574 +#define VFR_FORMID_PAGE_POLICY_DISPLAY 0x57D +#define VFR_FORMID_MEMORY_TRAINING_DISPLAY 0x57E +#define VFR_FORMID_MEM_PWR_SAVE_ADV_ID 0x57F +#define VFR_FORMID_CKE_DISPLAY 0x59F +#define VFR_FORMID_SREF_DISPLAY 0x5A0 +#define VFR_FORMID_MEM_THERMAL_ID 0x580 +#define VFR_FORMID_XMP_DISPLAY 0x581 +#define VFR_FORMID_MEM_PM_CFG_ID 0x582 +#define VFR_FORMID_MEM_MAP 0x58A +#define VFR_FORMID_RAPL 0x58B +#define VFR_FORMID_SECURE_ERASE 0x58E + +#define VFR_FID_KTI_CPU4_LINK2 0x590 +#define VFR_FID_KTI_CPU5_LINK0 0x591 +#define VFR_FID_KTI_CPU5_LINK1 0x592 +#define VFR_FID_KTI_CPU5_LINK2 0x593 +#define VFR_FID_KTI_CPU6_LINK0 0x594 +#define VFR_FID_KTI_CPU6_LINK1 0x595 +#define VFR_FID_KTI_CPU6_LINK2 0x596 +#define VFR_FID_KTI_CPU7_LINK0 0x597 +#define VFR_FID_KTI_CPU7_LINK1 0x598 +#define VFR_FID_KTI_CPU7_LINK2 0x599 + +#define VFR_FID_KTI_WARNING_LOG 0x59E + + +// +// MEMORY Form IDs +// + + + + +// +// IIO Form IDs +// +#define VFR_FORMID_IIO_CONFIG 0x450 +#define VFR_FORMID_VTD 0x451 +#define VFR_FORMID_PCIE 0x452 +#define VFR_FORMID_PCIE_IIO0P0 0x453 +#define VFR_FORMID_PCIE_IIO0P1 0x454 +#define VFR_FORMID_PCIE_IIO0P2 0x455 +#define VFR_FORMID_PCIE_IIO0P3 0x456 +#define VFR_FORMID_PCIE_IIO0P4 0x457 +#define VFR_FORMID_PCIE_IIO0P5 0x458 +#define VFR_FORMID_PCIE_IIO0P6 0x459 +#define VFR_FORMID_PCIE_IIO0P7 0x45A +#define VFR_FORMID_PCIE_IIO0P8 0x45B +#define VFR_FORMID_PCIE_IIO0P9 0x45C +#define VFR_FORMID_PCIE_IIO0P10 0x45D +#define VFR_FORMID_PCIE_IIO0P11 0x45E +#define VFR_FORMID_PCIE_IIO0P12 0x45F +#define VFR_FORMID_PCIE_IIO0P13 0x460 +#define VFR_FORMID_PCIE_IIO0P14 0x461 +#define VFR_FORMID_PCIE_IIO0P15 0x488 +#define VFR_FORMID_PCIE_IIO0P16 0x489 +#define VFR_FORMID_PCIE_IIO0P17 0x48A +#define VFR_FORMID_PCIE_IIO0P18 0x48B +#define VFR_FORMID_PCIE_IIO0P19 0x48C +#define VFR_FORMID_PCIE_IIO0P20 0x48D + +#define VFR_FORMID_PCIE_IIO1P0 0x462 +#define VFR_FORMID_PCIE_IIO1P1 0x463 +#define VFR_FORMID_PCIE_IIO1P2 0x469 +#define VFR_FORMID_PCIE_IIO1P3 0x46A +#define VFR_FORMID_PCIE_IIO1P4 0x46B +#define VFR_FORMID_PCIE_IIO1P5 0x46C +#define VFR_FORMID_PCIE_IIO1P6 0x46D +#define VFR_FORMID_PCIE_IIO1P7 0x46E +#define VFR_FORMID_PCIE_IIO1P8 0x46F +#define VFR_FORMID_PCIE_IIO1P9 0x470 +#define VFR_FORMID_PCIE_IIO1P10 0x475 +#define VFR_FORMID_PCIE_IIO1P11 0x476 +#define VFR_FORMID_PCIE_IIO1P12 0x477 +#define VFR_FORMID_PCIE_IIO1P13 0x478 +#define VFR_FORMID_PCIE_IIO1P14 0x479 +#define VFR_FORMID_PCIE_IIO1P15 0x48E +#define VFR_FORMID_PCIE_IIO1P16 0x48F +#define VFR_FORMID_PCIE_IIO1P17 0x490 +#define VFR_FORMID_PCIE_IIO1P18 0x491 +#define VFR_FORMID_PCIE_IIO1P19 0x492 +#define VFR_FORMID_PCIE_IIO1P20 0x493 + +#define VFR_FORMID_IIO0 0x47A +#define VFR_FORMID_IIO1 0x47B +#define VFR_FORMID_IOAT_CONFIG 0x47C +#define VFR_FORMID_IIO0IOAT 0x47D +#define VFR_FORMID_IIO1IOAT 0x47E +#define VFR_FORMID_IIO2IOAT 0x47F +#define VFR_FORMID_IIO3IOAT 0x480 +#define VFR_FORMID_IIO_PCIE_SLOT 0x487 +// +// extended IIO form IDs for 4S +// +#define VFR_FORMID_PCIE_IIO2P0 0x0690 +#define VFR_FORMID_PCIE_IIO2P1 0x0691 +#define VFR_FORMID_PCIE_IIO2P2 0x0692 +#define VFR_FORMID_PCIE_IIO2P3 0x0693 +#define VFR_FORMID_PCIE_IIO2P4 0x0694 +#define VFR_FORMID_PCIE_IIO2P5 0x0695 +#define VFR_FORMID_PCIE_IIO2P6 0x0696 +#define VFR_FORMID_PCIE_IIO2P7 0x0697 +#define VFR_FORMID_PCIE_IIO2P8 0x0698 +#define VFR_FORMID_PCIE_IIO2P9 0x0699 +#define VFR_FORMID_PCIE_IIO2P10 0x069A +#define VFR_FORMID_PCIE_IIO2P11 0x069B +#define VFR_FORMID_PCIE_IIO2P12 0x069C +#define VFR_FORMID_PCIE_IIO2P13 0x069D +#define VFR_FORMID_PCIE_IIO2P14 0x069E +#define VFR_FORMID_PCIE_IIO2P15 0x06AA +#define VFR_FORMID_PCIE_IIO2P16 0x06AB +#define VFR_FORMID_PCIE_IIO2P17 0x06AC +#define VFR_FORMID_PCIE_IIO2P18 0x06AD +#define VFR_FORMID_PCIE_IIO2P19 0x06AE +#define VFR_FORMID_PCIE_IIO2P20 0x06AF + +#define VFR_FORMID_PCIE_IIO3P0 0x069F +#define VFR_FORMID_PCIE_IIO3P1 0x0670 +#define VFR_FORMID_PCIE_IIO3P2 0x0671 +#define VFR_FORMID_PCIE_IIO3P3 0x0672 +#define VFR_FORMID_PCIE_IIO3P4 0x0673 +#define VFR_FORMID_PCIE_IIO3P5 0x06A0 +#define VFR_FORMID_PCIE_IIO3P6 0x06A1 +#define VFR_FORMID_PCIE_IIO3P7 0x06A2 +#define VFR_FORMID_PCIE_IIO3P8 0x06A3 +#define VFR_FORMID_PCIE_IIO3P9 0x06A4 +#define VFR_FORMID_PCIE_IIO3P10 0x06A5 +#define VFR_FORMID_PCIE_IIO3P11 0x06A6 +#define VFR_FORMID_PCIE_IIO3P12 0x06A7 +#define VFR_FORMID_PCIE_IIO3P13 0x06A8 +#define VFR_FORMID_PCIE_IIO3P14 0x06A9 +#define VFR_FORMID_PCIE_IIO3P15 0x06B0 +#define VFR_FORMID_PCIE_IIO3P16 0x06B1 +#define VFR_FORMID_PCIE_IIO3P17 0x06B2 +#define VFR_FORMID_PCIE_IIO3P18 0x06B3 +#define VFR_FORMID_PCIE_IIO3P19 0x06B4 +#define VFR_FORMID_PCIE_IIO3P20 0x06B5 + +#define VFR_FORMID_VMD 0x06C0 +#define VFR_FORMID_VMD_IIO0 0x06C1 +#define VFR_FORMID_VMD_IIO1 0x06C2 +#define VFR_FORMID_VMD_IIO2 0x06C3 +#define VFR_FORMID_VMD_IIO3 0x06C4 +#define VFR_FORMID_IIO_RTO_CONFIG 0x06C5 +#define VFR_FORMID_IIO_RTO_SKT0SVDEVHIDE 0x06C6 +#define VFR_FORMID_IIO_RTO_SKT1SVDEVHIDE 0x06C7 +#define VFR_FORMID_IIO_RTO_SKT2SVDEVHIDE 0x06C8 +#define VFR_FORMID_IIO_RTO_SKT3SVDEVHIDE 0x06C9 + +#define VFR_FORMID_RTO_PCIE_IIO0P0 0x06CA +#define VFR_FORMID_RTO_PCIE_IIO0P1 0x06CB +#define VFR_FORMID_RTO_PCIE_IIO0P2 0x06CD +#define VFR_FORMID_RTO_PCIE_IIO0P3 0x06CE +#define VFR_FORMID_RTO_PCIE_IIO0P4 0x06CF +#define VFR_FORMID_RTO_PCIE_IIO0P5 0x06D0 +#define VFR_FORMID_RTO_PCIE_IIO0P6 0x06D1 +#define VFR_FORMID_RTO_PCIE_IIO0P7 0x06D2 +#define VFR_FORMID_RTO_PCIE_IIO0P8 0x06D3 +#define VFR_FORMID_RTO_PCIE_IIO0P9 0x06D4 +#define VFR_FORMID_RTO_PCIE_IIO0P10 0x06D5 +#define VFR_FORMID_RTO_PCIE_IIO0P11 0x06D6 +#define VFR_FORMID_RTO_PCIE_IIO0P12 0x06D7 +#define VFR_FORMID_RTO_PCIE_IIO0P13 0x06D8 +#define VFR_FORMID_RTO_PCIE_IIO0P14 0x06D9 +#define VFR_FORMID_RTO_PCIE_IIO0P15 0x06DA +#define VFR_FORMID_RTO_PCIE_IIO0P16 0x06DB +#define VFR_FORMID_RTO_PCIE_IIO0P17 0x06DC +#define VFR_FORMID_RTO_PCIE_IIO0P18 0x06DD +#define VFR_FORMID_RTO_PCIE_IIO0P19 0x06DE +#define VFR_FORMID_RTO_PCIE_IIO0P20 0x06DF + +#define VFR_FORMID_RTO_PCIE_IIO1P0 0x06E0 +#define VFR_FORMID_RTO_PCIE_IIO1P1 0x06E1 +#define VFR_FORMID_RTO_PCIE_IIO1P2 0x06E2 +#define VFR_FORMID_RTO_PCIE_IIO1P3 0x06E3 +#define VFR_FORMID_RTO_PCIE_IIO1P4 0x06E4 +#define VFR_FORMID_RTO_PCIE_IIO1P5 0x06E5 +#define VFR_FORMID_RTO_PCIE_IIO1P6 0x06E6 +#define VFR_FORMID_RTO_PCIE_IIO1P7 0x06E7 +#define VFR_FORMID_RTO_PCIE_IIO1P8 0x06E8 +#define VFR_FORMID_RTO_PCIE_IIO1P9 0x06E9 +#define VFR_FORMID_RTO_PCIE_IIO1P10 0x06EA +#define VFR_FORMID_RTO_PCIE_IIO1P11 0x06EB +#define VFR_FORMID_RTO_PCIE_IIO1P12 0x06EC +#define VFR_FORMID_RTO_PCIE_IIO1P13 0x06ED +#define VFR_FORMID_RTO_PCIE_IIO1P14 0x06EE +#define VFR_FORMID_RTO_PCIE_IIO1P15 0x06EF +#define VFR_FORMID_RTO_PCIE_IIO1P16 0x06F0 +#define VFR_FORMID_RTO_PCIE_IIO1P17 0x06F1 +#define VFR_FORMID_RTO_PCIE_IIO1P18 0x06F2 +#define VFR_FORMID_RTO_PCIE_IIO1P19 0x06F3 +#define VFR_FORMID_RTO_PCIE_IIO1P20 0x06F4 +#define VFR_FORMID_RTO_PCIE_IIO2P0 0x06F5 +#define VFR_FORMID_RTO_PCIE_IIO2P1 0x06F6 +#define VFR_FORMID_RTO_PCIE_IIO2P2 0x06F7 +#define VFR_FORMID_RTO_PCIE_IIO2P3 0x06F8 +#define VFR_FORMID_RTO_PCIE_IIO2P4 0x06F9 +#define VFR_FORMID_RTO_PCIE_IIO2P5 0x06FA +#define VFR_FORMID_RTO_PCIE_IIO2P6 0x06FB +#define VFR_FORMID_RTO_PCIE_IIO2P7 0x06FC +#define VFR_FORMID_RTO_PCIE_IIO2P8 0x06FD +#define VFR_FORMID_RTO_PCIE_IIO2P9 0x06FE +#define VFR_FORMID_RTO_PCIE_IIO2P10 0x06FF +#define VFR_FORMID_RTO_PCIE_IIO2P11 0x0700 +#define VFR_FORMID_RTO_PCIE_IIO2P12 0x0701 +#define VFR_FORMID_RTO_PCIE_IIO2P13 0x0702 +#define VFR_FORMID_RTO_PCIE_IIO2P14 0x0703 +#define VFR_FORMID_RTO_PCIE_IIO2P15 0x0704 +#define VFR_FORMID_RTO_PCIE_IIO2P16 0x0705 +#define VFR_FORMID_RTO_PCIE_IIO2P17 0x0706 +#define VFR_FORMID_RTO_PCIE_IIO2P18 0x0707 +#define VFR_FORMID_RTO_PCIE_IIO2P19 0x0708 +#define VFR_FORMID_RTO_PCIE_IIO2P20 0x0709 + +#define VFR_FORMID_RTO_PCIE_IIO3P0 0x070A +#define VFR_FORMID_RTO_PCIE_IIO3P1 0x070B +#define VFR_FORMID_RTO_PCIE_IIO3P2 0x070C +#define VFR_FORMID_RTO_PCIE_IIO3P3 0x070D +#define VFR_FORMID_RTO_PCIE_IIO3P4 0x070E +#define VFR_FORMID_RTO_PCIE_IIO3P5 0x070F +#define VFR_FORMID_RTO_PCIE_IIO3P6 0x0710 +#define VFR_FORMID_RTO_PCIE_IIO3P7 0x0711 +#define VFR_FORMID_RTO_PCIE_IIO3P8 0x0712 +#define VFR_FORMID_RTO_PCIE_IIO3P9 0x0713 +#define VFR_FORMID_RTO_PCIE_IIO3P10 0x0714 +#define VFR_FORMID_RTO_PCIE_IIO3P11 0x0715 +#define VFR_FORMID_RTO_PCIE_IIO3P12 0x0716 +#define VFR_FORMID_RTO_PCIE_IIO3P13 0x0717 +#define VFR_FORMID_RTO_PCIE_IIO3P14 0x0718 +#define VFR_FORMID_RTO_PCIE_IIO3P15 0x0719 +#define VFR_FORMID_RTO_PCIE_IIO3P16 0x071A +#define VFR_FORMID_RTO_PCIE_IIO3P17 0x071B +#define VFR_FORMID_RTO_PCIE_IIO3P18 0x071C +#define VFR_FORMID_RTO_PCIE_IIO3P19 0x071D +#define VFR_FORMID_RTO_PCIE_IIO3P20 0x071E + +#define VFR_FORMID_RTO_IIO0 0x071F +#define VFR_FORMID_RTO_IIO1 0x0720 +#define VFR_FORMID_RTO_IIO2 0x0721 +#define VFR_FORMID_RTO_IIO3 0x0722 + +#define VFR_FORMID_PCIEAIC 0x0723 +#define VFR_FORMID_PCIEAIC_IIO0 0x0724 +#define VFR_FORMID_PCIEAIC_IIO1 0x0725 +#define VFR_FORMID_PCIEAIC_IIO2 0x0726 +#define VFR_FORMID_PCIEAIC_IIO3 0x0727 + +#define VFR_FORMLABLE_SOCKET_TOP 0x4062 +#define VFR_FORMLABLE_SOCKET_BOTTOM 0x4063 + +// +// Defines used for variables to be range checked before consumption. +// +#define MAX_CAS_LATENCY 32 +#define MAX_TRP_LATENCY 32 +#define MAX_TRCD_LATENCY 32 +#define MAX_TRRD_LATENCY 255 +#define MAX_TWTR_LATENCY 255 +#define MAX_TRAS_LATENCY 63 +#define MAX_TRTP_LATENCY 255 +#define MAX_TWR_LATENCY 50 +#define MAX_TFAW_LATENCY 63 +#define MAX_TCWL_LATENCY 31 +#define MAX_TRC_LATENCY 255 +#define MAX_REFRESH_RATE 32767 +#define MAX_TRFC_LATENCY 1023 +#define MAX_MC_BGF_THRESHOLD 15 + + +//Per Socket forms for active core count and IOT options +#define VFR_FORMID_PER_SOCKET 0x300 +#define VFR_FORMID_CPU_SOCKET0 0x301 +#define VFR_FORMID_CPU_SOCKET1 0x302 +#define VFR_FORMID_CPU_SOCKET2 0x303 +#define VFR_FORMID_CPU_SOCKET3 0x304 +#define VFR_FORMID_CPU_SOCKET4 0x305 +#define VFR_FORMID_CPU_SOCKET5 0x306 +#define VFR_FORMID_CPU_SOCKET6 0x307 +#define VFR_FORMID_CPU_SOCKET7 0x308 +#define VFR_FORMID_IIO_ERR 0x309 + +#define SOCKET0_CPUPWRADVPMCFG_FORMID 0x310 +#define SOCKET1_CPUPWRADVPMCFG_FORMID 0x311 +#define SOCKET2_CPUPWRADVPMCFG_FORMID 0x312 +#define SOCKET3_CPUPWRADVPMCFG_FORMID 0x313 +#define SOCKET4_CPUPWRADVPMCFG_FORMID 0x314 +#define SOCKET5_CPUPWRADVPMCFG_FORMID 0x315 +#define SOCKET6_CPUPWRADVPMCFG_FORMID 0x316 +#define SOCKET7_CPUPWRADVPMCFG_FORMID 0x317 + +//P State Control Form +#define P_STATE_CONTROL_FORMID 0x380 +#define XE_RATIO_LIMIT_FORMID 0x381 +#define VID_OPTIONS_FORM_ID 0x382 + +//HWPM control Form +#define HWPM_STATE_CONTROL_FORMID 0x385 + +//C State Control Form +#define CPU0_CSTATE_CONTROL_FORM_ID 0x390 +#define HLV_SASV_FORM_ID 0x391 + +//T State Control Form +#define CPU_TSTATE_CONTROL_FORM_ID 0x392 + +//CPU Theraml Management +#define CPU_THERMMAL_MANAGE_FORM_ID 0x393 + +//Package C State Control +#define PACKAGE_CSTATE_CONTROL_FORM_ID 0x394 + +//DST 2.0 +#define CPU_THERMAL_DTS_2_0_FORM_ID 0x395 + +//Advacned PM Tuning Form +#define CPU_POWER_ADVANCED_CONFIG_FORM_ID 0x3A0 +#define ENERGY_PERF_BIAS_FORM_ID 0x3A1 +//#define PROG_POWERCTL_MSR_FORM_ID 0x3A2 +#define PROG_MSR_PP_CURT_CFG_CTRL_FORM_ID 0x3A3 +#define PROG_MSR_PP_CURT_PSI_CONFIG_FORM_ID 0x3A4 +#define PROG_ENTRY_CRITERIA_FORM_ID 0x3A5 +#define PROG_CSR_SWLTROVRD_FORM_ID 0x3A6 +#define PROG_CSR_DYNAMIC_PERF_POWER_CTL_FORM_ID 0x3A7 +#define PROG_CSR_SAPMCTL_FORM_ID 0x3A8 +#define PROG_CSR_PERF_P_LIMIT_FORM_ID 0x3A9 + +#define DRAM_RAPL_FORMID 0x3B0 +#define SOCKET_RAPL_FORMID 0x3C0 + +#define ACPI_S_STATE_FORMID 0x3D0 + +#define PROG_CSR_PMAX_CONFIG_FORM_ID 0x3E0 + +#define SOCKET0_PKGCENTRY_FORMID 0x3F0 +#define SOCKET1_PKGCENTRY_FORMID 0x3F1 +#define SOCKET2_PKGCENTRY_FORMID 0x3F2 +#define SOCKET3_PKGCENTRY_FORMID 0x3F3 +#define SOCKET4_PKGCENTRY_FORMID 0x3F4 +#define SOCKET5_PKGCENTRY_FORMID 0x3F5 +#define SOCKET6_PKGCENTRY_FORMID 0x3F6 +#define SOCKET7_PKGCENTRY_FORMID 0x3F7 + +#define SOCKET0_PKGCSAPM_FORMID 0x3F8 +#define SOCKET1_PKGCSAPM_FORMID 0x3F9 +#define SOCKET2_PKGCSAPM_FORMID 0x3FA +#define SOCKET3_PKGCSAPM_FORMID 0x3FB +#define SOCKET4_PKGCSAPM_FORMID 0x3FC +#define SOCKET5_PKGCSAPM_FORMID 0x3FD +#define SOCKET6_PKGCSAPM_FORMID 0x3FE +#define SOCKET7_PKGCSAPM_FORMID 0x3FF + +#define SOCKET0_PMAX_CONFIG_FORMID 0x400 +#define SOCKET1_PMAX_CONFIG_FORMID 0x401 +#define SOCKET2_PMAX_CONFIG_FORMID 0x402 +#define SOCKET3_PMAX_CONFIG_FORMID 0x403 +#define SOCKET4_PMAX_CONFIG_FORMID 0x404 +#define SOCKET5_PMAX_CONFIG_FORMID 0x405 +#define SOCKET6_PMAX_CONFIG_FORMID 0x406 +#define SOCKET7_PMAX_CONFIG_FORMID 0x407 + +// {516D5A04-C0D5-4657-B908-E4FB1D935EF0} +#define SOCKET_FORMSET_GUID \ + { \ + 0x516d5a04, 0xc0d5, 0x4657, 0xb9, 0x8, 0xe4, 0xfb, 0x1d, 0x93, 0x5e, 0xf0 \ + } + +// {DD84017E-7F52-48F9-B16E-50ED9E0DBE27} +#define SOCKET_IIO_CONFIG_GUID \ + { \ + 0xdd84017e, 0x7f52, 0x48f9, 0xb1, 0x6e, 0x50, 0xed, 0x9e, 0xd, 0xbe, 0x27 \ + } + +// {4402CA38-808F-4279-BCEC-5BAF8D59092F} +#define SOCKET_COMMONRC_CONFIG_GUID \ + { \ + 0x4402ca38, 0x808f, 0x4279, 0xbc, 0xec, 0x5b, 0xaf, 0x8d, 0x59, 0x09, 0x2f \ + } + +// {2B9B22DE-2AD4-4ABC-957D-5F18C504A05C} +#define SOCKET_MP_LINK_CONFIG_GUID \ + { \ + 0x2b9b22de, 0x2ad4, 0x4abc, 0x95, 0x7d, 0x5f, 0x18, 0xc5, 0x04, 0xa0, 0x5c \ + } + +// {CA3FF937-D646-4936-90E8-1B950649B389} +#define SOCKET_PCI_RESOURCE_CONFIG_DATA_GUID \ + { \ + 0xca3ff937, 0xd646, 0x4936, 0x90, 0xe8, 0x1b, 0x95, 0x06, 0x49, 0xb3, 0x89 \ + } + +// {98CF19ED-4109-4681-B79D-9196757C7824} +#define SOCKET_MEMORY_CONFIG_GUID \ + { \ + 0x98cf19ed, 0x4109, 0x4681, 0xb7, 0x9d, 0x91, 0x96, 0x75, 0x7c, 0x78, 0x24 \ + } + +// {6BE64B20-C679-4ECD-ACE8-87AB4B70EC06} +#define SOCKET_MISC_CONFIG_GUID \ + { \ + 0x6be64b20, 0xc679, 0x4ecd, 0xac, 0xe8, 0x87, 0xab, 0x4b, 0x70, 0xec, 0x6 \ + } +// {A1047342-BDBA-4DAE-A67A-40979B65C7F8} +#define SOCKET_POWERMANAGEMENT_CONFIG_GUID \ + { \ + 0xA1047342, 0xBDBA, 0x4DAE, 0xA6, 0x7A, 0x40, 0x97, 0x9B, 0x65, 0xC7, 0xF8 \ + } +// {07013588-C789-4E12-A7C3-88FAFAE79F7C} +#define SOCKET_PROCESSORCORE_CONFIG_GUID \ + { \ + 0x07013588, 0xC789, 0x4E12, 0xA7, 0xC3, 0x88, 0xFA, 0xFA, 0xE7, 0x9F, 0x7C \ + } +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/UncoreCommonIncludes.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/UncoreCommonIncludes.h new file mode 100644 index 0000000000..a80d492d24 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/UncoreCommonIncludes.h @@ -0,0 +1,354 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _UNCORE_COMMON_INCLUDES_H_ +#define _UNCORE_COMMON_INCLUDES_H_ + +#ifndef V_INTEL_VID +#define V_INTEL_VID 0x8086 +#endif + +#ifndef MAX_CORE +#define MAX_CORE 28 // Maximum cores per CPU (SKX) +#define MAX_CORE_BITMASK 0xFFFFFFF // for SKX CPU +#endif + +#define MAX_PROCESSOR_CORE_RATIO 100 +#define DEFAULT_PROCESSOR_CORE_RATIO 23 +#define MAX_SCRAMBLE_SEED_LOW 65535 +#define MAX_SCRAMBLE_SEED_HIGH 65535 +#define ITURBO_MODE_TRADITIONAL 0 +#define ITURBO_MODE_POWER_OPTIMIZED 4 +#define MAX_PROCESSOR_TSEG 5 + + +// Define the different SKX package Sku's +#define SKX_PHY_CHOP_HCC 0x2 +#define SKX_PHY_CHOP_MCC 0x1 +#define SKX_PHY_CHOP_LCC 0x0 + +// +// Defines used for variables to be range checked before consumption. +// For MiniBIOS support, these are also defined in +// so any changes here need to be updated in these files as well. +// If you change this, please also update CPU_FAMILY_XXX in \Library\ProcMemInit\Include\CpuPciAccess.h, Library\ProcessorStartup\Ia32\ProcessorStartupPlatform.inc +#ifndef CPU_FAMILY_HSX +#define CPU_FAMILY_HSX 0x306F // Haswell CPU +#endif +#ifndef CPU_FAMILY_SKX +#define CPU_FAMILY_SKX 0x5065 // Skylake CPU +#endif + +// SKX REV_ID SiliconID SteppingID CPUID ChopType +// A0 0 0 0 0x50650 3 +// A1 0 1 0 0x50650 3 +// A2 2 2 1 0x50651 3 +// B0 3 3 2 0x50652 3 +// L0 4 4 2 0x50652 2 +// B1 5 5 3 0x50653 3 +// H0 6 6 4 0x50654 3 (xcc) +// M0 7 6 4 0x50654 2 (hcc) +// U0 8 6 4 0x50654 0 (lcc) +// +// xy_REV_SKX is the logical ID for BIOS to distinguish the Si +// A0 and A1 still keep to 0 +// +#ifndef A0_REV +#define A0_REV 0x00 +#endif +#ifndef A0_REV_SKX +#define A0_REV_SKX A0_REV +#endif +#ifndef A1_REV_SKX +#define A1_REV_SKX A0_REV +#endif +#ifndef A2_REV_SKX +#define A2_REV_SKX 0x02 +#endif +#ifndef B0_REV_SKX +#define B0_REV_SKX 0x03 +#endif +#ifndef L0_REV_SKX +#define L0_REV_SKX 0x04 +#endif +#ifndef B1_REV_SKX +#define B1_REV_SKX 0x05 +#endif +#ifndef H0_REV_SKX +#define H0_REV_SKX 0x06 +#endif +#ifndef M0_REV_SKX +#define M0_REV_SKX 0x07 +#endif +#ifndef U0_REV_SKX +#define U0_REV_SKX 0x08 +#endif + +#ifndef C0_REV_SKX +#define C0_REV_SKX 0x09 +#endif + +// +// Xy_CPU_STEP is from CPUID +// +#ifndef A0_CPU_STEP +#define A0_CPU_STEP 0x00 +#endif +#ifndef A1_CPU_STEP +#define A1_CPU_STEP A0_CPU_STEP +#endif +#ifndef A2_CPU_STEP +#define A2_CPU_STEP 0x01 +#endif +#ifndef B0_CPU_STEP +#define B0_CPU_STEP 0x02 +#endif +#ifndef L0_CPU_STEP +#define L0_CPU_STEP 0x02 +#endif +#ifndef B1_CPU_STEP +#define B1_CPU_STEP 0x03 +#endif +#ifndef H0_CPU_STEP +#define H0_CPU_STEP 0x04 +#endif +#ifndef M0_CPU_STEP +#define M0_CPU_STEP 0x04 +#endif +#ifndef U0_CPU_STEP +#define U0_CPU_STEP 0x04 +#endif + +#ifndef C0_CPU_STEP +#define C0_CPU_STEP 0x05 +#endif + +#include "MaxSocket.h" + +#define MAX_THREAD 2 +#define MAX_DIE 1 +#define MAX_CPU_NUM (MAX_THREAD * MAX_CORE * MAX_DIE * MAX_SOCKET) + +#ifndef MAX_HA +#define MAX_HA 2 +#endif + + +// If you change this, please also update MAX_KTI_PORTS in \Library\ProcMemInit\Platform\Include\PlatformHost.h +#ifndef MAX_KTI_PORTS +#define MAX_KTI_PORTS 3 // Max KTI ports supported +#endif + +// If you change this, please also update MAX_IMC in Library\ProcMemInit\Include\MemHostChip.h +// If you change this, please also update MAX_IMC in Library\ProcMemInit\Platform\Include\MemDefaults.h +#ifndef MAX_IMC +#define MAX_IMC 2 // Maximum memory controllers per socket +#endif + +// If you change this, please also update MAX_MC_CH in Library\ProcMemInit\Include\MemHostChip.h +// If you change this, please also update MAX_IMC in Library\ProcMemInit\Platform\Include\MemDefaults.h +#ifndef MAX_MC_CH +#define MAX_MC_CH 3 // Max number of channels per MC (3 for EP) +#endif + + +// If you change this, please also update MAX_CH in Library\ProcMemInit\Include\MemHostChip.h +// If you change this, please also update MAX_IMC in Library\ProcMemInit\Platform\Include\MemDefaults.h +#ifndef MAX_CH +#define MAX_CH ((MAX_IMC)*(MAX_MC_CH)) // Max channels per socket (worst case EP * EX combination = 16) +#endif + +// If you change this, please also update MAX_DIMM in Library\ProcMemInit\Include\MemHostChip.h +#ifndef MAX_DIMM +#define MAX_DIMM 2 // Max DIMM per channel +#endif + +// If you change this, please also update MC_MAX_NODE in Library\ProcMemInit\Include\MemHostChip.h +#ifndef MC_MAX_NODE +#define MC_MAX_NODE (MAX_SOCKET * MAX_IMC) // Max number of memory nodes +#endif + +// If you change this, please also update MAX_SYS_CH in Library\ProcMemInit\Include\MemHostChip.h +// If you change this, please also update MAX_IMC in Library\ProcMemInit\Platform\Include\MemDefaults.h +#ifndef MAX_SYS_CH +#define MAX_SYS_CH (MAX_CH * MAX_SOCKET) // Max channels in the system +#endif +#define MAX_SYS_DIMM MAX_SYS_CH * MAX_DIMM + +#define MAX_CRS_ENTRIES_PER_NODE 8 // Max number of ranges allowed on a memory node +#ifndef NUMBER_PORTS_PER_SOCKET +#define NUMBER_PORTS_PER_SOCKET 21 +#endif + +#ifndef CB3_DEVICES_PER_SOCKET +#define CB3_DEVICES_PER_SOCKET 8 +#endif + +#ifndef TOTAL_CB3_DEVICES +#if MAX_SOCKET > 4 +#define TOTAL_CB3_DEVICES 64 // Todo Check SKX CB3 devices (IOAT_TOTAL_FUNCS * MAX_SOCKET). Note: this covers up to 8S. +#else +#define TOTAL_CB3_DEVICES 32 // Todo Check SKX CB3 devices. +#endif +#endif + +#ifndef MaxIIO +#define MaxIIO MAX_SOCKET +#endif + +#ifndef MAX_TOTAL_PORTS +#if MAX_SOCKET > 4 +#define MAX_TOTAL_PORTS 168 //NUMBER_PORTS_PER_SOCKET * MaxIIO. As now, treats setup S0-S3 = S4_S7 as optimal +#else +#define MAX_TOTAL_PORTS 84 //NUMBER_PORTS_PER_SOCKET * MaxIIO +#endif +#endif + +#ifndef TOTAL_IIO_STACKS +#if MAX_SOCKET > 4 +#define TOTAL_IIO_STACKS 48 // MAX_SOCKET * MAX_IIO_STACK. Not reflect architecture but only sysHost structure! +#else +#define TOTAL_IIO_STACKS 24 // MAX_SOCKET * MAX_IIO_STACK +#endif +#endif + +#ifndef NUMBER_NTB_PORTS_PER_SOCKET +#define NUMBER_NTB_PORTS_PER_SOCKET 3 +#endif + +#ifndef MAX_NTB_PORTS + +#if MAX_SOCKET > 4 +#define MAX_NTB_PORTS 24 // NUMBER_NTB_PORTS_PER_SOCKET * MAX_SOCKET +#else +#define MAX_NTB_PORTS 12 // NUMBER_NTB_PORTS_PER_SOCKET * MAX_SOCKET +#endif +#endif + +#ifndef VMD_STACK_PER_SOCKET +#define VMD_STACK_PER_SOCKET 3 +#endif + +#ifndef VMD_PORT_PER_STACK +#define VMD_PORT_PER_STACK 4 +#endif + +#ifndef VMD_PORTS_PER_SOCKET +#define VMD_PORTS_PER_SOCKET 12 +#endif + +#if MAX_SOCKET > 4 +#ifndef MAX_VMD_PORTS +#define MAX_VMD_PORTS 96 // VMD_PORTS_PER_SOCKET * MAX_SOCKET +#endif + +#ifndef MAX_VMD_STACKS +#define MAX_VMD_STACKS 24 // VMD_STACK_PER_SOCKET * MAX_SOCKET*/ +#endif +#else +#ifndef MAX_VMD_PORTS +#define MAX_VMD_PORTS 48 // VMD_PORTS_PER_SOCKET * MAX_SOCKET +#endif + +#ifndef MAX_VMD_STACKS +#define MAX_VMD_STACKS 12 // VMD_STACK_PER_SOCKET * MAX_SOCKET*/ +#endif +#endif + +#ifndef NUM_DEVHIDE_REGS +#define NUM_DEVHIDE_REGS 8 +#endif + +#ifndef MAX_DEVHIDE_REGS +#define MAX_DEVHIDE_REGS (MAX_IIO_STACK * NUM_DEVHIDE_REGS) +#endif + +#ifndef MAX_DEVHIDE_REGS_PER_SYSTEM + +#if MAX_SOCKET > 4 +#define MAX_DEVHIDE_REGS_PER_SYSTEM 384 //(MAX_DEVHIDE_REGS * MAX_SOCKET) +#else +#define MAX_DEVHIDE_REGS_PER_SYSTEM 192 //(MAX_DEVHIDE_REGS * MAX_SOCKET) +#endif + +#endif + + +#if MAX_SOCKET > 4 +#define MAX_TOTAL_CORE_HIDE 32 //(MAX_SOCKET * VARIABLE_FUNC3_ELEMENTS) +#else +#define MAX_TOTAL_CORE_HIDE 16 //(MAX_SOCKET * VARIABLE_FUNC3_ELEMENTS) +#endif + +#define MAX_IOU_PORT_DEVICES 4 + +// +// Resource Ratio units used by Uncore Init PEIM. +// +// Assumption: these values must be 2^N; Otherwise the algorithm in OemProcMemInit.c +// needs to be adjusted: the "if (Alignment > KTI_SOCKET_BUS_RATIO_UNIT) {" should be +// removed when computing adjusted "Length". +// +#define KTI_SOCKET_BUS_RATIO_UNIT 0x20 +#define KTI_SOCKET_IO_RATIO_UNIT 0x2000 +#define KTI_SOCKET_MMIOL_RATIO_UNIT 0x4000000 +// +// Maximum alignment bit allowed for Socket PCI Resources. +// +#define KTI_SOCKET_MAX_BUS_ALIGNMENT 0x8 +#define KTI_SOCKET_MAX_IO_ALIGNMENT 0x10 +#define KTI_SOCKET_MAX_MMIOL_ALIGNMENT 0x20 + +#ifndef MAX_IIO_STACK +#define IIO_CSTACK 0 +#define IIO_PSTACK0 1 +#define IIO_PSTACK1 2 +#define IIO_PSTACK2 3 +#define IIO_PSTACK3 4 +#define IIO_PSTACK4 5 +#define MAX_IIO_STACK 6 +#endif + +#ifndef UNDEFINED_RAS +#define HEDT_RAS 0x0 +#define BASIC_RAS_AX 0x1 // Valid in A stepping only. +#define S1WS_RAS 0x2 // Not valid in A stepping. +#define CORE_RAS 0x3 // Not valid in A stepping . +#define STANDARD_RAS 0x4 +#define FPGA_RAS 0x5 // Not valid in A stepping. +#define ADVANCED_RAS 0x6 +#define UNDEFINED_RAS 0x7 +#endif + +// +// Defines used for variables to be range checked before consumption. +// +#define MAX_CAS_LATENCY 32 +#define MAX_TRP_LATENCY 32 +#define MAX_TRCD_LATENCY 32 +#define MAX_TRRD_LATENCY 255 +#define MAX_TWTR_LATENCY 255 +#define MAX_TRAS_LATENCY 63 +#define MAX_TRTP_LATENCY 255 +#define MAX_TWR_LATENCY 50 +#define MAX_TFAW_LATENCY 63 +#define MAX_TCWL_LATENCY 31 +#define MAX_TRC_LATENCY 255 +#define MAX_REFRESH_RATE 32767 +#define MAX_TRFC_LATENCY 1023 +#define MAX_MC_BGF_THRESHOLD 15 + +// +// ACPI table information used to initialize tables. +// +#define EFI_ACPI_OEM_ID "INTEL " +#define EFI_ACPI_OEM_TABLE_ID 0x59454C525550 // "PURLEY" +#define EFI_ACPI_OEM_REVISION 0x00000002 +#define EFI_ACPI_CREATOR_ID 0x4C544E49 // "INTL" +#define EFI_ACPI_CREATOR_REVISION 0x20091013 // Oct 13 2009 + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Include/UsraAccessType.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/UsraAccessType.h new file mode 100644 index 0000000000..143069b782 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Include/UsraAccessType.h @@ -0,0 +1,195 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __USRA_ACCESS_TYPE_H__ +#define __USRA_ACCESS_TYPE_H__ + +typedef enum { + AddrTypePCIE = 0, + AddrTypePCIEBLK, + AddrTypeCSR, + AddrTypeMMIO, + AddrTypeIO, + AddrTypeMaximum +} USRA_ADDR_TYPE; + +typedef enum { + UsraWidth8 = 0, + UsraWidth16, + UsraWidth32, + UsraWidth64, + UsraWidthFifo8, + UsraWidthFifo16, + UsraWidthFifo32, + UsraWidthFifo64, + UsraWidthFill8, + UsraWidthFill16, + UsraWidthFill32, + UsraWidthFill64, + UsraWidthMaximum +} USRA_ACCESS_WIDTH; + +typedef enum { + CsrBoxInst = 0, + CsrChId, + CsrMcId, + CsrSubTypeMax +} CSR_INST_TYPE; + +#define USRA_ENABLE 1; +#define USRA_DISABLE 0; + +#pragma pack (1) + +typedef struct + { + UINT32 RawData32[2]; // RawData of two UINT32 type, place holder + UINT32 AddrType:8; // Address type: CSR, PCIE, MMIO, IO, SMBus ... + UINT32 AccessWidth:4; // The Access width for 8, 16,32,64 -bit access + UINT32 FastBootEn:1; // Fast Boot Flag, can be used to log register access trace for fast boot + UINT32 S3Enable:1; // S3 Enable bit, when enabled, it will save the write to script to support S3 + UINT32 HptrType:1; // Host Pointer type, below or above 4GB + UINT32 ConvertedType:1; // The address type was from converted type, use this field for address migration support + UINT32 RFU3:16; // Reserved for User use or Future Use + + UINT32 HostPtr:32; // The Host Pointer, to point to Attribute buffer etc. +} ADDR_ATTRIBUTE_TYPE; + +typedef struct + { + UINT32 Offset:12; // The PCIE Register Offset + UINT32 Func:3; // The PCIE Function + UINT32 Dev:5; // The PCIE Device + UINT32 Bus:8; // The PCIE Bus + UINT32 RFU1:4; // Reserved for User use or Future Use + + UINT32 Seg:16; // The PCI Segment + UINT32 Count:16; // Access Count + +} USRA_PCIE_ADDR_TYPE; + +typedef struct + { + UINT32 Offset; // This Offset occupies 32 bits. It's platform code's responsibilty to define the meaning of specific + // bits and use them accordingly. + UINT32 InstId:8; // The Box Instance, 0 based, Index/Port within the box, Set Index as 0 if the box has only one instances + UINT32 SocketId:8; // The socket Id + UINT32 InstType:8; // The Instance Type, it can be Box, Memory Channel etc. + UINT32 RFU:8; // Reserved for User use or Future Ues + +} USRA_CSR_ADDR_TYPE; + +typedef struct + { + UINT32 Offset:32; // The MMIO Offset + + UINT32 OffsetH: 32; // The MMIO Offset Higher 32-bit +} USRA_MMIO_ADDR_TYPE; + +typedef struct + { + UINT32 Offset:16; // The IO Offset + UINT32 RFU1:16; // Reserved for User use or Future Use + + UINT32 RFU2:32; // Reserved for User use or Future Use + +} USRA_IO_ADDR_TYPE; + +#pragma pack() + +typedef union { + UINT32 dwRawData[4]; + ADDR_ATTRIBUTE_TYPE Attribute; // The address attribute type. + USRA_PCIE_ADDR_TYPE Pcie; + USRA_PCIE_ADDR_TYPE PcieBlk; + USRA_CSR_ADDR_TYPE Csr; + USRA_MMIO_ADDR_TYPE Mmio; + USRA_IO_ADDR_TYPE Io; +} USRA_ADDRESS; + +// +// Assemble macro for USRA_PCIE_ADDR_TYPE +// +#define USRA_PCIE_SEG_ADDRESS(Address, WIDTH, SEG, BUS, DEV, FUNC, OFFSET) \ + USRA_ZERO_ADDRESS(Address); \ + ((USRA_ADDRESS *)(&Address))->Attribute.AccessWidth = WIDTH; \ + ((USRA_ADDRESS *)(&Address))->Attribute.AddrType = AddrTypePCIE; \ + ((USRA_ADDRESS *)(&Address))->Pcie.Seg = (UINT32)(SEG); \ + ((USRA_ADDRESS *)(&Address))->Pcie.Bus = (UINT32)(BUS) & 0xFF; \ + ((USRA_ADDRESS *)(&Address))->Pcie.Dev = (UINT32)(DEV) & 0x1F; \ + ((USRA_ADDRESS *)(&Address))->Pcie.Func = (UINT32)(FUNC) & 0x07; \ + ((USRA_ADDRESS *)(&Address))->Pcie.Offset = (UINT32)(OFFSET) & 0x0FFF + +// +// Assemble macro for USRA_BDFO_ADDR_TYPE +// +#define USRA_PCIE_SEG_BDFO_ADDRESS(Address, WIDTH, SEG, BDFO) \ + USRA_ZERO_ADDRESS(Address); \ + ((USRA_ADDRESS *)(&Address))->Attribute.AccessWidth = WIDTH; \ + ((USRA_ADDRESS *)(&Address))->Attribute.AddrType = AddrTypePCIE; \ + ((USRA_ADDRESS *)(&Address))->Pcie.Seg = (UINT32)(SEG); \ + ((USRA_ADDRESS *)(&Address))->Pcie.Bus = (UINT32)(BDFO >> 20) & 0xFF; \ + ((USRA_ADDRESS *)(&Address))->Pcie.Dev = (UINT32)(BDFO >> 15) & 0x1F; \ + ((USRA_ADDRESS *)(&Address))->Pcie.Func = (UINT32)(BDFO >> 12) & 0x07; \ + ((USRA_ADDRESS *)(&Address))->Pcie.Offset = (UINT32)(BDFO) & 0x0FFF + +// +// Assemble macro for USRA_PCIE_BLK_ADDR_TYPE +// +#define USRA_BLOCK_PCIE_ADDRESS(Address, WIDTH, COUNT, SEG, BUS, DEV, FUNC, OFFSET) \ + USRA_ZERO_ADDRESS(Address); \ + ((USRA_ADDRESS *)(&Address))->Attribute.AccessWidth = WIDTH; \ + ((USRA_ADDRESS *)(&Address))->Attribute.AddrType = AddrTypePCIEBLK; \ + ((USRA_ADDRESS *)(&Address))->PcieBlk.Count = (UINT32)COUNT; \ + ((USRA_ADDRESS *)(&Address))->PcieBlk.Seg = (UINT32)SEG; \ + ((USRA_ADDRESS *)(&Address))->PcieBlk.Bus = (UINT32)(BUS) & 0xFF; \ + ((USRA_ADDRESS *)(&Address))->PcieBlk.Dev = (UINT32)(DEV) & 0x1F; \ + ((USRA_ADDRESS *)(&Address))->PcieBlk.Func = (UINT32)(FUNC) & 0x07; \ + ((USRA_ADDRESS *)(&Address))->PcieBlk.Offset = (UINT32)(OFFSET) & 0x0FFF +// +// Assemble macro for USRA_PCIE_SEG_ADDR_TYPE +// +#define USRA_PCIE_ADDRESS(Address, WIDTH, BUS, DEV, FUNC, OFFSET) \ + USRA_PCIE_SEG_ADDRESS(Address, WIDTH, 0, BUS, DEV, FUNC, OFFSET) + +// +// Assemble macro for USRA_CSR_ADDR_TYPE +// +#define USRA_CSR_OFFSET_ADDRESS(Address, SOCKETID, INSTID, CSROFFSET, INSTTYPE) \ + USRA_ZERO_ADDRESS(Address); \ + ((USRA_ADDRESS *)(&Address))->Attribute.AddrType = AddrTypeCSR; \ + ((USRA_ADDRESS *)(&Address))->Csr.InstType = INSTTYPE; \ + ((USRA_ADDRESS *)(&Address))->Csr.SocketId = SOCKETID; \ + ((USRA_ADDRESS *)(&Address))->Csr.InstId = INSTID; \ + ((USRA_ADDRESS *)(&Address))->Csr.Offset = CSROFFSET + +// +// Assemble macro for ZERO_USRA ADDRESS +// +#define USRA_ZERO_ADDRESS(Address) \ + ((UINT32 *)&Address)[3] = (UINT32)0; \ + ((UINT32 *)&Address)[2] = (UINT32)0; \ + ((UINT32 *)&Address)[1] = (UINT32)0; \ + ((UINT32 *)&Address)[0] = (UINT32)0 + +// +// Assemble macro for ZERO_ADDR_TYPE +// +#define USRA_ZERO_ADDRESS_TYPE(Address, AddressType) \ + ((UINT32 *)&Address)[3] = (UINT32)0; \ + ((UINT32 *)&Address)[2] = (UINT32)((AddressType) & 0x0FF); \ + ((UINT32 *)&Address)[1] = (UINT32)0; \ + ((UINT32 *)&Address)[0] = (UINT32)0 + +#define USRA_ADDRESS_COPY(DestAddrPtr, SourceAddrPtr) \ + ((UINT32 *)DestAddrPtr)[3] = ((UINT32 *)SourceAddrPtr)[3]; \ + ((UINT32 *)DestAddrPtr)[2] = ((UINT32 *)SourceAddrPtr)[2]; \ + ((UINT32 *)DestAddrPtr)[1] = ((UINT32 *)SourceAddrPtr)[1]; \ + ((UINT32 *)DestAddrPtr)[0] = ((UINT32 *)SourceAddrPtr)[0]; + +#endif + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioConfig.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioConfig.h new file mode 100644 index 0000000000..1c6b16ebed --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioConfig.h @@ -0,0 +1,300 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _IIO_CONFIG_H +#define _IIO_CONFIG_H + +#pragma pack(1) //to align members on byte boundary +typedef struct { + +/** +================================================================================================== +================================== VTd Setup Options ================================== +================================================================================================== +**/ + + UINT8 VTdSupport; + UINT8 InterruptRemap; + UINT8 CoherencySupport; + UINT8 ATS; + UINT8 PostedInterrupt; + UINT8 PassThroughDma; + +/** +================================================================================================== +================================== PCIE Setup Options ================================== +================================================================================================== +**/ + UINT8 IioPresent[MAX_SOCKET]; + UINT8 VtdAcsWa; + + // Platform data needs to update these PCI Configuration settings + UINT8 SLOTIMP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Slot Implemented - PCIE Capabilities (D0-10 / F0 / R0x92 / B8) + UINT16 SLOTPSP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Physical slot Number - Slot Capabilities (D0-10 / F0 / R0xA4 / B31:19). Change to use 13 bits instead of 8 + UINT8 SLOTEIP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Electromechanical Interlock Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B17) + UINT8 SLOTSPLS[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Slot Power Limit Scale - Slot Capabilities (D0-10 / F0 / R0xA4 / B16:15) + UINT8 SLOTSPLV[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Slot Power Limit Value - Slot Capabilities (D0-10 / F0 / R0xA4 / B14:7) + UINT8 SLOTHPCAP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Slot Hot Plug capable - Slot Capabilities (D0-10 / F0 / R0xA4 / B6) + UINT8 SLOTHPSUP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Hot Plug surprise supported - Slot Capabilities (D0-10 / F0 / R0xA4 / B5) + UINT8 SLOTPIP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Power Indicator Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B4) + UINT8 SLOTAIP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Attention Inductor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B3) + UINT8 SLOTMRLSP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // MRL Sensor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B2) + UINT8 SLOTPCP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Power Controller Present - Slot Capabilities (D0-10 / F0 / R0xA4 /B1) + UINT8 SLOTABP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Attention Button Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B0) + UINT8 PcieSSDCapable[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Indicate if Port will PcieSSD capable. + + // General PCIE Configuration + UINT8 ConfigIOU0[MAX_SOCKET]; // 00-x4x4x4x4, 01-x4x4x8NA, 02-x8NAx4x4, 03-x8NAx8NA, 04-x16 (P5p6p7p8) + UINT8 ConfigIOU1[MAX_SOCKET]; // 00-x4x4x4x4, 01-x4x4x8NA, 02-x8NAx4x4, 03-x8NAx8NA, 04-x16 (P9p10p11p12) + UINT8 ConfigIOU2[MAX_SOCKET]; // 00-x4x4x4x4, 01-x4x4x8NA, 02-x8NAx4x4, 03-x8NAx8NA, 04-x16 (P1p2p3p4) + UINT8 ConfigMCP0[MAX_SOCKET]; // 04-x16 (p13) + UINT8 ConfigMCP1[MAX_SOCKET]; // 04-x16 (p14) + UINT8 CompletionTimeoutGlobal; // + UINT8 CompletionTimeoutGlobalValue; + UINT8 CompletionTimeout[MAX_SOCKET]; // On Setup + UINT8 CompletionTimeoutValue[MAX_SOCKET]; // On Setup + UINT8 CoherentReadPart; + UINT8 CoherentReadFull; + UINT8 PcieGlobalAspm; // + UINT8 StopAndScream; // + UINT8 SnoopResponseHoldOff; // + // + // PCIE capability + // + UINT8 PCIe_LTR; // + UINT8 PcieExtendedTagField; // + UINT8 PCIe_AtomicOpReq; // + UINT8 PcieMaxReadRequestSize; // + + + UINT8 RpCorrectableErrorEsc[MAX_SOCKET]; //on Setup + UINT8 RpUncorrectableNonFatalErrorEsc[MAX_SOCKET]; //on Setup + UINT8 RpUncorrectableFatalErrorEsc[MAX_SOCKET]; //on Setup + + + // mixc PCIE configuration + UINT8 PcieLinkDis[MAX_TOTAL_PORTS]; // On Setup + UINT8 PcieAspm[MAX_TOTAL_PORTS]; // On Setup + UINT8 PcieCommonClock[MAX_TOTAL_PORTS]; // On Setup + UINT8 PcieMaxPayload[MAX_TOTAL_PORTS]; // On Setup PRD + UINT8 PcieDState[MAX_TOTAL_PORTS]; // On Setup + UINT8 PcieL0sLatency[MAX_TOTAL_PORTS]; //On Setup + UINT8 PcieL1Latency[MAX_TOTAL_PORTS]; //On Setup + UINT8 MsiEn[MAX_TOTAL_PORTS]; // On Setup + UINT8 ExtendedSync[MAX_TOTAL_PORTS]; // On Setup + UINT8 InbandPresenceDetect[MAX_TOTAL_PORTS]; // Not implemented in code + UINT8 PciePortDisable[MAX_TOTAL_PORTS]; // Not implemented in code + UINT8 PciePmeIntEn[MAX_TOTAL_PORTS]; // Not implemented in code + UINT8 IODC[MAX_TOTAL_PORTS]; // On Setup + // + // VPP Control + // + UINT8 VppEnable[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // 00 -- Disable, 01 -- Enable //no setup option defined- aj + UINT8 VppPort[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // 00 -- Port 0, 01 -- Port 1 //no setup option defined- aj + UINT8 VppAddress[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // 01-07 for SMBUS address of Vpp //no setup option defined- aj + + // + // PCIE setup options for Link Control2 + // + UINT8 PciePortLinkSpeed[MAX_TOTAL_PORTS]; //on Setup + UINT8 ComplianceMode[MAX_TOTAL_PORTS]; // On Setup PRD + UINT8 PciePortLinkMaxWidth[MAX_TOTAL_PORTS]; // On Setup + UINT8 DeEmphasis[MAX_TOTAL_PORTS]; // On Setup + + // + // PCIE setup options for MISCCTRLSTS + // + UINT8 EOI[MAX_TOTAL_PORTS]; // On Setup + UINT8 MSIFATEN[MAX_TOTAL_PORTS]; //On Setup. + UINT8 MSINFATEN[MAX_TOTAL_PORTS]; //On Setup. + UINT8 MSICOREN[MAX_TOTAL_PORTS]; //On Setup. + UINT8 ACPIPMEn[MAX_TOTAL_PORTS]; //On Setup + UINT8 DISL0STx[MAX_TOTAL_PORTS]; //On Setup + UINT8 P2PWrtDis[MAX_TOTAL_PORTS]; //On Setup Peer 2 Peer + UINT8 P2PRdDis[MAX_TOTAL_PORTS]; //On Setup Peer 2 peer + UINT8 DisPMETOAck[MAX_TOTAL_PORTS]; //On Setup + UINT8 ACPIHP[MAX_TOTAL_PORTS]; //On Setup + UINT8 ACPIPM[MAX_TOTAL_PORTS]; //On Setup + UINT8 SRIS[MAX_TOTAL_PORTS]; //On Setup + UINT8 TXEQ[MAX_TOTAL_PORTS]; //On Setup + UINT8 ECRC[MAX_TOTAL_PORTS]; //On Setup + // + // PCIE RAS (Errors) + // + + UINT8 PcieUnsupportedRequests[MAX_TOTAL_PORTS]; // Unsupported Request per-port option + UINT8 Serr; + UINT8 Perr; + UINT8 IioErrorEn; + UINT8 LerEn; + UINT8 WheaPcieErrInjEn; + + // + // PciePll + // + UINT8 PciePllSsc; //On Setup + + // + // PCIE Link Training Ctrl + // + +/** +================================================================================================== +================================== Crystal Beach 3 Setup Options =========================== +================================================================================================== +**/ + UINT8 Reserved1[MAX_SOCKET]; // on setup + UINT8 Cb3DmaEn[TOTAL_CB3_DEVICES]; // on setup + UINT8 Cb3NoSnoopEn[TOTAL_CB3_DEVICES]; // on setup + UINT8 DisableTPH; + UINT8 PrioritizeTPH; + UINT8 CbRelaxedOrdering; +/** +================================================================================================== +================================== MISC IOH Setup Options ========================== +================================================================================================== +**/ + + // The following are for hiding each individual device and function + UINT8 PEXPHIDE[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Hide any of the DMI or PCIE devices - SKT 0,1,2,3; Device 0-10 PRD + UINT8 PCUF6Hide; // Hide Device PCU Device 30, Function 6 + UINT8 EN1K; // Enable/Disable 1K granularity of IO for P2P bridges 0:20:0:98 bit 2 + UINT8 DualCvIoFlow; // Dual CV IO Flow + UINT8 PcieBiosTrainEnable; // Used as a work around for A0 PCIe + UINT8 MultiCastEnable; // MultiCastEnable test enable + UINT8 McastBaseAddrRegion; // McastBaseAddrRegion + UINT8 McastIndexPosition; // McastIndexPosition + UINT8 McastNumGroup; // McastNumGroup + UINT8 MctpEn; + + UINT8 LegacyVgaSoc; + UINT8 LegacyVgaStack; + + UINT8 HidePEXPMenu[MAX_TOTAL_PORTS]; // to suppress /display the PCIe port menu + +/** +================================================================================================== +================================== NTB Related Setup Options ========================== +================================================================================================== +**/ + UINT8 NtbPpd[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizeOverride[MAX_NTB_PORTS]; //on setup option + UINT8 NtbSplitBar[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizePBar23[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizePBar45[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizePBar4[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizePBar5[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizeSBar23[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizeSBar45[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizeSBar4[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizeSBar5[MAX_NTB_PORTS]; //on setup option + UINT8 NtbSBar01Prefetch[MAX_NTB_PORTS]; //on setup option + UINT8 NtbXlinkCtlOverride[MAX_NTB_PORTS]; //on setup option + +/** +================================================================================================== +================================== VMD Related Setup Options ========================== +================================================================================================== +**/ + UINT8 VMDEnabled[MAX_VMD_STACKS]; + UINT8 VMDPortEnable[MAX_VMD_PORTS]; + UINT8 VMDHotPlugEnable[MAX_VMD_STACKS]; + UINT8 VMDCfgBarSz[MAX_VMD_STACKS]; + UINT8 VMDCfgBarAttr[MAX_VMD_STACKS]; + UINT8 VMDMemBarSz1[MAX_VMD_STACKS]; + UINT8 VMDMemBar1Attr[MAX_VMD_STACKS]; + UINT8 VMDMemBarSz2[MAX_VMD_STACKS]; + UINT8 VMDMemBar2Attr[MAX_VMD_STACKS]; + + /** + ================================================================================================== + ================================== PcieSSD Related Setup Options ========================== + ================================================================================================== + **/ + UINT8 PcieAICEnabled[MAX_VMD_STACKS]; // Indicate if PCIE AIC Device will be connected behind an specific IOUx + UINT8 PcieAICPortEnable[MAX_VMD_PORTS]; + UINT8 PcieAICHotPlugEnable[MAX_VMD_STACKS]; + +/** +================================================================================================== +================================== Gen3 Related Setup Options ========================== +================================================================================================== +**/ + + //PCIE Global Option + UINT8 NoSnoopRdCfg; //on Setup + UINT8 NoSnoopWrCfg; //on Setup + UINT8 MaxReadCompCombSize; //on Setup + UINT8 ProblematicPort; //on Setup + UINT8 DmiAllocatingFlow; //on Setup + UINT8 PcieAllocatingFlow; //on Setup + UINT8 PcieHotPlugEnable; //on Setup + UINT8 PcieAcpiHotPlugEnable; //on Setup + UINT8 HaltOnDmiDegraded; //on Setup + UINT8 RxClockWA; + UINT8 GlobalPme2AckTOCtrl; //on Setup + + UINT8 PcieSlotOprom1; //On Setup + UINT8 PcieSlotOprom2; //On Setup + UINT8 PcieSlotOprom3; //On Setup + UINT8 PcieSlotOprom4; //On Setup + UINT8 PcieSlotOprom5; //On Setup + UINT8 PcieSlotOprom6; //On Setup + UINT8 PcieSlotOprom7; //On Setup + UINT8 PcieSlotOprom8; //On Setup + UINT8 PcieSlotItemCtrl; //On Setup + UINT8 PcieRelaxedOrdering; //On Setup + UINT8 PciePhyTestMode; //On setup +/** +================================================================================================== +================================== IOAPIC Related Setup Options ========================== +================================================================================================== +**/ + + UINT8 DevPresIoApicIio[TOTAL_IIO_STACKS]; +/** +================================================================================================== +================================== Security Related Setup Options ========================== +================================================================================================== +**/ + UINT8 LockChipset; + UINT8 PeciInTrustControlBit; + UINT8 ProcessorX2apic; + UINT8 ProcessorMsrLockControl; + +/** +================================================================================================== +================================== Iio Related Setup Options ========================== +================================================================================================== +**/ + UINT8 RtoEnable; // On Setup + UINT8 RtoLtssmLogger; // On Setup + UINT8 RtoLtssmLoggerStop; // On Setup + UINT8 RtoLtssmLoggerSpeed; // On Setup + UINT8 RtoLtssmLoggerMask; // On Setup + UINT8 RtoJitterLogger; // On Setup + UINT32 RtoSocketDevFuncHide[MAX_DEVHIDE_REGS_PER_SYSTEM]; // On Setup + UINT8 RtoGen3NTBTestCard[MAX_TOTAL_PORTS]; // On Setup + + UINT8 RtoGen3OverrideMode[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3TestCard[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh2_Precursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh2_Cursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh2_Postcursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh3_Precursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh3_Cursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh3_Postcursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoDnTxPreset[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoRxPreset[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoUpTxPreset[MAX_TOTAL_PORTS]; //On Setup + + UINT8 InboundConfiguration[MAX_TOTAL_PORTS]; //On Setup + +} IIO_CONFIG; +#pragma pack() + +#endif // _IIO_CONFIG_H diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioPlatformData.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioPlatformData.h new file mode 100644 index 0000000000..be5ce8ddec --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioPlatformData.h @@ -0,0 +1,298 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _IIO_PLATFORM_DATA_H_ +#define _IIO_PLATFORM_DATA_H_ + +#include +#include +#include +#include +#ifndef MINIBIOS_BUILD +#ifndef IA32 +#include +#include +#include +#define IIO_CPU_CSR_ACCESS EFI_CPU_CSR_ACCESS_PROTOCOL +#endif +#endif + +#define IIO_HANDLE VOID * +#define IIO_STATUS UINT32 + +typedef struct { + UINT8 Register; + UINT8 Function; + UINT8 Device; + UINT8 Bus; + UINT32 ExtendedRegister; +} PCI_ROOT_BRIDGE_PCI_ADDRESS; + +typedef enum { + DmiTypeVc0, + DmiTypeVc1, + DmiTypeVcm, + MaxDmiVcType +} DMI_VC_TYPE; + +typedef enum { + IioDmiTc0, + IioDmiTc1, + IioDmiTc2, + IioDmiTc3, + IioDmiTc4, + IioDmiTc5, + IioDmiTc6, + IioDmiTc7, + IioMaxDmiTc +} IIO_DMI_TC; + +typedef enum { + IIOInitPhase1 = 1, + IIOInitPhase2 = 2, + IIOInitPhase3 = 4, +} IIO_INIT_PHASE; + +typedef enum { + IioBeforeBifurcation, // Point before IOU Bi-fucuation and link training, no generic inbound access at this point + IioAfterBifurcation, // Point immediately after IOU bifurcation and link training but before any PCIe root port initialization + IioPortEnumeration, // Point before Port initialization, no generic inbound access at this point + IioPortEnumProgramMISCCTRL, // Inside IioPortInit.PcieSlotInit + IioEnumEnd, + IioVtDPreEn, + IioVtDInit, + IioVtDEn, // At this point it has been decided to enable VtD through setup IioVtdInit.VtdInitialization + IioPostInitEnd, // this is the last stage of IIO PCIe port init + IioBeforeResources, // At this point IIO Ports configuration has been completed + IioAfterResources, // At this point PCIe Resources allocation has been completed + IioReadyToBoot +} IIO_INIT_ENUMERATION; + + +extern const CHAR* IioPortLabel[]; + +#define IIO_PORT_LABEL(x) ( ((x) < NUMBER_PORTS_PER_SOCKET) ? (IioPortLabel[(x)]) : IioPortLabel[NUMBER_PORTS_PER_SOCKET] ) + +#pragma pack(1) + +typedef union{ + struct{ + UINT32 Value; + UINT32 ValueHigh; + }Address32bit; + UINT64 Address64bit; +}IIO_PTR_ADDRESS; + +typedef struct { + UINT32 Device; + UINT32 Function; + UINT32 RegOffset; + UINT32 AndMask; + UINT32 OrMask; +} PCI_OP_STRUCT; + +typedef struct { + UINT32 Instance; + UINT32 RegOffset; + UINT32 AndMask; + UINT32 OrMask; +} CSR_ACCESS_OP_STRUCT; + +typedef struct { + UINT8 Isoc; + UINT32 meRequestedSize; + UINT8 Vc1_pri_en; + UINT8 Isoc_Enable; +} ISOC_VC_TABLE_STRUCT; + +/* + * Following are the data structure defined to support multiple CBDMA types on a system + */ + +typedef struct{ + UINT32 DcaSupported : 1; + UINT32 NoSnoopSupported : 1; + UINT32 RelaxOrderSupported : 1; +}CB_CONFIG_CAPABILITY; + +typedef struct{ + UINT8 CB_VER; + UINT8 BusNo; + UINT8 DevNo; + UINT8 FunNo; + UINT8 MaxNoChannels; + CB_CONFIG_CAPABILITY CBConfigCap; +}CBDMA_CONTROLLER; + +typedef struct{ + CBDMA_CONTROLLER CbDmaDevice; +}DMA_HOST; + +// <<<< end of CBDMA data structures >>>> + +typedef union { +struct { + UINT32 Dev0 : 1; + UINT32 Dev1 : 1; + UINT32 Dev2 : 1; + UINT32 Dev3 : 1; + UINT32 Dev4 : 1; + UINT32 Dev5 : 1; + UINT32 Dev6 : 1; + UINT32 Dev7 : 1; + UINT32 Dev8 : 1; + UINT32 Dev9 : 1; + UINT32 Dev10 : 1; + UINT32 Dev11 : 1; + UINT32 Dev12 : 1; + UINT32 Dev13 : 1; + UINT32 Dev14 : 1; + UINT32 Dev15 : 1; + UINT32 Dev16 : 1; + UINT32 Dev17 : 1; + UINT32 Dev18 : 1; + UINT32 Dev19 : 1; + UINT32 Dev20 : 1; + UINT32 Dev21 : 1; + UINT32 Dev22 : 1; + UINT32 Dev23 : 1; + UINT32 Dev24 : 1; + UINT32 Dev25 : 1; + UINT32 Dev26 : 1; + UINT32 Dev27 : 1; + UINT32 Dev28 : 1; + UINT32 Dev29 : 1; + UINT32 Dev30 : 1; + UINT32 Dev31 : 1; + } Bits; + UINT32 Data; +} DEVHIDE_FIELD; + +typedef struct{ + UINT32 DevToHide[NUM_DEVHIDE_REGS]; +} IIO_DEVFUNHIDE; + +typedef struct{ + IIO_DEVFUNHIDE IioStackDevHide[MAX_IIO_STACK]; +}IIO_DEVFUNHIDE_TABLE; + +typedef struct { + UINT8 CpuType; + UINT8 CpuStepping; + UINT8 CpuSubType; + UINT8 SystemRasType; + UINT8 IsocEnable; + UINT8 EVMode; + UINT32 meRequestedSize; + UINT8 DmiVc[MaxDmiVcType]; + UINT8 DmiVcId[MaxDmiVcType]; + DMI_VC_TYPE DmiTc[IioMaxDmiTc]; + UINT8 PlatformType; + UINT8 IOxAPICCallbackBootEvent; + UINT8 RasOperation; + UINT8 SocketUnderOnline; + UINT8 CompletedReadyToBootEventServices; + UINT8 SocketPresent[MaxIIO]; + UINT8 SocketBaseBusNumber[MaxIIO]; + UINT8 SocketLimitBusNumber[MaxIIO]; + UINT8 StackPresentBitmap[MaxIIO]; + UINT64_STRUCT SegMmcfgBase[MaxIIO]; + UINT8 SegmentSocket[MaxIIO]; + UINT8 SocketStackPersonality[MaxIIO][MAX_IIO_STACK]; + UINT8 SocketStackBus[MaxIIO][MAX_IIO_STACK]; + UINT8 SocketStackBaseBusNumber[MaxIIO][MAX_IIO_STACK]; + UINT8 SocketStackLimitBusNumber[MaxIIO][MAX_IIO_STACK]; + UINT8 SocketPortBusNumber[MaxIIO][NUMBER_PORTS_PER_SOCKET]; + UINT8 StackPerPort[MaxIIO][NUMBER_PORTS_PER_SOCKET]; + UINT8 SocketUncoreBusNumber[MaxIIO]; + UINT32 PchIoApicBase; + UINT32 PciResourceMem32Base[MaxIIO]; + UINT32 PciResourceMem32Limit[MaxIIO]; + UINT8 Pci64BitResourceAllocation; + UINT32 StackPciResourceMem32Limit[MaxIIO][MAX_IIO_STACK]; + UINT32 VtdBarAddress[MaxIIO][MAX_IIO_STACK]; + UINT32 IoApicBase[MaxIIO][MAX_IIO_STACK]; + UINT32 RcBaseAddress; + UINT64 PciExpressBase; + UINT32 PmBase; + UINT32 PchSegRegBaseAddress; + UINT8 PcieRiser1Type; + UINT8 PcieRiser2Type; + UINT8 DmiVc1; + UINT8 DmiVcm; + UINT8 Emulation; + UINT8 SkuPersonality[MAX_SOCKET]; + UINT8 VMDStackEnable[MaxIIO][MAX_IIO_STACK]; + UINT8 IODC; + UINT8 MultiPch; + UINT8 FpgaActive[MaxIIO]; +} IIO_V_DATA; + +typedef struct { + UINT8 Device; + UINT8 Function; +} IIO_PORT_INFO; + +typedef struct { + UINT8 Valid; + UINT8 IioUplinkPortIndex; //defines platform specific uplink port index (if any else FF) + IIO_PORT_INFO UplinkPortInfo; +}IIO_UPLINK_PORT_INFO; + +typedef struct _INTEL_IIO_PORT_INFO { + UINT8 Device; + UINT8 Function; + UINT8 RtoDevice; + UINT8 RtoFunction; + UINT8 RtoClusterDevice; + UINT8 RtoClusterFunction; + UINT8 RtoReutLinkSel; + UINT8 SuperClusterPort; +} INTEL_IIO_PORT_INFO; + +typedef struct _INTEL_DMI_PCIE_INFO { + INTEL_IIO_PORT_INFO PortInfo[NUMBER_PORTS_PER_SOCKET]; +} INTEL_DMI_PCIE_INFO; + +typedef struct _INTEL_IIO_PRELINK_DATA { + INTEL_DMI_PCIE_INFO PcieInfo; + IIO_UPLINK_PORT_INFO UplinkInfo[MaxIIO]; +} INTEL_IIO_PRELINK_DATA; + +typedef struct { + UINT8 PciePortPresent[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 PciePortConfig[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 PciePortOwnership[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 CurrentPXPMap[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 MaxPXPMap[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 LinkedPXPMap[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 SpeedPXPMap[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 LaneReversedPXPMap[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 PciePortMaxWidth[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 PciePortNegWidth[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 PciePortNegSpeed[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + IIO_PTR_ADDRESS PtrAddress; + IIO_PTR_ADDRESS PtrPcieTopology; + UINT64 McastRsvdMemory; + DMA_HOST DMAhost[MaxIIO]; + UINT8 resetRequired; +} IIO_OUT_DATA; + +typedef struct { + IIO_V_DATA IioVData; + INTEL_IIO_PRELINK_DATA PreLinkData; + IIO_OUT_DATA IioOutData; +} IIO_VAR; + +typedef struct { + IIO_CONFIG SetupData; + IIO_VAR IioVar; +} IIO_GLOBALS; + +#pragma pack() + +#endif //_IIO_PLATFORM_DATA_H_ diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioRegs.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioRegs.h new file mode 100644 index 0000000000..9537e7c3b0 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioRegs.h @@ -0,0 +1,314 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _IIO_REGS_H_ +#define _IIO_REGS_H_ + +/** +================================================================================================== +================================== General Defintions ================================== +================================================================================================== +**/ + +#define NUMBER_PORTS_PER_SOCKET 21 +#define IIO_UPLINK_PORT_INDEX 5 //Port 2A is the uplink port in Neon-City ///TODO Check if this is required for SKX/Purley SKX_TTEST +#define MaxIIO MAX_SOCKET + +#if MAX_SOCKET > 4 +#define TOTAL_CB3_DEVICES 64 // Todo Check SKX CB3 devices (IOAT_TOTAL_FUNCS * MAX_SOCKET). Note: this covers up to 8S. +#define MAX_TOTAL_PORTS 168 //NUMBER_PORTS_PER_SOCKET * MaxIIO. As now, treats setup S0-S3 = S4_S7 as optimal +#else +#define TOTAL_CB3_DEVICES 32 // Todo Check SKX CB3 devices. +#define MAX_TOTAL_PORTS 84 //NUMBER_PORTS_PER_SOCKET * MaxIIO +#endif + +#if MAX_SOCKET > 4 +#define TOTAL_IIO_STACKS 48 // MAX_SOCKET * MAX_IIO_STACK. Not reflect architecture but only sysHost structure! +#define TOTAL_SYSTEM_IIO_STACKS 32 // In term of system architecture support +#else +#define TOTAL_IIO_STACKS 24 // MAX_SOCKET * MAX_IIO_STACK +#define TOTAL_SYSTEM_IIO_STACKS 24 // In term of system architecture support +#endif + +#define NUMBER_NTB_PORTS_PER_SOCKET 3 +#if MAX_SOCKET > 4 +#define MAX_NTB_PORTS 24 // NUMBER_NTB_PORTS_PER_SOCKET * MAX_SOCKET +#else +#define MAX_NTB_PORTS 12 // NUMBER_NTB_PORTS_PER_SOCKET * MAX_SOCKET +#endif +#define VMD_STACK_PER_SOCKET 3 +#define VMD_PORT_PER_STACK 4 +#define VMD_PORTS_PER_SOCKET 12 +#if MAX_SOCKET > 4 +#define MAX_VMD_PORTS 96 // VMD_PORTS_PER_SOCKET * MAX_SOCKET +#define MAX_VMD_STACKS 24 // VMD_STACK_PER_SOCKET * MAX_SOCKET +#else +#define MAX_VMD_PORTS 48 // VMD_PORTS_PER_SOCKET * MAX_SOCKET +#define MAX_VMD_STACKS 12 // VMD_STACK_PER_SOCKET * MAX_SOCKET +#endif + + +#define VARIABLE_FUNC3_ELEMENTS 4 +#if MAX_SOCKET > 4 +#define MAX_TOTAL_CORE_HIDE 32 //(MAX_SOCKET * VARIABLE_FUNC3_ELEMENTS) +#else +#define MAX_TOTAL_CORE_HIDE 16 //(MAX_SOCKET * VARIABLE_FUNC3_ELEMENTS) +#endif + +#define MAX_IOU_PORT_DEVICES 4 + + +/** +================================================================================================== +================================== IIO Root Port Defintions ==================== +================================================================================================== +**/ +typedef enum { + IioPortA = 0, + IioPortB = 1, + IioPortC = 2, + IioPortD = 3 +}IIOPORTS; + +typedef enum { + IioIou0 = 0, + IioIou1, + IioIou2, + IioMcp0, + IioMcp1, + IioIouMax +} IIOIOUS; + +// +// Bifurcation control register shorthand +// +#define IIO_BIFURCATE_AUTO 0xFF + +// Ports 1D-1A, 2D-2A, 3D-3A +// +#define IIO_BIFURCATE_x4x4x4x4 0 +#define IIO_BIFURCATE_x4x4xxx8 1 +#define IIO_BIFURCATE_xxx8x4x4 2 +#define IIO_BIFURCATE_xxx8xxx8 3 +#define IIO_BIFURCATE_xxxxxx16 4 +#define IIO_BIFURCATE_xxxxxxxx 0xF + +#define PORT_0_INDEX 0 +#define PCIE_PORT_2_DEV 0x02 + +// IOU2 +#define PORT_1A_INDEX 1 +#define PORT_1B_INDEX 2 +#define PORT_1C_INDEX 3 +#define PORT_1D_INDEX 4 +// IOU0 +#define PORT_2A_INDEX 5 +#define PORT_2B_INDEX 6 +#define PORT_2C_INDEX 7 +#define PORT_2D_INDEX 8 +// IOU1 +#define PORT_3A_INDEX 9 +#define PORT_3B_INDEX 10 +#define PORT_3C_INDEX 11 +#define PORT_3D_INDEX 12 +//MCP0 +#define PORT_4A_INDEX 13 +#define PORT_4B_INDEX 14 +#define PORT_4C_INDEX 15 +#define PORT_4D_INDEX 16 +//MCP1 +#define PORT_5A_INDEX 17 +#define PORT_5B_INDEX 18 +#define PORT_5C_INDEX 19 +#define PORT_5D_INDEX 20 + +// +#define SOCKET_0_INDEX 0 +#define SOCKET_1_INDEX 21 +#define SOCKET_2_INDEX 42 +#define SOCKET_3_INDEX 63 +#define SOCKET_4_INDEX 84 +#define SOCKET_5_INDEX 105 +#define SOCKET_6_INDEX 126 +#define SOCKET_7_INDEX 147 + +#define PCIE_PORT_0_DEV 0x00 +#define PCIE_PORT_0_FUNC 0x00 + +#define PCIE_PORT_1A_DEV 0x00 +#define PCIE_PORT_1B_DEV 0x01 +#define PCIE_PORT_1C_DEV 0x02 +#define PCIE_PORT_1D_DEV 0x03 +#define PCIE_PORT_1A_FUNC 0x00 +#define PCIE_PORT_1B_FUNC 0x00 +#define PCIE_PORT_1C_FUNC 0x00 +#define PCIE_PORT_1D_FUNC 0x00 + +#define PCIE_PORT_2A_DEV 0x00 +#define PCIE_PORT_2B_DEV 0x01 +#define PCIE_PORT_2C_DEV 0x02 +#define PCIE_PORT_2D_DEV 0x03 +#define PCIE_PORT_2A_FUNC 0x00 +#define PCIE_PORT_2B_FUNC 0x00 +#define PCIE_PORT_2C_FUNC 0x00 +#define PCIE_PORT_2D_FUNC 0x00 + +#define PCIE_PORT_3A_DEV 0x00 +#define PCIE_PORT_3B_DEV 0x01 +#define PCIE_PORT_3C_DEV 0x02 +#define PCIE_PORT_3D_DEV 0x03 +#define PCIE_PORT_3A_FUNC 0x00 +#define PCIE_PORT_3B_FUNC 0x00 +#define PCIE_PORT_3C_FUNC 0x00 +#define PCIE_PORT_3D_FUNC 0x00 + +#define PCIE_PORT_4A_DEV 0x00 +#define PCIE_PORT_4B_DEV 0x01 +#define PCIE_PORT_4C_DEV 0x02 +#define PCIE_PORT_4D_DEV 0x03 +#define PCIE_PORT_4A_FUNC 0x00 +#define PCIE_PORT_4B_FUNC 0x00 +#define PCIE_PORT_4C_FUNC 0x00 +#define PCIE_PORT_4D_FUNC 0x00 + +#define PCIE_PORT_5A_DEV 0x00 +#define PCIE_PORT_5B_DEV 0x01 +#define PCIE_PORT_5C_DEV 0x02 +#define PCIE_PORT_5D_DEV 0x03 +#define PCIE_PORT_5A_FUNC 0x00 +#define PCIE_PORT_5B_FUNC 0x00 +#define PCIE_PORT_5C_FUNC 0x00 +#define PCIE_PORT_5D_FUNC 0x00 + +#define PCIE_PORT_GLOBAL_RTO_DEV 0x07 +#define PCIE_PORT_GLOBAL_RTO_FUNC 0x07 + +#define PCIE_PORT_0_RTO_DEV 0x07 +#define PCIE_PORT_0_RTO_FUNC 0x00 + +#define PCIE_PORT_1A_RTO_DEV 0x07 +#define PCIE_PORT_1A_RTO_FUNC 0x00 +#define PCIE_PORT_1B_RTO_DEV 0x07 +#define PCIE_PORT_1B_RTO_FUNC 0x01 +#define PCIE_PORT_1C_RTO_DEV 0x07 +#define PCIE_PORT_1C_RTO_FUNC 0x02 +#define PCIE_PORT_1D_RTO_DEV 0x07 +#define PCIE_PORT_1D_RTO_FUNC 0x03 + + +#define PCIE_PORT_2A_RTO_DEV 0x07 +#define PCIE_PORT_2A_RTO_FUNC 0x00 +#define PCIE_PORT_2B_RTO_DEV 0x07 +#define PCIE_PORT_2B_RTO_FUNC 0x01 +#define PCIE_PORT_2C_RTO_DEV 0x07 +#define PCIE_PORT_2C_RTO_FUNC 0x02 +#define PCIE_PORT_2D_RTO_DEV 0x07 +#define PCIE_PORT_2D_RTO_FUNC 0x03 + +#define PCIE_PORT_3A_RTO_DEV 0x07 +#define PCIE_PORT_3A_RTO_FUNC 0x00 +#define PCIE_PORT_3B_RTO_DEV 0x07 +#define PCIE_PORT_3B_RTO_FUNC 0x01 +#define PCIE_PORT_3C_RTO_DEV 0x07 +#define PCIE_PORT_3C_RTO_FUNC 0x02 +#define PCIE_PORT_3D_RTO_DEV 0x07 +#define PCIE_PORT_3D_RTO_FUNC 0x03 + +#define PCIE_PORT_4A_RTO_DEV 0x07 +#define PCIE_PORT_4A_RTO_FUNC 0x00 +#define PCIE_PORT_4B_RTO_DEV 0x07 +#define PCIE_PORT_4B_RTO_FUNC 0x01 +#define PCIE_PORT_4C_RTO_DEV 0x07 +#define PCIE_PORT_4C_RTO_FUNC 0x02 +#define PCIE_PORT_4D_RTO_DEV 0x07 +#define PCIE_PORT_4D_RTO_FUNC 0x03 + +#define PCIE_PORT_5A_RTO_DEV 0x07 +#define PCIE_PORT_5A_RTO_FUNC 0x00 +#define PCIE_PORT_5B_RTO_DEV 0x07 +#define PCIE_PORT_5B_RTO_FUNC 0x01 +#define PCIE_PORT_5C_RTO_DEV 0x07 +#define PCIE_PORT_5C_RTO_FUNC 0x02 +#define PCIE_PORT_5D_RTO_DEV 0x07 +#define PCIE_PORT_5D_RTO_FUNC 0x03 + +#define PCIE_PORT_0_LINK_SEL 0x00 +#define PCIE_PORT_1A_LINK_SEL 0x00 +#define PCIE_PORT_1B_LINK_SEL 0x01 +#define PCIE_PORT_1C_LINK_SEL 0x02 +#define PCIE_PORT_1D_LINK_SEL 0x03 +#define PCIE_PORT_2A_LINK_SEL 0x00 +#define PCIE_PORT_2B_LINK_SEL 0x01 +#define PCIE_PORT_2C_LINK_SEL 0x02 +#define PCIE_PORT_2D_LINK_SEL 0x03 +#define PCIE_PORT_3A_LINK_SEL 0x00 +#define PCIE_PORT_3B_LINK_SEL 0x01 +#define PCIE_PORT_3C_LINK_SEL 0x02 +#define PCIE_PORT_3D_LINK_SEL 0x03 +#define PCIE_PORT_4A_LINK_SEL 0x00 +#define PCIE_PORT_4B_LINK_SEL 0x01 +#define PCIE_PORT_4C_LINK_SEL 0x02 +#define PCIE_PORT_4D_LINK_SEL 0x03 +#define PCIE_PORT_5A_LINK_SEL 0x00 +#define PCIE_PORT_5B_LINK_SEL 0x01 +#define PCIE_PORT_5C_LINK_SEL 0x02 +#define PCIE_PORT_5D_LINK_SEL 0x03 + +#define PCIE_PORT_0_SUPER_CLUSTER_PORT 0x00 +#define PCIE_PORT_1A_SUPER_CLUSTER_PORT 0x01 +#define PCIE_PORT_1B_SUPER_CLUSTER_PORT 0x01 +#define PCIE_PORT_1C_SUPER_CLUSTER_PORT 0x01 +#define PCIE_PORT_1D_SUPER_CLUSTER_PORT 0x01 +#define PCIE_PORT_2A_SUPER_CLUSTER_PORT 0x05 +#define PCIE_PORT_2B_SUPER_CLUSTER_PORT 0x05 +#define PCIE_PORT_2C_SUPER_CLUSTER_PORT 0x05 +#define PCIE_PORT_2D_SUPER_CLUSTER_PORT 0x05 +#define PCIE_PORT_3A_SUPER_CLUSTER_PORT 0x09 +#define PCIE_PORT_3B_SUPER_CLUSTER_PORT 0x09 +#define PCIE_PORT_3C_SUPER_CLUSTER_PORT 0x09 +#define PCIE_PORT_3D_SUPER_CLUSTER_PORT 0x09 +#define PCIE_PORT_4A_SUPER_CLUSTER_PORT 0x0D +#define PCIE_PORT_4B_SUPER_CLUSTER_PORT 0x0D +#define PCIE_PORT_4C_SUPER_CLUSTER_PORT 0x0D +#define PCIE_PORT_4D_SUPER_CLUSTER_PORT 0x0D +#define PCIE_PORT_5A_SUPER_CLUSTER_PORT 0x11 +#define PCIE_PORT_5B_SUPER_CLUSTER_PORT 0x11 +#define PCIE_PORT_5C_SUPER_CLUSTER_PORT 0x11 +#define PCIE_PORT_5D_SUPER_CLUSTER_PORT 0x11 + +#define PORT_LINK_WIDTH_x16 16 +#define PORT_LINK_WIDTH_x8 8 +#define PORT_LINK_WIDTH_x4 4 +#define PORT_LINK_WIDTH_x2 2 +#define PORT_LINK_WIDTH_x1 1 + +// +// Port Config Mode +// +#define REGULAR_PCIE_OWNERSHIP 0 +#define PCIE_PORT_REGULAR_MODE 1 +#define PCIE_PORT_NTB_MODE 2 +#define VMD_OWNERSHIP 3 +#define PCIEAIC_OCL_OWNERSHIP 4 + + +/** +================================================================================================== +================================== Devide Hide Definitions ======================================= +================================================================================================== +**/ + +#define NUM_DEVHIDE_REGS 8 +// Hide all 8 Devices for every Stack +#define MAX_DEVHIDE_REGS (MAX_IIO_STACK * NUM_DEVHIDE_REGS) +#if MaxIIO > 4 +#define MAX_DEVHIDE_REGS_PER_SYSTEM 384 //(MAX_DEVHIDE_REGS * MaxIIO) +#else +#define MAX_DEVHIDE_REGS_PER_SYSTEM 192 //(MAX_DEVHIDE_REGS * MaxIIO) +#endif + +#endif //_IIO_REGS_H_ diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioSetupDefinitions.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioSetupDefinitions.h new file mode 100644 index 0000000000..61b7389cff --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioSetupDefinitions.h @@ -0,0 +1,111 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef IIOSETUPDEFINITIONS_H_ +#define IIOSETUPDEFINITIONS_H_ + +/** +================================================================================================== +================= Equates common for Setup options (.vfr/.hfr) and source files (.c/.h) ========== +================================================================================================== +**/ + +#define PCIE_ASPM_AUTO 7 +#define PCIE_ASPM_DISABLE 0 +#define PCIE_ASPM_L0S_ONLY 1 +#define PCIE_ASPM_L1_ONLY 2 +#define PCIE_ASPM_L0S_L1_BOTH 3 + +#define PCIE_LINK_SPEED_AUTO 0 +#define PCIE_LINK_SPEED_GEN1 1 +#define PCIE_LINK_SPEED_GEN2 2 +#define PCIE_LINK_SPEED_GEN3 3 + +#define PCIE_L0S_4US_8US 3 +#define PCIE_L1_8US_16US 4 + +#define IIO_OPTION_AUTO 2 +#define IIO_OPTION_ENABLE 1 +#define IIO_OPTION_DISABLE 0 + +#define GEN3MANUAL_PH2_PRECURSOR_MIN 0 +#define GEN3MANUAL_PH2_CURSOR_MIN 0 +#define GEN3MANUAL_PH2_POSTCURSOR_MIN 0 + +#define GEN3MANUAL_PH2_PRECURSOR_MAX 63 +#define GEN3MANUAL_PH2_CURSOR_MAX 63 +#define GEN3MANUAL_PH2_POSTCURSOR_MAX 63 + +#define GEN3MANUAL_PH2_PRECURSOR_DEFAULT 11 +#define GEN3MANUAL_PH2_CURSOR_DEFAULT 41 +#define GEN3MANUAL_PH2_POSTCURSOR_DEFAULT 11 + +#define GEN3MANUAL_PH3_PRECURSOR_MIN 0 +#define GEN3MANUAL_PH3_CURSOR_MIN 0 +#define GEN3MANUAL_PH3_POSTCURSOR_MIN 0 + +#define GEN3MANUAL_PH3_PRECURSOR_MAX 63 +#define GEN3MANUAL_PH3_CURSOR_MAX 63 +#define GEN3MANUAL_PH3_POSTCURSOR_MAX 63 + +#define GEN3MANUAL_PH3_PRECURSOR_DEFAULT 11 +#define GEN3MANUAL_PH3_CURSOR_DEFAULT 41 +#define GEN3MANUAL_PH3_POSTCURSOR_DEFAULT 11 + +#define RTO_GEN3_OVERRIDE_MODE_UNIPHY 0 +#define RTO_GEN3_OVERRIDE_MODE_MANUAL 1 +#define RTO_GEN3_OVERRIDE_MODE_TEST_CARD 2 +#define RTO_GEN3_OVERRIDE_MODE_ALTERNATE_TXEQ 3 + +#define RTO_GEN3_TEST_CARD_LAGUNA 0 +#define RTO_GEN3_TEST_CARD_NTB 1 + +#define RTO_GEN3_EQ_MODE_TESTCARD 1 +#define RTO_GEN3_EQ_MODE_NTB_TESTCARD 2 + + +#define COMPLETION_TIMEOUT_260MS_900MS 9 + +#define SNOOP_RESP_DEF_VALUE 6 + +#define MC_INDEX_POS_12 0xC + +#define MC_NUM_GROUP_8 8 + +#define CONFIG_IOU_AUTO 0xFF + +#define NTB_BARSIZE_PBAR23_DEFAULT 0xC +#define NTB_BARSIZE_PBAR45_DEFAULT 0xC +#define NTB_BARSIZE_PBAR4_DEFAULT 0xC +#define NTB_BARSIZE_PBAR5_DEFAULT 0xC +#define NTB_BARSIZE_SBAR23_DEFAULT 0xC +#define NTB_BARSIZE_SBAR45_DEFAULT 0xC +#define NTB_BARSIZE_SBAR4_DEFAULT 0xC +#define NTB_BARSIZE_SBAR5_DEFAULT 0xC +#define NTB_IIO_XLINK_CTL_DSD_USP 2 + +#define VMD_CFG_BAR_SIZE_DEFAULT 25 +#define VMD_MEM_BAR_SIZE1_DEFAULT 25 +#define VMD_MEM_BAR_SIZE2_DEFAULT 20 + +#define VMD_32BIT_NONPREFETCH 0 +#define VMD_64BIT_NONPREFETCH 1 +#define VMD_64BIT_PREFETCH 2 + +#define IODC_DISABLE 0 +#define IODC_AUTO 1 +#define IODC_EN_REM_INVITOM_PUSH 2 +#define IODC_EN_REM_INVITOM_ALLOCFLOW 3 +#define IODC_EN_REM_INVITOM_ALLOC_NONALLOC 4 +#define IODC_EN_REM_INVITOM_AND_WCILF 5 +#define IODC_GLOBAL_KTI_OPTION 6 + +#define PCIE_PORT_DISABLE 0 +#define PCIE_PORT_ENABLE 1 +#define PCIE_PORT_AUTO 2 + +#endif /* IIOSETUPDEFINITIONS_H_ */ diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/KtiDisc.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/KtiDisc.h new file mode 100644 index 0000000000..44bf2ec2ff --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/KtiDisc.h @@ -0,0 +1,26 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _KTI_DISCOVERY_H_ +#define _KTI_DISCOVERY_H_ +#ifdef _MSC_VER +#pragma warning (disable: 4127 4214 4100) // disable C4127: constant conditional expression +#endif +#include "DataTypes.h" +#include "PlatformHost.h" +#include "KtiSi.h" + +#define MAX_TREE_NODES (MAX_SOCKET + 2) // 2 additional nodes since a node will appear more than once in the tree when it is being constructed +#define MAX_RING_TREE_NODES 46 // A CPU with 3 links supported will have 1 + 1*3 + 3*2 + 6*2 + 12*2 = 46 nodes maximum in ring tree +#define MAX_RINGS 6 // Maximum number of rings possible in systems with upto 8 sockets (HyperCube) +#define CPUS_PER_RING 4 // # of CPUs in a CPU ring +#define VN0 0 +#define VN1 1 +#define TX 0 +#define RX 1 + +#endif // _KTI_DISCOVERY_H_ diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/KtiHost.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/KtiHost.h new file mode 100644 index 0000000000..7824cfe33b --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/KtiHost.h @@ -0,0 +1,136 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// Definition Flag: +// 1. KTI_HW_PLATFORM -> run with real hardware or SoftIVT +// 2. KTI_SW_SIMULATION -> run with KTIRC Simulation +// 3. IA32 -> run with IA32 mode + + +#ifndef _KTI_HOST_H_ +#define _KTI_HOST_H_ +#ifdef _MSC_VER +#pragma warning (disable: 4127 4214 4100) // disable C4127: constant conditional expression +#endif +#include "DataTypes.h" +#include "PlatformHost.h" +#include "KtiSi.h" +#include "KtiDisc.h" + +#pragma pack(1) + +typedef INT32 KTI_STATUS; +#ifndef NULL +#define NULL 0 +#endif +#define CONST const +#define STATIC static +#define VOID void +#define VOLATILE volatile +#define KTI_SUCCESS 0 +#define KTI_REBOOT 1 +#define KTI_SNC_CHANGED 2 +#define KTI_IGNORE 3 +#define KTI_FAILURE -1 + +// +// Warning log +// +#define MAX_WARNING_LOGS 16 + +typedef enum { + NORMAL_OPERATION = 0, + RECOVERY_OPERATION +} SNC_COLDRESET_REGISTER_OPERATION_TYPE; + +typedef enum { + KTI_GROUP = 0, +} GROUP_TYPE; + +/********************************************************* + KTIRC Host Structure Related +*********************************************************/ + +typedef enum { + KTI_LINK0 = 0x0, + KTI_LINK1, + KTI_LINK2 +} KTI_LOGIC_LINK; + +typedef enum { + FULL_SPEED = 0, + HALF_SPEED +} KTI_LINK_SPEED_TYPE; + + +// +// Definitions to be used in Eparam tables: +// +typedef enum { + PER_LANES_TXEQ_ENABLED = 0, // each lane use different TXEQ value + ALL_LANES_TXEQ_ENABLED // all lanes use same TXEQ value +} LANE_TXEQ_TYPE; + +// +// Number of Clusters. +// +typedef enum { + CLUSTER_MODE_1, + CLUSTER_MODE_2, +} CLUSTER_MODE; + +typedef enum { + LCC = 0, // 10c + MCC, // 14c + HCC, // 22c + XCC, // 28c + MAX_CHOP_TYPES +} PHYSICAL_CHOP; + + +// +// PHY settings that are system dependent. Need 1 of these for each socket/link/freq. +// + +typedef struct { + UINT8 SocketID; + UINT8 AllLanesUseSameTxeq; + UINT8 Freq; + UINT32 Link; + UINT32 TXEQL[20]; + UINT32 CTLEPEAK[5]; +} PER_LANE_EPARAM_LINK_INFO; + +// +// This is for full speed mode, all lanes have the same TXEQ setting +// +typedef struct { + UINT8 SocketID; + UINT8 Freq; + UINT32 Link; + UINT32 AllLanesTXEQ; + UINT8 CTLEPEAK; +} ALL_LANES_EPARAM_LINK_INFO; + +#define ADAPTIVE_CTLE 0x3f +#define PER_LANE_ADAPTIVE_CTLE 0X3f3f3f3f + +typedef enum { + TYPE_UBOX = 0, + TYPE_UBOX_IIO, + TYPE_MCP, + TYPE_FPGA, + TYPE_DISABLED, // This item must be prior to stack specific disable types + TYPE_UBOX_IIO_DIS, + TYPE_MCP_DIS, + TYPE_FPGA_DIS, + TYPE_NONE +} STACK_TYPE; + +#pragma pack() + +#endif // _KTI_HOST_H_ diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/KtiSi.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/KtiSi.h new file mode 100644 index 0000000000..89934b97b7 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/KtiSi.h @@ -0,0 +1,39 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _KTI_SI_H_ +#define _KTI_SI_H_ +#ifdef _MSC_VER +#pragma warning (disable: 4127 4214 4100) // disable C4127: constant conditional expression +#endif +#include "DataTypes.h" +#include "PlatformHost.h" + +/********************************************************* + KTI Topology Related +*********************************************************/ +#define SI_MAX_CPU_SOCKETS 8 // Maximum CPU sockets supported by Si +#define SI_MAX_KTI_PORTS 3 // Maximum KTI ports supported by Si + +/********************************************************* + IIO Stacks +*********************************************************/ +#define IIO_CSTACK 0 +#define IIO_PSTACK0 1 +#define IIO_PSTACK1 2 +#define IIO_PSTACK2 3 +#define IIO_PSTACK3 4 +#define IIO_PSTACK4 5 +#define MAX_IIO_STACK 6 + +/********************************************************* + M3KTI +*********************************************************/ +#define MAX_M3KTI 2 +#define MAX_PORT_IN_M3KTI 2 + +#endif // _KTI_SI_H_ diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Protocol/CpuCsrAccess.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Protocol/CpuCsrAccess.h new file mode 100644 index 0000000000..ee2a407a40 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Protocol/CpuCsrAccess.h @@ -0,0 +1,143 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _CPUCSRACCESS_PROTOCOL_H_ +#define _CPUCSRACCESS_PROTOCOL_H_ + +// +// CPU CSR Access Protocol GUID +// +// {0067835F-9A50-433a-8CBB-852078197814} +#define EFI_CPU_CSR_ACCESS_GUID \ + { \ + 0x67835f, 0x9a50, 0x433a, 0x8c, 0xbb, 0x85, 0x20, 0x78, 0x19, 0x78, 0x14 \ + } + +//#define REG_ADDR( bus, dev, func, reg, size ) ((size << 28) + ((bus+2) << 20) + (dev << 15) + (func << 12) + reg) + +typedef +UINT64 +(EFIAPI *GET_CPU_CSR_ADDRESS) ( + IN UINT8 SocId, + IN UINT8 BoxInst, + IN UINT32 Offset, + IN OUT UINT8 *Size + ); + +typedef +UINT32 +(EFIAPI *READ_CPU_CSR) ( + IN UINT8 SocId, + IN UINT8 BoxInst, + IN UINT32 Offset + ); + +typedef +VOID +(EFIAPI *WRITE_CPU_CSR) ( + IN UINT8 SocId, + IN UINT8 BoxInst, + IN UINT32 RegOffset, + IN UINT32 Data + ); + +typedef +UINT32 +(EFIAPI *READ_MC_CPU_CSR) ( + IN UINT8 SocId, + IN UINT8 McId, + IN UINT32 Offset + ); + +typedef +VOID +(EFIAPI *WRITE_MC_CPU_CSR) ( + IN UINT8 SocId, + IN UINT8 McId, + IN UINT32 RegOffset, + IN UINT32 Data + ); + +typedef +UINTN +(EFIAPI *GET_MC_CPU_ADDR) ( + IN UINT8 SocId, + IN UINT8 McId, + IN UINT32 RegOffset + ); + +typedef +UINT32 +(EFIAPI *READ_PCI_CSR) ( + IN UINT8 socket, + IN UINT32 reg + ); + +typedef +VOID +(EFIAPI *WRITE_PCI_CSR) ( + IN UINT8 socket, + IN UINT32 reg, + IN UINT32 data + ); + +typedef +UINT32 +(EFIAPI *GET_PCI_CSR_ADDR) ( + IN UINT8 socket, + IN UINT32 reg + ); + +typedef +VOID +(EFIAPI *UPDATE_CPU_CSR_ACCESS_VAR) ( + VOID + ); + +typedef +UINT32 +(EFIAPI *BIOS_2_PCODE_MAILBOX_WRITE) ( + IN UINT8 socket, + IN UINT32 command, + IN UINT32 data + ); + +typedef +UINT64 +(EFIAPI *BIOS_2_VCODE_MAILBOX_WRITE) ( + IN UINT8 socket, + IN UINT32 command, + IN UINT32 data + ); + +typedef +VOID +(EFIAPI *BREAK_AT_CHECK_POINT) ( + IN UINT8 majorCode, + IN UINT8 minorCode, + IN UINT16 data + ); + +typedef struct _EFI_CPU_CSR_ACCESS_PROTOCOL { + GET_CPU_CSR_ADDRESS GetCpuCsrAddress; + READ_CPU_CSR ReadCpuCsr; + WRITE_CPU_CSR WriteCpuCsr; + BIOS_2_PCODE_MAILBOX_WRITE Bios2PcodeMailBoxWrite; + BIOS_2_VCODE_MAILBOX_WRITE Bios2VcodeMailBoxWrite; + READ_MC_CPU_CSR ReadMcCpuCsr; + WRITE_MC_CPU_CSR WriteMcCpuCsr; + GET_MC_CPU_ADDR GetMcCpuCsrAddress; + UPDATE_CPU_CSR_ACCESS_VAR UpdateCpuCsrAccessVar; + READ_PCI_CSR ReadPciCsr; + WRITE_PCI_CSR WritePciCsr; + GET_PCI_CSR_ADDR GetPciCsrAddress; + BREAK_AT_CHECK_POINT BreakAtCheckpoint; +} EFI_CPU_CSR_ACCESS_PROTOCOL; + +extern EFI_GUID gEfiCpuCsrAccessGuid; + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Setup/IioUniversalData.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Setup/IioUniversalData.h new file mode 100644 index 0000000000..c051a836c9 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Setup/IioUniversalData.h @@ -0,0 +1,187 @@ +/** @file + +Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _IIO_UNIVERSAL_DATA_ +#define _IIO_UNIVERSAL_DATA_ + +#define IIO_UNIVERSAL_DATA_GUID { 0x7FF396A1, 0xEE7D, 0x431E, { 0xBA, 0x53, 0x8F, 0xCA, 0x12, 0x7C, 0x44, 0xC0 } } +#include "SysHost.h" +#include "UncoreCommonIncludes.h" +#include + +//--------------------------------------------------------------------------------------// +// Structure definitions for Universal Data Store (UDS) +//--------------------------------------------------------------------------------------// +#define UINT64 unsigned long long + +#pragma pack(1) + + +typedef struct { + UINT8 Valid; // TRUE, if the link is valid (i.e reached normal operation) + UINT8 PeerSocId; // Socket ID + UINT8 PeerSocType; // Socket Type (0 - CPU; 1 - IIO) + UINT8 PeerPort; // Port of the peer socket +}QPI_PEER_DATA; + +typedef struct { + UINT8 Valid; + UINT8 SocketFirstBus; + UINT8 SocketLastBus; + UINT8 segmentSocket; + UINT8 PcieSegment; + UINT64_STRUCT SegMmcfgBase; + UINT8 stackPresentBitmap; + UINT8 StackBus[MAX_IIO_STACK]; + UINT8 M2PciePresentBitmap; + UINT8 TotM3Kti; + UINT8 TotCha; + UINT32 ChaList; + UINT32 SocId; + QPI_PEER_DATA PeerInfo[MAX_KTI_PORTS]; // QPI LEP info +} QPI_CPU_DATA; + +typedef struct { + UINT8 Valid; + UINT8 SocId; + QPI_PEER_DATA PeerInfo[MAX_SOCKET]; // QPI LEP info +} QPI_IIO_DATA; + +typedef struct { + IIO_PORT_INFO PortInfo[NUMBER_PORTS_PER_SOCKET]; +} IIO_DMI_PCIE_INFO; + +typedef struct _STACK_RES { + UINT8 Personality; + UINT8 BusBase; + UINT8 BusLimit; + UINT16 PciResourceIoBase; + UINT16 PciResourceIoLimit; + UINT32 IoApicBase; + UINT32 IoApicLimit; + UINT32 PciResourceMem32Base; + UINT32 PciResourceMem32Limit; + UINT64 PciResourceMem64Base; + UINT64 PciResourceMem64Limit; + UINT32 VtdBarAddress; +} STACK_RES; + +typedef struct { + UINT8 Valid; + UINT8 SocketID; // Socket ID of the IIO (0..3) + UINT8 BusBase; + UINT8 BusLimit; + UINT16 PciResourceIoBase; + UINT16 PciResourceIoLimit; + UINT32 IoApicBase; + UINT32 IoApicLimit; + UINT32 PciResourceMem32Base; + UINT32 PciResourceMem32Limit; + UINT64 PciResourceMem64Base; + UINT64 PciResourceMem64Limit; + STACK_RES StackRes[MAX_IIO_STACK]; + UINT32 RcBaseAddress; + IIO_DMI_PCIE_INFO PcieInfo; + UINT8 DmaDeviceCount; +} IIO_RESOURCE_INSTANCE; + +typedef struct { + UINT16 PlatGlobalIoBase; // Global IO Base + UINT16 PlatGlobalIoLimit; // Global IO Limit + UINT32 PlatGlobalMmiolBase; // Global Mmiol base + UINT32 PlatGlobalMmiolLimit; // Global Mmiol limit + UINT64 PlatGlobalMmiohBase; // Global Mmioh Base [43:0] + UINT64 PlatGlobalMmiohLimit; // Global Mmioh Limit [43:0] + QPI_CPU_DATA CpuQpiInfo[MAX_SOCKET]; // QPI related info per CPU + QPI_IIO_DATA IioQpiInfo[MAX_SOCKET]; // QPI related info per IIO + UINT32 MemTsegSize; + UINT32 MemIedSize; + UINT64 PciExpressBase; + UINT32 PciExpressSize; + UINT32 MemTolm; + IIO_RESOURCE_INSTANCE IIO_resource[MAX_SOCKET]; + UINT8 numofIIO; + UINT8 MaxBusNumber; + UINT32 packageBspApicID[MAX_SOCKET]; // This data array is valid only for SBSP, not for non-SBSP CPUs. for CpuSv + UINT8 EVMode; + UINT8 Pci64BitResourceAllocation; + UINT8 SkuPersonality[MAX_SOCKET]; + UINT8 VMDStackEnable[MaxIIO][MAX_IIO_STACK]; + UINT16 IoGranularity; + UINT32 MmiolGranularity; + UINT64_STRUCT MmiohGranularity; + UINT8 RemoteRequestThreshold; + UINT64 Reserved; + BOOLEAN Simics; // TRUE - Simics Environtment; FALSE - H\w +} PLATFORM_DATA; + +typedef struct { + UINT8 CurrentCsiLinkSpeed;// Current programmed CSI Link speed (Slow/Full speed mode) + UINT8 CurrentCsiLinkFrequency; // Current requested CSI Link frequency (in GT) + UINT32 OutKtiPerLinkL1En[MAX_SOCKET]; // output kti link enabled status for PM + UINT8 IsocEnable; + UINT32 meRequestedSize; // Size of the memory range requested by ME FW, in MB + UINT8 DmiVc1; + UINT8 DmiVcm; + UINT32 CpuPCPSInfo; + UINT8 MinimumCpuStepping; + UINT8 LtsxEnable; + UINT8 MctpEn; + UINT8 cpuType; + UINT8 cpuSubType; + UINT8 SystemRasType; + UINT8 numCpus; // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC + UINT32 FusedCores[MAX_SOCKET]; ///< Fused Core Mask in the package + UINT32 ActiveCores[MAX_SOCKET];// Current actived core Mask in the package + UINT8 MaxCoreToBusRatio[MAX_SOCKET]; // Package Max Non-turbo Ratio (per socket). + UINT8 MinCoreToBusRatio[MAX_SOCKET]; // Package Maximum Efficiency Ratio (per socket). + UINT8 CurrentCoreToBusRatio; // Current system Core to Bus Ratio + UINT32 IntelSpeedSelectCapable; // ISS Capable (system level) Bit[7:0] and current Config TDP Level Bit[15:8] + UINT32 IssConfigTdpLevelInfo; // get B2P CONFIG_TDP_GET_LEVELS_INFO + UINT32 IssConfigTdpTdpInfo[MAX_SOCKET][CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_TDP_INFO + UINT32 IssConfigTdpPowerInfo[MAX_SOCKET][CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_POWER_INFO + UINT8 IssConfigTdpCoreCount[MAX_SOCKET][CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_CORE_COUNT + UINT8 PbfCapable; // PBF Capable (Prioritized Base Frequency) + UINT64 PbfHighPriCoreMap[MAX_SOCKET]; // PBF High Priority Cores Bitmap + UINT8 PbfP1HighRatio[MAX_SOCKET]; // PBF P1_High Ratio + UINT8 PbfP1LowRatio[MAX_SOCKET]; // PBF P1_Low Ratio + UINT32 socketPresentBitMap; // bitmap of sockets with CPUs present detected by QPI RC + UINT32 FpgaPresentBitMap; // bitmap of NID w/ fpga present detected by QPI RC + UINT16 tolmLimit; + UINT32 tohmLimit; + UINT32 mmCfgBase; + UINT32 RcVersion; + UINT8 DdrXoverMode; // DDR 2.2 Mode + // For RAS + UINT8 bootMode; + UINT8 OutClusterOnDieEn; // Whether RC enabled COD support + UINT8 OutSncEn; + UINT8 OutNumOfCluster; + UINT8 imcEnabled[MAX_SOCKET][MAX_IMC]; + UINT8 numChPerMC; + UINT8 maxCh; + UINT8 maxIMC; + UINT16 LlcSizeReg; + UINT8 chEnabled[MAX_SOCKET][MAX_CH]; + UINT8 mcId[MAX_SOCKET][MAX_CH]; + UINT8 memNode[MC_MAX_NODE]; + UINT8 IoDcMode; + UINT8 CpuAccSupport; + UINT8 SmbusErrorRecovery; + UINT8 MonitorMwaitEnabled; + UINT8 AepDimmPresent; + UINT32 VolMemMode; +} SYSTEM_STATUS; + +typedef struct { + PLATFORM_DATA PlatformData; + SYSTEM_STATUS SystemStatus; + UINT32 OemValue; +} IIO_UDS; +#pragma pack() + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/CpuHost.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/CpuHost.h new file mode 100644 index 0000000000..c297389061 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/CpuHost.h @@ -0,0 +1,255 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef cpuhost_h +#define cpuhost_h +#include "PlatformHost.h" +#include "DataTypes.h" +#include "SysHostChipCommon.h" + +#define inline __inline + +// +// CPU ExtFamily/Family/Model bit[19:4] of cpuid(1)_eax +// +#ifndef CPU_FAMILY_HSX +#define CPU_FAMILY_HSX 0x306F // Haswell CPU +#endif +#ifndef CPU_FAMILY_SKX +#define CPU_FAMILY_SKX 0x5065 // Skylake CPU +#endif +#ifndef CPU_FAMILY_ICX +#define CPU_FAMILY_ICX 0x606a // IceLake CPU +#endif +#ifndef CPU_FAMILY_KNH +#define CPU_FAMILY_KNH 0x706F // KnightsHill CPU +#endif + + +//typedef INT32 CPU_STATUS; // this causes MiniBIOS build failure +typedef int CPU_STATUS; +#define CPU_SUCCESS 0 +#define CPU_FAILURE -1 + + +// +// Reset types needed post execution +// +#define POST_RESET_NO_RESET 0x0 +#define POST_RESET_WARM 0x2 // bit1 +#define POST_RESET_POWERGOOD 0x4 // bit2 +#define POST_RESET_AMI 0x8 // bit3 + +// +// Max reservable TOR entries defines +// +#define MAX_TOR_ENTRIES_ISOC 15 +#define MAX_TOR_ENTRIES_NORMAL 17 + +// +// Error Code used for LogError() +// +#define ERROR_CPU_BIST 0xC0 + #define ERROR_CPU_BIST_MINOR_SOME_SOCKET 0x01 + #define ERROR_CPU_BIST_MINOR_SOME_BISTRESULTMASK 0x02 + #define ERROR_CPU_BIST_MINOR_ALL 0x03 + +// +// Error Codes used for LogError() and LogWarning() +// +#define WARN_CPU_BIST 0xC0 +#define WARN_CPU_BIST_MINOR_LOWER_TILE_RANGE 0x01 +#define WARN_CPU_BIST_MINOR_MIDDLE_TILE_RANGE 0x02 +#define WARN_CPU_BIST_MINOR_UPPER_TILE_RANGE 0x03 +#define WARN_CPU_BIST_MINOR_ALL 0x04 + + +// +// MSR definitions +// +#ifndef MSR_IA32_PLATFORM_ID +#define MSR_IA32_PLATFORM_ID 0x0017 +#endif +#ifndef MSR_APIC_BASE +#define MSR_APIC_BASE 0x001B +#endif +#ifndef MSR_EBC_FREQUENCY_ID +#define MSR_EBC_FREQUENCY_ID 0x002C +#endif +#ifndef MSR_CORE_THREAD_COUNT +#define MSR_CORE_THREAD_COUNT 0x0035 +#endif +#ifndef MSR_SOCKET_ID +#define MSR_SOCKET_ID 0x0039 +#endif +#ifndef MSR_IA32_FEATURE_CONTROL +#define MSR_IA32_FEATURE_CONTROL 0x003A +#endif +#ifndef VIRTUAL_MSR_MCA_ON_NON_NEW_CACHABLE_MMIO_EN_ADDR +#define VIRTUAL_MSR_MCA_ON_NON_NEW_CACHABLE_MMIO_EN_ADDR 0x61 +#endif +#ifndef MCAONNONNEMCACHEABLEMMIO_BIT +#define MCAONNONNEMCACHEABLEMMIO_BIT 0x1 +#endif +#ifndef MSR_IA32_BIOS_UPDT_TRIG +#define MSR_IA32_BIOS_UPDT_TRIG 0x0079 +#endif +#ifndef MSR_TRACE_HUB_STH_ACPIBAR_BASE +#define MSR_TRACE_HUB_STH_ACPIBAR_BASE 0x00000080 +#define B_MSR_TRACE_HUB_STH_ACPIBAR_BASE_LOCK BIT0 +#define V_MSR_TRACE_HUB_STH_ACPIBAR_BASE_MASK 0x0003FFFF +#endif +#ifndef PCH_TRACE_HUB_FW_BASE_ADDRESS +#define PCH_TRACE_HUB_FW_BASE_ADDRESS 0xFE0C0000 ///< TraceHub FW MMIO base address +#endif +#ifndef MSR_IA32_BIOS_SIGN_ID +#define MSR_IA32_BIOS_SIGN_ID 0x008B +#endif +#ifndef MSR_PLATFORM_INFO +#define MSR_PLATFORM_INFO 0x00CE +#endif +#ifndef MSR_PMG_CST_CONFIG_CONTROL +#define MSR_PMG_CST_CONFIG_CONTROL 0x00E2 +#endif +#ifndef MSR_PMG_IO_CAPTURE_BASE +#define MSR_PMG_IO_CAPTURE_BASE 0x0E4 +#endif +#ifndef MSR_MCG_CONTAIN +#define MSR_MCG_CONTAIN 0x178 +#define B_MSR_MCG_CONTAIN_PE BIT0 +#endif +#ifndef MSR_IA32_MCG_CAP +#define MSR_IA32_MCG_CAP 0x179 +#define B_MSR_MCG_CAP_GCM BIT24 +#endif +#ifndef MSR_CLOCK_FLEX_MAX +#define MSR_CLOCK_FLEX_MAX 0x0194 +#endif +#ifndef MSR_IA32_PERF_STS +#define MSR_IA32_PERF_STS 0x0198 +#endif +#ifndef MSR_IA32_PERF_CTL +#define MSR_IA32_PERF_CTL 0x0199 +#endif +#ifndef MSR_IA32_MISC_ENABLES +#define MSR_IA32_MISC_ENABLES 0x01A0 +#endif +#ifndef IA32_MISC_ENABLE +#define IA32_MISC_ENABLE 0x01A0 +#endif +#ifndef FAST_STRING_ENABLE_BIT +#define FAST_STRING_ENABLE_BIT 0x1 +#endif +#ifndef MSR_MISC_PWR_MGMT +#define MSR_MISC_PWR_MGMT 0x01AA +#endif +#ifndef MSR_TURBO_POWER_CURRENT_LIMIT +#define MSR_TURBO_POWER_CURRENT_LIMIT 0x1AC +#endif +#ifndef MSR_TURBO_RATIO_LIMIT +#define MSR_TURBO_RATIO_LIMIT 0x01AD +#endif +#ifndef MSR_POWER_CTRL +#define MSR_POWER_CTRL 0x01FC +#endif +#ifndef MSR_NO_EVICT_MODE +#define MSR_NO_EVICT_MODE 0x02E0 +#endif +#ifndef MSR_IA32_MC7_CTL +#define MSR_IA32_MC7_CTL 0x041C +#endif +#ifndef MSR_IA32_MC8_MISC2 +#define MSR_IA32_MC8_MISC2 0x0288 +#endif +#ifndef MSR_PCIEXBAR +#define MSR_PCIEXBAR 0x0300 +#endif +#ifndef MSR_PPIN_CTL +#define MSR_PPIN_CTL 0x004E +#endif +#ifndef MSR_PPIN +#define MSR_PPIN 0x004F +#endif +#ifndef MSR_MC_CTL +#define MSR_MC_CTL 0x0434 +#endif +#define MSR_UNCORE_FREQ 0x0620 + +#define MSR_UPI0_MC_STS 0x0415 +#define MSR_UPI1_MC_STS 0x0431 +#define MSR_UPI2_MC_STS 0x044d + +#ifndef MTRR_PHYS_BASE_0 +#define MTRR_PHYS_BASE_0 0x0200 +#define MTRR_PHYS_MASK_0 0x0201 +#define MTRR_PHYS_BASE_1 0x0202 +#define MTRR_PHYS_MASK_1 0x0203 +#define MTRR_PHYS_BASE_2 0x0204 +#define MTRR_PHYS_MASK_2 0x0205 +#define MTRR_PHYS_BASE_3 0x0206 +#define MTRR_PHYS_MASK_3 0x0207 +#define MTRR_PHYS_BASE_4 0x0208 +#define MTRR_PHYS_MASK_4 0x0209 +#define MTRR_PHYS_BASE_5 0x020A +#define MTRR_PHYS_MASK_5 0x020B +#define MTRR_PHYS_BASE_6 0x020C +#define MTRR_PHYS_MASK_6 0x020D +#define MTRR_PHYS_BASE_7 0x020E +#define MTRR_PHYS_MASK_7 0x020F +#define MTRR_FIX_64K_00000 0x0250 +#define MTRR_FIX_16K_80000 0x0258 +#define MTRR_FIX_16K_A0000 0x0259 +#define MTRR_FIX_4K_C0000 0x0268 +#define MTRR_FIX_4K_C8000 0x0269 +#define MTRR_FIX_4K_D0000 0x026A +#define MTRR_FIX_4K_D8000 0x026B +#define MTRR_FIX_4K_E0000 0x026C +#define MTRR_FIX_4K_E8000 0x026D +#define MTRR_FIX_4K_F0000 0x026E +#define MTRR_FIX_4K_F8000 0x026F +#define MTRR_DEF_TYPE 0x02FF + +#define MTRR_MEMORY_TYPE_UC 0x00 +#define MTRR_MEMORY_TYPE_WC 0x01 +#define MTRR_MEMORY_TYPE_WT 0x04 +#define MTRR_MEMORY_TYPE_WP 0x05 +#define MTRR_MEMORY_TYPE_WB 0x06 + +#define MTRR_DEF_TYPE_E 0x0800 +#define MTRR_DEF_TYPE_FE 0x0400 +#define MTRR_PHYS_MASK_VALID 0x0800 +#endif // MTRR_PHYS_BASE_0 + +#define CONFIG_TDP_MAX_LEVEL 5 + +// +// Memory-mapped APIC Offsets +// +#define APIC_LOCAL_APIC_ID 0x020 +#define APIC_ICR_LO 0x300 +#define APIC_ICR_HI 0x310 +#define APIC_TMR_INITIAL_CNT 0x380 +#define APIC_TMR_CURRENT_CNT 0x390 + +// +// APIC Timer runs at 133MHz and by default decrements +// the current count register at once per two clocks. +// t = time in milliseconds +// c = APIC Timer Initial Value +// c = (t * 10^(-6) sec) * (133 * 10^6 count/sec) * (1/2 clocks) +// Notice seconds and exponents cancel out leaving count value +// c = (t * 133 / 2) +// +#define APIC_TMR_1US (1 * 133 / 2) +#define APIC_TMR_10US (10 * 133 / 2) +#define APIC_TMR_20US (20 * 133 / 2) +#define APIC_TMR_100US (100 * 133 / 2) +#define APIC_TMR_200US (200 * 133 / 2) +#define APIC_TMR_10MS (10 * 1000 * 133 / 2) + + +#endif // cpuhost_h diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/CsrToPcieAddress.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/CsrToPcieAddress.h new file mode 100644 index 0000000000..04d0d4d790 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/CsrToPcieAddress.h @@ -0,0 +1,42 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __CSR_TO_PCIE_ADDRESS_H__ +#define __CSR_TO_PCIE_ADDRESS_H__ + + +#include + +////////////////////////////////////////////////////////////////////////// +// +// Common Silicon Address Library +// This Lib provide the way use platform Library instance +// +////////////////////////////////////////////////////////////////////////// + + +/** + This Lib Convert the logical address (CSR type, e.g. CPU ID, Boxtype, Box instance etc.) into physical address + + @param[in] Global Global pointer + @param[in] Virtual Virtual address + @param[in] Address A pointer of the address of the USRA Address Structure + @param[out] AlignedAddress A pointer of aligned address converted from USRA address + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +UINTN +EFIAPI +CsrGetPcieAlignAddress ( + IN VOID *Global, + IN BOOLEAN Virtual, + IN USRA_ADDRESS *Address, + OUT UINTN *AlignedAddress + ); + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/DataTypes.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/DataTypes.h new file mode 100644 index 0000000000..493408b256 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/DataTypes.h @@ -0,0 +1,111 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _datatypes_h +#define _datatypes_h + +typedef unsigned char BOOLEAN; +//typedef signed char INT8; // SKX TODO: All string/ASCII/ANSI character based functions need to be ported to use CHAR type due +// to GCC difference. After that porting occurs, then INT8 should be defined as signed type. MS compiler treats char as signed value. +// GNU compiler treats char as unsigned value. This creates havoc when trying to make code compatible with runtime libraries. So... +// henceforth all strings usage will be of type CHAR and not INT8. +typedef char CHAR; +#if defined(__GNUC__) && !defined(MINIBIOS_BUILD) +typedef signed char INT8; +#else +typedef char INT8; +#endif +typedef char CHAR8; +typedef unsigned char UINT8; +typedef short INT16; +typedef unsigned short UINT16; +typedef int INT32; +typedef unsigned int UINT32; +typedef unsigned int MMRC_STATUS; +#define MMRC_SUCCESS 0 +#define MMRC_FAILURE 0xFFFFFFFF +#ifndef CONST +#define CONST const +#endif +#ifndef IN +#define IN +#endif +#ifndef OUT +#define OUT +#endif +#ifndef NULL +#define NULL ((VOID *) 0) +#endif +#ifdef MINIBIOS_BUILD +typedef unsigned long long UINT64; +#endif +typedef unsigned char UCHAR8; +typedef unsigned short CHAR16; +//typedef signed long long SINT64; +//typedef signed long SINT32; +//typedef signed short SINT16; +//typedef signed char SINT8; +#define SINT8 INT8 +#define SINT16 INT16 +#define SINT32 INT32 + +#define CONST const +#define STATIC static +#define VOID void +#define VOLATILE volatile + +#ifndef TRUE +#define TRUE ((BOOLEAN) 1 == 1) +#endif +#ifndef FALSE +#define FALSE ((BOOLEAN) 0 == 1) +#endif + +typedef UINT64 UINTX; + +typedef struct u64_struct { + UINT32 lo; + UINT32 hi; +} UINT64_STRUCT, *PUINT64_STRUCT; + +typedef struct u128_struct { + UINT32 one; + UINT32 two; + UINT32 three; + UINT32 four; +} UINT128; + +typedef struct { + UINT32 Data1; + UINT16 Data2; + UINT16 Data3; + UINT8 Data4[8]; +} GUID_RC; + +#ifndef NT32_BUILD +#if defined (RC_SIM) || defined (MINIBIOS_BUILD) +typedef GUID_RC EFI_GUID; +#endif // #if defined (RC_SIM) || defined (MINIBIOS_BUILD) + +#ifdef MINIBIOS_BUILD +typedef INT32 INTN; +typedef UINT32 UINTN; +typedef UINTN RETURN_STATUS; +#define MAX_BIT (1 << ((sizeof (UINTN) << 3) - 1)) +#define ENCODE_ERROR(StatusCode) ((RETURN_STATUS)(MAX_BIT | (StatusCode))) +#define RETURN_SUCCESS 0 +#define RETURN_UNSUPPORTED ENCODE_ERROR (3) +#define EFIAPI +#define PcdUsraSupportS3 FALSE + +#endif // #ifdef MINIBIOS_BUILD +#endif // #ifndef NT32_BUILD + + +#define MAX_STRING_LENGTH 0x100 + +#endif // _datatypes_h diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MemHost.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MemHost.h new file mode 100644 index 0000000000..a833a6dc57 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MemHost.h @@ -0,0 +1,328 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _memhost_h +#define _memhost_h +#include "DataTypes.h" +#include "PlatformHost.h" +#include "SysRegs.h" +#include "MemRegs.h" +#include "MemDefaults.h" +#include "MrcCommonTypes.h" +#include "MemHostChipCommon.h" +#include "KtiSi.h" + +#define MAX_DIMMTABLEINDEX (MAX_CH * MAX_DIMM) + + +#define MAXFIELDVAL(bitfield) (bitfield = 0xffffffff) + +//EFI_GUID definition locations for different BDAT/BSSA cases + +#include + +// Debug Build code +// These should be disabled for all normal builds and only enable on demand for debugging +//#define DEBUG_TURNAROUNDS 1 +#define DEBUG_PERFORMANCE_STATS 1 +//#define DEBUG_RDRAND 1 +//#define DEBUG_SENSEAMP 1 + +#ifdef DEBUG_PERFORMANCE_STATS +#define MAX_NOZONE 20 +#endif // DEBUG_PERFORMANCE_STATS + +#define PGT_TIMER_ENABLE 1 +#define PGT_TIMER_DISABLE 0 + +// +// DDR3 frequencies 800 - 2666 +// DDR4 frequencies 1333 - 4200 +// +#define MAX_SUP_FREQ 28 // 26 frequencies are supported (800, 1067, 1333, 1600, 1867, 2133, 2400, 2666, 2933, + // 3200, 3400, 3467, 3600, 3733, 3800, 4000, 4200, 4266, 4400) + + + + +/// +/// External signal names +/// +typedef enum { + RAS_N, CAS_N, WE_N, + BA0, BA1, BA2, + A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, + CS0_N, CS1_N, CS2_N, CS3_N, CS4_N, CS5_N, CS6_N, CS7_N, CS8_N, CS9_N, + CKE0, CKE1, CKE2, CKE3, CKE4, CKE5, + ODT0, ODT1, ODT2, ODT3, ODT4, ODT5, + PAR, ALERT_N, + BG0, BG1, ACT_N, C0, C1, C2, + CK0, CK1, CK2, CK3, CK4, CK5, + FNV_GOOD_PARITY, DESELECT, PRECHARGE, GNT, // these are actually commands as opposed to signals + gsmCsnDelim = INT32_MAX +} GSM_CSN; + +typedef struct { + INT16 left; + INT16 right; +} SIGNAL_EYE; + +#define MAX_PHASE 2 // MAX_PHASE + +// +// Common Core dummy defines +// + +#ifndef MAX_MC_CH +#define MAX_MC_CH 2 // Max channels per MC +#endif +#ifndef MAX_CLUSTERS +#define MAX_CLUSTERS 1 // Maximum number of clusters supported +#endif + +#ifndef MAX_EDC +#define MAX_EDC 1 // Maximum number of EDC supported +#endif + +#define CATCHALL_TIMEOUT 100000 // 100 ms + +#pragma pack(push, 1) + +extern const UINT16 rankSize[MAX_TECH]; ///< Rank size in 64 MB units +extern const UINT16 rankSizeDDR4[MAX_TECH]; ///< Rank size in 64 MB units + + +#define ALL_DRAMS 0xFF // Indicates to write to all DRAMs when in PDA mode +#define ALL_DATABUFFERS 0xFF // Indicates to write to all Buffers in PBA Mode + +typedef enum { +INVALID_BUS, +SMBUS, +EMRS, +CPGC, +SAD, +} BUS_TYPE; + +#ifdef SERIAL_DBG_MSG +#define MemDebugPrint(dbgInfo) debugPrintMem dbgInfo +#define MspDebugPrint(dbgInfo) debugPrintMsp dbgInfo +#define MmrcDebugPrint(dbgInfo) +#define OutputExtendedCheckpoint(dbgInfo) +#else +#define MemDebugPrint(dbgInfo) +#define MspDebugPrint(dbgInfo) +#define MmrcDebugPrint(dbgInfo) +#define OutputExtendedCheckpoint(dbgInfo) OutputCheckpoint dbgInfo +#endif + + +typedef enum +{ + MRC_PF_NULL, // All policy flags turned off. + MRC_PF_COLD = BIT0, // Execute MRC function on cold reset. + MRC_PF_FAST = BIT1, // Execute MRC function on cold reset when S3 data is present. + MRC_PF_WARM = BIT2, // Execute MRC function on warm reset. + MRC_PF_S3 = BIT3, // Execute MRC function on S3 exit. + //MRC_PF_FULL_MRC = BIT4, // Execute MRC function when in Full MRC mode. + //MRC_PF_MINI_MRC = BIT5, // Execute MRC function when in Mini-MRC mode. + MRC_PF_ALL = 0xF // All policy flags turned off. +} PFSelectorType; + +typedef enum +{ + MRC_MP_NULL, // All policy flags turned off + MRC_MP_SERIAL = BIT0, // Execute function when in serial mode + MRC_MP_PARALLEL = BIT1, // Execute function when in parallel mode + MRC_MP_LOOP = BIT2, // Execute function for each socket when in serial mode + MRC_MP_BOTH = MRC_MP_SERIAL | MRC_MP_PARALLEL, // Execute function in both modes + MRC_MP_BOTH_LOOP = MRC_MP_SERIAL | MRC_MP_PARALLEL | MRC_MP_LOOP, // Execute function in both modes and loop +} MPSelectorType; + +// +// TRR defines +// +#define PTRR_MODE BIT0 +#define TRR_MODE_A BIT1 +#define TRR_IMMUNE BIT2 +#ifdef TRR_MODE_B_SUPPORT +#define TRR_MODE_B BIT3 +#endif //TRR_MODE_B_SUPPORT + +typedef struct { + UINT8 stackPresentBitmap[MAX_SOCKET]; ///< bitmap of present stacks per socket + UINT8 StackBus[MAX_SOCKET][MAX_IIO_STACK]; ///< Bus of each stack + UINT8 SocketFirstBus[MAX_SOCKET]; + UINT8 Socket10nmUboxBus0[MAX_SOCKET]; //10nm CPU use only + UINT8 SocketLastBus[MAX_SOCKET]; + UINT8 segmentSocket[MAX_SOCKET]; + UINT8 cpuType; + UINT8 stepping; + UINT32 socketPresentBitMap; + UINT32 FpgaPresentBitMap; + UINT32 mmCfgBase; + UINT8 maxCh; + UINT8 maxIMC; + UINT8 numChPerMC; + UINT8 imcEnabled[MAX_SOCKET][MAX_IMC]; + UINT8 mcId[MAX_SOCKET][MAX_CH]; + CPU_CSR_ACCESS_VAR_CHIP ///< Chip hook to enable CPU_CSR_ACCESS_VAR fields +} CPU_CSR_ACCESS_VAR; + +#pragma pack(pop) + +/// +/// (MPT_MT - MemeoryPowerTraining_MarginType)param type for power training steps +/// +typedef enum { + GetMargin = 0, + TerMargin = 1, + BerMargin = 2 +} MPT_MT; + +/// +/// (MPT_PT - MemeoryPowerTraining_ParamType)param type for power training steps +/// +typedef enum { + PerChPerByte = 0, + PerRank = 1, + PerStrobe = 2, + PerCh = 3, + PerMC = 4 +} MPT_PT; + +/// +/// (MPT_P - MemeoryPowerTraining_Param)param for power training steps +/// +typedef enum { + traindramron = 0, + trainmcodt = 1, + trainnontgtodt = 2, + trainrttwr = 3, + trainmcron = 4, + traintxeq = 5, + trainimode = 6, + trainctle = 7, + traintcocomp = 8, + traindramrxeq = 9, +} MPT_P; + +#define IMC0 0 +#define IMC1 1 + +// +// PPR Status +// +#define PPR_STS_SUCCESS 0x00 +#define PPR_STS_ADDR_VALID 0x01 +#define PPR_STS_FAILED 0x02 + +#define DRAM_UNKNOWN 0xFF + +#pragma pack(push, 1) +// +// ----------------------------------------------------------------------------- + +// +// NVRAM structures for S3 state +// + +#define MAX_CMD_CSR 16 +#define MAX_SIDE 2 + +// +// ----------------------------------------------------------------------------- +// +// ddrChannelSetup STRUCT 4t ; Channel setup structure declaration +// +// enabled BYTE ? ; Channel enable switch: +// ; 0 = channel disabled +// ; 1 = channel enabled +// +// options BYTE ? ; Bit-mapped options: +// +// numDimmSlots BYTE ? ; Number of Dimm slots per channel +// ; Valid options are 1, 2 or 3 +// ; MAX_DIMM is defined in mrcplatform.h. This option can be no larger than MAX_DIMM. +// ; It overrides MAX_DIMM when it is smaller. +// +// ddrChannelSetup ENDS +// +// ----------------------------------------------------------------------------- +// + +// +// ----------------------------------------------------------------------------- +// +// Node bit-mapped options +// +// ddrSocketSetup STRUCT 4t ; Socket setup structure declaration +// +// enabled BYTE ? ; imc enable switch: +// ; 0 = imc disabled +// ; 1 = imc enabled +// +// options BYTE ? ; Bit-mapped options per socket: +// +// vrefDefaultValue BYTE ? ; Default DCP value per socket for DIMM Vref = Vddq/2 +// +// vrefDcp smbDevice <> ; Defines override of DCP SMBus device and address +// ; compId = DCP_ISL9072X or DCP_AD5247 +// ; strapAddress +// ; busSegment +// +// ddrSocketSetup ENDS +// +// ----------------------------------------------------------------------------- +// + +/// +/// PPR DRAM Address +/// +typedef struct { + UINT8 dimm; + UINT8 rank; + UINT8 subRank; + UINT32 dramMask; + UINT8 bank; + UINT32 row; +} PPR_ADDR; + +// HIGH_ADDR_EN enables extention of the MMIO hole to force memory to high address region +#define HIGH_ADDR_EN BIT0 +#define CR_MIXED_SKU BIT2 //used to enable(1)- halt on mixed sku discovery and disable(0) - warn on mixed sku discovery + +//#pragma pack(pop) + +/// +/// Sub-boot state internal to MRC (8-15 are definable). The 2 main boot types and paths through QPIRC/MRC - NormalBoot and S3Resume. +/// Within NormalBoot and S3Resume, the sub-boot type can be cold, warm, fast warm, fast cold, and ADR resume. These are populated +/// at the beginning of MRC so they are not applicable for QPIRC. +/// +typedef enum SubBootMode +{ + ColdBoot = 8, // Normal path through MRC with full mem detection, init, training, etc. + WarmBoot = 9, // Warm boot path through MRC. Some functionality can be skipped for speed. + WarmBootFast = 10, // Fast warm boot path uses the NVRAM structure to skip as much MRC + // code as possible to try to get through MRC fast. Should be as close + // as possible to the S3 flow. + ColdBootFast = 11, // Fast cold boot path uses the NVRAM structure to skip as much MRC + // code as possible on a cold boot. + AdrResume = 12, // ADR flow can skip most of MRC (i.e. take the S3 path) for DIMMs that + // are in self-refresh. But the DIMMs that are not in self-refresh + // must go through more of MRC. + Reserved13 = 13 +} SubBootMode; + +#define MAX_ADV_MT_LOG 16 + +#define MEM_CHIP_POLICY_DEF(x) host->var.mem.memChipPolicy.x +#define MEM_CHIP_POLICY_VALUE(host, x) host->var.mem.memChipPolicy.x +#define CHIP_FUNC_CALL(host, x) x + +#pragma pack(pop) + +#endif // _memhost_h diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MemHostChipCommon.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MemHostChipCommon.h new file mode 100644 index 0000000000..87f1e2d15c --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MemHostChipCommon.h @@ -0,0 +1,122 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _memhostchipcommon_h +#define _memhostchipcommon_h + +#include "SysHostChipCommon.h" + +#define NODE_TO_SKT(node) (node / MAX_IMC) +#define SKT_TO_NODE(socket, mc) ((socket << 1) | (mc & BIT0)) +#define NODE_TO_MC(node) (node % MAX_IMC) +#define SKTMC_TO_NODE(socket, mc) ((socket * MAX_IMC) | (mc % MAX_IMC)) +#define NODECH_TO_SKTCH(node, ch) (((node % MAX_IMC)*MAX_MC_CH) + ch) + +// + +// +//MAX_CHANNELS and DYNVAR_MAX were previously defined in MmrcProjectDefinitionsGenerated.h, but +// now are here and must be manually updated as needed depending on MMRC tool execution (they have been +// removed from automatic generation by the tool) +// +// Channels +// +#define MAX_CHANNELS 6 + +#define DYNVAR_MAX 51 + +#define MAX_IMC 2 + +#define MAX_MC_CH 3 // Max channels per MC +#define MAX_CH ((MAX_IMC)*(MAX_MC_CH)) // Max channels per socket +#define MC_MAX_NODE (MAX_SOCKET * MAX_IMC) // Max number of memory nodes +#define MAX_DIMM 2 // Max DIMM per channel + +#define MAX_DIMM3 3 // Max DIMM per channel +#define MAX_TECH 19 // Number of entries in DRAM technology table + +#define MAX_RIR 4 // Number of Rank Interleave Register rules for DDR +#define MAX_RIR_DDRT 4 // Number of Rank Interleave Register rules for NVMDIMM +#define MAX_RIR_WAYS 8 // Number of interleave ways for RIR for DDR +#define TAD_RULES 8 // Number of TAD rule registers +#define MAX_TAD_WAYS 3 // Number of interleave ways for TAD RULES +#define SAD_RULES 24 // Number of SAD rule registers +#define MAX_SAD_RULES 24 // Number of SAD rule registers +#define MAX_STROBE 18 // Number of strobe groups +#define MAX_SEEDS 10 // Maximum +#if QR_DIMM_SUPPORT +#define MAX_RANK_DIMM 4 // Max ranks per DIMM +#else +#define MAX_RANK_DIMM 2 // Max ranks per DIMM +#endif +#define MAX_RANK_CH 8 // Max ranks per channel +#define MAX_SPARE_RANK 2 // Max number of spare ranks in a channel +#define SPD_MODULE_PART 18 // Number of bytes of module part - DDR3 +#define SPD_MODULE_PART_DDR4 20 // Number of bytes of module part - DDR4 +#define SAD_RULES_ADDR_RANGE 4 // Max IOT rules = 4, Total address limits (lower(4) entries each) +// Ctl FUBs +#define NUM_CTL_PLATFORM_GROUPS 4 + +// SPD Defines +//----------------------------------------------------------------------------- + +#pragma pack(1) + +// +// Define the WDB line. The WDB line is like the cache line. +// +#define MRC_WDB_LINES 32 +#define MRC_WDB_LINE_SIZE 64 +#define CADB_LINES 16 +// Define in the Critical Section function on what to wait. +// +typedef enum { + DoneAndRefDrained, + Done, + Immediate +} EWaitOn; + +typedef enum { + ssOne = 0, + ssTwo, + ssThree, + ssFour, +} TSubSequencesNumber; + +#define MAX_PHASE_IN_FINE_ADJUSTMENT 64 +#pragma pack() + +#define SKX_PCKG_TYPE 4 //CMD_CTL_DELAY_H + +#define CHIP_IOGPDLY_PSECS SKX_PCKG_TYPE + +// +// Chip specific section of the struct CPU_CSR_ACCESS_VAR +// +#define CPU_CSR_ACCESS_VAR_CHIP \ + + +typedef enum { + TYPE_SCF_BAR = 0, + TYPE_PCU_BAR, + TYPE_MEM_BAR0, + TYPE_MEM_BAR1, + TYPE_MEM_BAR2, + TYPE_MEM_BAR3, + TYPE_MEM_BAR4, + TYPE_MEM_BAR5, + TYPE_MEM_BAR6, + TYPE_MEM_BAR7, + TYPE_SBREG_BAR, + TYPE_MAX_MMIO_BAR +} MMIO_BARS; + + +// Output structures based on scope +#define MAX_BITS 72 + +#endif // _memhostchipcommon_h diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MemRegs.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MemRegs.h new file mode 100644 index 0000000000..d29a5d0971 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MemRegs.h @@ -0,0 +1,13 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _memregs_h +#define _memregs_h + +#define SPD_LR_PERS_BYTES_TOTAL 15 // LR DIMM Total number of Personality Bytes + +#endif // _memregs_h diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MrcCommonTypes.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MrcCommonTypes.h new file mode 100644 index 0000000000..0f6727924f --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MrcCommonTypes.h @@ -0,0 +1,20 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _MrcCommonTypes_h_ +#define _MrcCommonTypes_h_ + +#include "DataTypes.h" + +#define INT32_MIN (0x80000000) +#ifndef INT32_MAX //INT32_MAX->Already defined +#define INT32_MAX (0x7FFFFFFF) +#endif +#define INT16_MIN (0x8000) +#define INT16_MAX (0x7FFF) + +#endif // _MrcCommonTypes_h_ diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/PcieAddress.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/PcieAddress.h new file mode 100644 index 0000000000..d9578056f6 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/PcieAddress.h @@ -0,0 +1,65 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PCIE_MMCFG_H__ +#define __PCIE_MMCFG_H__ + +#include + + +////////////////////////////////////////////////////////////////////////// +// +// PCIE MMCFG Table definition +// This table was based on PCI Firmwar Spec Rev 3.1 +// +////////////////////////////////////////////////////////////////////////// + +typedef struct + { + UINT8 Signature[4]; ///< �MCFG�. Signature For this Table + UINT32 Length; ///< Length, in bytes, include base address allocation structures. + UINT8 Revision; ///< "1" + UINT8 SegMax; ///< The Maximum number of Segments + UINT16 ValidSegMap; ///< Valid Segment Bit Map, LSB Bit0 for Seg0, bit1 for seg1 ... + UINT8 Reserved[4]; ///< Reserved +} PCIE_MMCFG_HEADER_TYPE; + +typedef struct + { + UINT32 BaseAddressL; ///< Processor-relative Base Address (Lower 32-bit) for the Enhanced Configuration Access Mechanism + UINT32 BaseAddressH; ///< Processor-relative Base Address (Upper 32-bit) for the Enhanced Configuration Access Mechanism + UINT16 Segment; ///< PCI Segment Group Number. Default is 0. + UINT8 StartBus; ///< Start PCI Bus number decoded by the host bridge + UINT8 EndBus; ///< End PCI Bus number decoded by the host bridge + UINT8 Reserved[4]; ///< Reserved +} PCIE_MMCFG_BASE_ADDRESS_TYPE; + + +typedef struct + { + PCIE_MMCFG_HEADER_TYPE Header; ///< The header of MMCFG Table + PCIE_MMCFG_BASE_ADDRESS_TYPE MmcfgBase[1]; ///< First Arrary of base address allocation structures. +} PCIE_MMCFG_TABLE_TYPE; + + +/** + This Lib is used for platfor to set platform specific Pcie MMCFG Table + + @param MmcfgTable: A pointer of the MMCFG Table structure for PCIE_MMCFG_TABLE_TYPE type. + @param NumOfSeg: Sumber of Segments in the table. + + @retval <>NULL The function completed successfully. + @retval NULL Returen Error +**/ +UINTN +EFIAPI +SetPcieSegMmcfgTable ( + IN PCIE_MMCFG_TABLE_TYPE *MmcfgTable, + IN UINT32 NumOfSeg +); + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/Printf.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/Printf.h new file mode 100644 index 0000000000..b531b711ed --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/Printf.h @@ -0,0 +1,74 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _printf_h +#define _printf_h + +#include "DataTypes.h" + +#define PRINTF_CONTROL_OUTOF_SYNC_ERR_MAJOR 0xCF +#define PRINTF_CONTROL_OUTOF_SYNC_ERR_MINOR 0x01 + +#define TAB_STOP 4 +#define LEFT_JUSTIFY 0x01 +#define PREFIX_SIGN 0x02 +#define PREFIX_BLANK 0x04 +#define COMMON_PREFIX_ZERO 0x08 +#define LONG_TYPE 0x10 + +#define INT_SIGNED 0x20 +#define COMA_TYPE 0x40 +#define LONG_LONG_TYPE 0x80 +#define TO_UPPER 0x100 + +#define CHAR_CR 0x0d +#define CHAR_LF 0x0a + +// +// ANSI Escape sequences for color +// +#define ANSI_FOREGROUND_BLACK 30 +#define ANSI_FOREGROUND_RED 31 +#define ANSI_FOREGROUND_GREEN 32 +#define ANSI_FOREGROUND_YELLOW 33 +#define ANSI_FOREGROUND_BLUE 34 +#define ANSI_FOREGROUND_MAGENTA 35 +#define ANSI_FOREGROUND_CYAN 36 +#define ANSI_FOREGROUND_WHITE 37 + +#define ANSI_BACKGROUND_BLACK 40 +#define ANSI_BACKGROUND_RED 41 +#define ANSI_BACKGROUND_GREEN 42 +#define ANSI_BACKGROUND_YELLOW 43 +#define ANSI_BACKGROUND_BLUE 44 +#define ANSI_BACKGROUND_MAGENTA 45 +#define ANSI_BACKGROUND_CYAN 46 +#define ANSI_BACKGROUND_WHITE 47 + +#define ANSI_ATTRIBUTE_OFF 0 +#define ANSI_ATTRIBUTE_BOLD 1 +#define ANSI_ATTRIBUTE_UNDERSCORE 4 +#define ANSI_ATTRIBUTE_BLINK 5 +#define ANSI_ATTRIBUTE_REVERSE 7 +#define ANSI_ATTRIBUTE_CONCEAL 8 + +#ifndef INT32_MAX +#define INT32_MAX 0x7fffffffU +#endif + +#ifndef va_start +typedef INT8 * va_list; +#define _INTSIZEOF(n) ((sizeof (n) + sizeof (UINT32) - 1) &~(sizeof (UINT32) - 1)) +#define va_start(ap, v) (ap = (va_list) & v + _INTSIZEOF (v)) +#define va_arg(ap, t) (*(t *) ((ap += _INTSIZEOF (t)) - _INTSIZEOF (t))) +#define va_end(ap) (ap = (va_list) 0) +#endif + +#define ISDIGIT(_c) (((_c) >= '0') && ((_c) <= '9')) +#define ISHEXDIGIT(_c) (((_c) >= 'a') && ((_c) <= 'f')) + +#endif // _printf_h diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/SysHost.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/SysHost.h new file mode 100644 index 0000000000..7fde63d166 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/SysHost.h @@ -0,0 +1,136 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _syshost_h +#define _syshost_h +//#define CCMRC 1 + + +#define RC_SIM_FASTCADB 0 + + + +// +// Host reset states (0-7 are definable) +// +typedef enum BootMode { + NormalBoot = 0, // Normal path through RC with full init, mem detection, init, training, etc. + // Some of these MRC specific init routines can be skipped based on MRC input params + // in addition to the sub-boot type (WarmBoot, WarmBootFast, etc). + S3Resume = 1 // S3 flow through RC. Should do the bare minimum required for S3 + // init and be optimized for speed. +} BootMode; + + +typedef struct sysHost SYSHOST, *PSYSHOST; + +#include "DataTypes.h" +#include "SysHostChipCommon.h" +#include "Printf.h" +#include "PlatformHost.h" +#include "CpuHost.h" +#include "MemHost.h" +#include "KtiHost.h" +#include "UsbDebugPort.h" + +#include "SysRegs.h" +#include "IioPlatformData.h" + +// +// ------------------------------------- +// Declarations and directives +// ------------------------------------- +// Reference Code (RC) revision in BCD format: +// [31:24] = Major revision number +// [23:16] = Minor revision number +// [15:8] = Release Candidate number +// +#define CCMRC_REVISION 0x00500000 + +#define SUCCESS 0 + +#define SDBG_MIN BIT0 +#define SDBG_MAX BIT1 +#define SDBG_TRACE BIT2 +#define SDBG_MEM_TRAIN BIT3 + SDBG_MAX +#define SDBG_TST BIT4 +#define SDBG_CPGC BIT5 +#define SDBG_RCWRITETAG BIT6 +#define SDBG_REG_ACCESS BIT6 // Displays all register accesses. +#define SDBG_MINMAX SDBG_MIN + SDBG_MAX + +#define SDBG_BUF_ENABLE 1 +#define SDBG_BUF_DISABLE 0 +#define SDBG_BUF_EN_DEFAULT SDBG_BUF_DISABLE // Default disable + +#define SDBG_PIPE_ENABLE 1 +#define SDBG_PIPE_DISABLE 0 +#define SDBG_PIPE_DEFAULT SDBG_PIPE_DISABLE + +#define SDBG_PIPE_COMPRESS_ENABLE 1 +#define SDBG_PIPE_COMPRESS_DISABLE 0 +#define SDBG_PIPE_COMPRESS_DEFAULT SDBG_PIPE_COMPRESS_DISABLE + + +// +// ----------------------------------------------------------------------------- +// Variable structures +// + +// +// Warning log +// +#define MAX_LOG 64 + +#define USB_BUF_LIMIT (4096-160) +#define USB_BUF_SIZE (USB_BUF_LIMIT + 160) + +// +// System previous boot error structure +// +#define MC_BANK_STATUS_REG 1 +#define MC_BANK_ADDRESS_REG 2 +#define MC_BANK_MISC_REG 3 + +#define MSR_LOG_VALID BIT31 +#define MSR_LOG_UC BIT29 +#define MSR_LOG_EN BIT28 + +// Bit definitions for commonSetup.options +// ; PROMOTE_WARN_EN enables warnings to be treated as fatal error +// ; PROMOTE_MRC_WARN_EN enables MRC warnings to be treated as fatal error +// ; HALT_ON_ERROR_EN enables errors to loop forever +#define PROMOTE_WARN_EN BIT0 +#define PROMOTE_MRC_WARN_EN BIT1 +#define HALT_ON_ERROR_EN BIT2 + + +// ----------------------------------------------------------------------------- +// + +// +// Handle assertions with RC_ASSERT +// +#if defined(SIM_BUILD) || defined(IA32) || defined (HEADLESS_MRC) + +#define RC_ASSERT(assertion, majorCode, minorCode) \ + if (!(assertion)) { \ + DebugPrintRc (host, 0xFF, "\n\nRC_ASSERT! %s: %u %s ", __FILE__, __LINE__, #assertion);\ + FatalError (host, majorCode, minorCode);\ + } + +#else + +#define RC_ASSERT(assertion, majorCode, minorCode) \ + if (!(assertion)) { \ + CpuCsrAccessError (host, "\n\nRC_ASSERT! %s: %u %s ", __FILE__, __LINE__, #assertion);\ + } + +#endif + + +#endif // _syshost_h diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/SysHostChipCommon.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/SysHostChipCommon.h new file mode 100644 index 0000000000..d49767573b --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/SysHostChipCommon.h @@ -0,0 +1,86 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _SYSHOST_CHIP_COMMON_H_ +#define _SYSHOST_CHIP_COMMON_H_ + +#ifndef SEGMENT_ACCESS +#define SEGMENT_ACCESS +#endif + +// +// Steppings +// +#define A0_REV 0x00 + +//TODO:Need to remove the old ones. Keep for noe to allow building +#define CPU_HSX 0 +#define CPU_IVT 1 +#define CPU_BDX 2 +#define CPU_SKX 0 + +// Defines for socketType +// +#define SOCKET_2S 0 +#define SOCKET_4S 1 +#define SOCKET_HEDT 2 + +// +// CpuPciAccess +// +#define READ_ACCESS 0 +#define WRITE_ACCESS 1 + +#pragma pack(1) + +typedef union { + struct { + UINT32 Bit0:1; + UINT32 Bit1:1; + UINT32 Bit2:1; + UINT32 Bit3:1; + UINT32 Bit4:1; + UINT32 Bit5:1; + UINT32 Bit6:1; + UINT32 Bit7:1; + UINT32 Bit8:1; + UINT32 Bit9:1; + UINT32 Bit10:1; + UINT32 Bit11:1; + UINT32 Bit12:1; + UINT32 Bit13:1; + UINT32 Bit14:1; + UINT32 Bit15:1; + UINT32 Bit16:1; + UINT32 Bit17:1; + UINT32 Bit18:1; + UINT32 Bit19:1; + UINT32 Bit20:1; + UINT32 Bit21:1; + UINT32 Bit22:1; + UINT32 Bit23:1; + UINT32 Bit24:1; + UINT32 Bit25:1; + UINT32 Bit26:1; + UINT32 Bit27:1; + UINT32 Bit28:1; + UINT32 Bit29:1; + UINT32 Bit30:1; + UINT32 Bit31:1; + } Bits; + UINT32 Data; +} DUMMY_REG; + +#pragma pack() + +// +// System previous boot error structure +// +#define MAX_PREV_BOOT_ERR_ENTRIES 15 + + +#endif // _SYSHOST_CHIP_COMMON_H_ diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/SysRegs.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/SysRegs.h new file mode 100644 index 0000000000..4ee6b7ba17 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/SysRegs.h @@ -0,0 +1,68 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _sysregs_h +#define _sysregs_h + +#include "DataTypes.h" + +#ifndef BIT0 +#define BIT0 1 +#define BIT1 (1 << 1) +#define BIT2 (1 << 2) +#define BIT3 (1 << 3) +#define BIT4 (1 << 4) +#define BIT5 (1 << 5) +#define BIT6 (1 << 6) +#define BIT7 (1 << 7) +#define BIT8 (1 << 8) +#define BIT9 (1 << 9) +#endif +#ifndef BIT10 +#define BIT10 (1 << 10) +#define BIT11 (1 << 11) +#define BIT12 (1 << 12) +#define BIT13 (1 << 13) +#define BIT14 (1 << 14) +#define BIT15 (1 << 15) +#define BIT16 (1 << 16) +#define BIT17 (1 << 17) +#define BIT18 (1 << 18) +#define BIT19 (1 << 19) +#define BIT20 (1 << 20) +#define BIT21 (1 << 21) +#define BIT22 (1 << 22) +#define BIT23 (1 << 23) +#define BIT24 (1 << 24) +#define BIT25 (1 << 25) +#define BIT26 (1 << 26) +#define BIT27 (1 << 27) +#define BIT28 (1 << 28) +#define BIT29 (1 << 29) +#define BIT30 (1 << 30) +#define BIT31 (UINT32) (1 << 31) +#endif + +#ifndef TRUE +#define TRUE ((BOOLEAN) 1 == 1) +#endif + +#ifndef FALSE +#define FALSE ((BOOLEAN) 0 == 1) +#endif + +#ifndef ABS +#define ABS(x) (((x) < 0) ? (-x) : (x)) +#endif +// +// disable compiler warning to use bit fields on unsigned short/long types +// +#ifdef _MSC_VER +#pragma warning(disable : 4214) +#endif + +#endif // _sysregs_h diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/UsbDebugPort.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/UsbDebugPort.h new file mode 100644 index 0000000000..172e794042 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Core/Include/UsbDebugPort.h @@ -0,0 +1,318 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _USB_DEBUG_PORT_INTERNAL_H +#define _USB_DEBUG_PORT_INTERNAL_H + +#include "DataTypes.h" + +#define PCI_VENDOR_ID_OFFSET 0x00 +#define PCI_DEVICE_ID_OFFSET 0x02 +#define PCI_COMMAND_OFFSET 0x04 +#define PCI_PRIMARY_STATUS_OFFSET 0x06 +#define PCI_REVISION_ID_OFFSET 0x08 +#define PCI_CLASSCODE_OFFSET 0x09 +#define PCI_SUBCLASSCODE_OFFSET 0x0A +#define PCI_BASECLASSCODE_OFFSET 0x0B // Base Class Code Register +#define PCI_CACHELINE_SIZE_OFFSET 0x0C +#define PCI_LATENCY_TIMER_OFFSET 0x0D +#define PCI_HEADER_TYPE_OFFSET 0x0E +#define PCI_BIST_OFFSET 0x0F +#define PCI_BASE_ADDRESSREG_OFFSET 0x10 +#define PCI_CARDBUS_CIS_OFFSET 0x28 +#define PCI_SVID_OFFSET 0x2C // SubSystem Vendor id +#define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C +#define PCI_SID_OFFSET 0x2E // SubSystem ID +#define PCI_SUBSYSTEM_ID_OFFSET 0x2E +#define PCI_EXPANSION_ROM_BASE 0x30 +#define PCI_CAPBILITY_POINTER_OFFSET 0x34 +#define PCI_INT_LINE_OFFSET 0x3C // Interrupt Line Register +#define PCI_INT_PIN_OFFSET 0x3D // Interrupt Pin Register +#define PCI_MAXGNT_OFFSET 0x3E // Max Grant Register +#define PCI_MAXLAT_OFFSET 0x3F // Max Latency Register + +#define PCI_CLASS_SERIAL 0x0C +#define PCI_CLASS_SERIAL_USB 0x03 + +#define IS_BIT_SET(Register, BitMask) (((*(volatile UINT32 *)(Register)) & (BitMask)) != 0) +#define IS_BIT_CLEAR(Register, BitMask) (((*(volatile UINT32 *)(Register)) & (BitMask)) == 0) + +#define SET_R32_BIT(Register, BitMask) \ + { \ + UINT32 RegisterValue = *(volatile UINT32 *)(Register); \ + RegisterValue |= (UINT32)(BitMask); \ + *(volatile UINT32 *)(Register) = RegisterValue; \ + } + +#define CLR_R32_BIT(Register, BitMask) \ + { \ + UINT32 RegisterValue = *(volatile UINT32 *)(Register); \ + RegisterValue &= (UINT32)(~(BitMask)); \ + *(volatile UINT32 *)(Register) = RegisterValue; \ + } + +#define CLR_AND_SET_R32_BIT(Register, BitMask, Value) \ + { \ + UINT32 RegisterValue = *(volatile UINT32 *)(Register); \ + RegisterValue &= (UINT32)(~(BitMask)); \ + RegisterValue |= (UINT32)(Value); \ + *(volatile UINT32 *)(Register) = RegisterValue; \ + } + +#define SET_R16_BIT(Register, BitMask) \ + { \ + UINT16 RegisterValue = *(volatile UINT16 *)(Register); \ + RegisterValue |= (UINT16)(BitMask); \ + *(volatile UINT16 *)(Register) = RegisterValue; \ + } + +#define CLR_R16_BIT(Register, BitMask) \ + { \ + UINT16 RegisterValue = *(volatile UINT16 *)(Register); \ + RegisterValue &= (UINT16)(~(BitMask)); \ + *(volatile UINT16 *)(Register) = RegisterValue; \ + } + +#define SET_R8_BIT(Register, BitMask) \ + { \ + UINT8 RegisterValue = *(volatile UINT8 *)(Register); \ + RegisterValue |= (UINT8)(BitMask); \ + *(volatile UINT8 *)(Register) = RegisterValue; \ + } + +#define CLR_R8_BIT(Register, BitMask) \ + { \ + UINT8 RegisterValue = *(volatile UINT8 *)(Register); \ + RegisterValue &= (UINT8)(~(BitMask)); \ + *(volatile UINT8 *)(Register) = RegisterValue; \ + } + +#define PCI_CLASS_SERIAL_USB_EHCI 0x20 +#define PCI_CAPABILITY_ID_DEBUG_PORT 0x0A + +#define PCI_USB2_SBRN_OFFSET 0x60 +#define PCI_PRIMARY_BUS_NUMBER_OFFSET 0x18 +#define PCI_SECONDARY_BUS_NUMBER_OFFSET 0x19 +#define PCI_SUBORDINATE_BUS_NUMBER_OFFSET 0x1A + +#define PCI_BRIDGE_MBASE_OFFSET 0x20 +#define PCI_BRIDGE_MLIMIT_OFFSET 0x22 + +#define PCI_EHCI_DEFAULT_BUS_NUMBER 0x00 +#define PCI_EHCI_DEFAULT_DEVICE_NUMBER 0x1D +#define PCI_EHCI_DEFAULT_FUNCTION_NUMBER 0x00 +#define PCI_EHCI_DEFAULT_DEBUG_CAPID_OFFSET 0x58 +#define PCI_EHCI_DEFAULT_DEBUG_BASE_OFFSET 0x5A + +// +// USB PIDs +// +#define USB2_PID_TOKEN_OUT 0xE1 +#define USB2_PID_TOKEN_IN 0x69 +#define USB2_PID_TOKEN_SOF 0xA5 +#define USB2_PID_TOKEN_SETUP 0x2D + +#define USB2_PID_DATA0 0xC3 +#define USB2_PID_DATA1 0x4B +#define USB2_PID_DATA2 0x87 +#define USB2_PID_MDATA 0x0F + +#define USB2_PID_HANDSHAKE_ACK 0xD2 +#define USB2_PID_HANDSHAKE_NAK 0x5A +#define USB2_PID_HANDSHAKE_STALL 0x1E +#define USB2_PID_HANDSHAKE_NYET 0x96 + +#define USB2_PID_SPECIAL_PRE 0x3C +#define USB2_PID_SPECIAL_ERR 0x3C +#define USB2_PID_SPECIAL_SPLIT 0x78 +#define USB2_PID_SPECIAL_PING 0xB4 +#define USB2_PID_SPECIAL_RESERVED 0xF0 + +// +// USB2 Debug Port Register +// +#define USB2_DEBUG_PORT_STATUS_OWNER 0x40000000 +#define USB2_DEBUG_PORT_STATUS_ENABLED 0x10000000 +#define USB2_DEBUG_PORT_STATUS_DONE 0x00010000 +#define USB2_DEBUG_PORT_STATUS_INUSE 0x00000400 +#define USB2_DEBUG_PORT_STATUS_EXCEPTION 0x00000380 +#define USB2_DEBUG_PORT_STATUS_ERROR 0x00000040 +#define USB2_DEBUG_PORT_STATUS_GO 0x00000020 +#define USB2_DEBUG_PORT_STATUS_WRITE 0x00000010 +#define USB2_DEBUG_PORT_STATUS_LENGTH 0x0000000F + +#define USB2_DEBUG_PORT_DEFAULT_ADDRESS 127 + +#define USB2_DEBUG_PORT_DEVICE_BUFFER_MAX 8 + +typedef struct _USB2_DEBUG_PORT_REGISTER { + UINT32 ControlStatus; + UINT8 TokenPid; + UINT8 SendPid; + UINT8 ReceivedPid; + UINT8 Reserved1; + UINT8 DataBuffer[USB2_DEBUG_PORT_DEVICE_BUFFER_MAX]; + UINT8 UsbEndPoint; + UINT8 UsbAddress; + UINT8 Reserved2; + UINT8 Reserved3; +}USB2_DEBUG_PORT_REGISTER; + +typedef struct _USB2_EHCI_CAPABILITY_REGISTER { + UINT8 CapLength; + UINT8 Reserved; + UINT16 HciVersion; + UINT32 HcsParams; + UINT32 HccParams; + UINT32 HcspPortRoute; +}USB2_EHCI_CAPABILITY_REGISTER; + +#define USB2_EHCI_USBCMD_RUN 0x00000001 +#define USB2_EHCI_USBCMD_RESET 0x00000002 + +#define USB2_EHCI_USBSTS_HC_HALTED 0x00001000 + +#define USB2_EHCI_PORTSC_PORT_OWNER 0x00002000 +#define USB2_EHCI_PORTSC_PORT_POWER 0x00001000 +#define USB2_EHCI_PORTSC_PORT_RESET 0x00000100 +#define USB2_EHCI_PORTSC_PORT_SUSPEND 0x00000080 +#define USB2_EHCI_PORTSC_PORT_ENABLED 0x00000004 + +typedef struct _USB2_EHCI_OPERATIONAL_REGISTER { + UINT32 UsbCommand; + UINT32 UsbStatus; + UINT32 UsbInterruptEnable; + UINT32 UsbFrameIndex; + UINT32 SegmentSelector; + UINT32 FrameListBaseAddress; + UINT32 NextAsyncListAddress; + UINT32 Reserved[9]; + UINT32 ConfigFlag; + UINT32 PortSc[0x0F]; +}USB2_EHCI_OPERATIONAL_REGISTER; + +#define USB2_DEBUG_PORT_DRIVER_BUFFER_MAX USB2_DEBUG_PORT_DEVICE_BUFFER_MAX * 2 + +typedef struct _USB2_DEBUG_PORT_INSTANCE { + + UINT32 EhciCapRegister; + UINT32 EhciOpRegister; + UINT32 PortSc; + UINT32 DebugRegister; + + BOOLEAN Ready; + + UINT8 PciBusNumber; + UINT8 PciDeviceNumber; + UINT8 PciDeviceFunction; + + UINT8 Reserved1; + UINT8 BarIndex; + UINT16 BarOffset; + + UINT32 PortBase; + UINT8 PortNumber; + UINT8 PortAddress; + UINT8 ReadEndpoint; + UINT8 WriteEndpoint; + + UINT8 ReadEndpointDataToggle; + UINT8 WriteEndpointDataToggle; + UINT8 Reserved2[2]; + + INT32 TempDataLength; + INT32 TempDataIndex; + UINT8 TempData[USB2_DEBUG_PORT_DRIVER_BUFFER_MAX]; +}USB2_DEBUG_PORT_INSTANCE; + +// +// Setup Packet +// +// Data phase transfer direction +// +#define USB2_REQUEST_TYPE_HOST_TO_DEVICE 0x00 +#define USB2_REQUEST_TYPE_DEVICE_TO_HOST 0x80 + +// +// Type +// +#define USB2_REQUEST_TYPE_STANDARD 0x00 +#define USB2_REQUEST_TYPE_CLASS 0x20 +#define USB2_REQUEST_TYPE_VENDOR 0x40 + +// +// Recipient +// +#define USB2_REQUEST_TYPE_DEVICE 0x00 +#define USB2_REQUEST_TYPE_INTERFACE 0x01 +#define USB2_REQUEST_TYPE_ENDPOINT 0x02 +#define USB2_REQUEST_TYPE_OTHER 0x03 + +// +// Request +// +#define USB2_REQUEST_GET_STATUS 0x00 +#define USB2_REQUEST_CLEAR_FEATURE 0x01 +#define USB2_REQUEST_SET_FEATURE 0x03 +#define USB2_REQUEST_SET_ADDRESS 0x05 +#define USB2_REQUEST_GET_DESCRIPTOR 0x06 +#define USB2_REQUEST_SET_DESCRIPTOR 0x07 +#define USB2_REQUEST_GET_CONFIGURATION 0x08 +#define USB2_REQUEST_SET_CONFIGURATION 0x09 +#define USB2_REQUEST_GET_INTERFACE 0x0A +#define USB2_REQUEST_SET_INTERFACE 0x11 + +// +// Descriptor Types +// +#define USB2_DESCRIPTOR_TYPE_DEVICE 0x01 +#define USB2_DESCRIPTOR_TYPE_CONFIGURATION 0x02 +#define USB2_DESCRIPTOR_TYPE_STRING 0x03 +#define USB2_DESCRIPTOR_TYPE_INTERFACE 0x04 +#define USB2_DESCRIPTOR_TYPE_ENDPOINT 0x05 +#define USB2_DESCRIPTOR_TYPE_DEVICE_QUALIFIER 0x06 +#define USB2_DESCRIPTOR_TYPE_OTHER_SPEED_CONFIGURATION 0x07 +#define USB2_DESCRIPTOR_TYPE_INTERFACE_POWER 0x08 +#define USB2_DESCRIPTOR_TYPE_OTG 0x09 +#define USB2_DESCRIPTOR_TYPE_DEBUG 0x0A + +// +// Standard Feature Selectors +// +#define USB2_FEATURE_DEVICE_REMOTE_WAKEUP 0x01 +#define USB2_FEATURE_ENDPOINT_HALT 0x00 +#define USB2_FEATURE_TEST_MODE 0x02 +#define USB2_FEATURE_OTG_B_HNP_ENABLE 0x03 +#define USB2_FEATURE_OTG_A_HNP_SUPPORT 0x04 +#define USB2_FEATURE_OTG_A_ALT_HNP_SUPPORT 0x05 +#define USB2_FEATURE_DEBUG_MODE 0x06 + +typedef struct _USB2_SETUP_PACKET { + UINT8 RequestType; + UINT8 Request; + UINT8 Value[2]; + UINT16 Index; + UINT16 Length_; +}USB2_SETUP_PACKET; + +typedef struct _USB2_DEBUG_DESCRIPTOR_TYPE { + UINT8 Length_; + UINT8 DescriptorType; + UINT8 DebugInEndpoint; + UINT8 DebugOutEndpoint; +}USB2_DEBUG_DESCRIPTOR_TYPE; + +typedef struct _USB2_ENDPOINT_DESCRIPTOR_TYPE { + UINT8 Length_; + UINT8 DescriptorType; + UINT8 EndpointAddress; + UINT8 Attributes; + UINT16 MaxPacketSize; + UINT8 Interval; +}USB2_ENDPOINT_DESCRIPTOR_TYPE; + +#endif /* _USB_DEBUG_PORT_H */ diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Platform/Purley/Include/MemDefaults.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Platform/Purley/Include/MemDefaults.h new file mode 100644 index 0000000000..df34de5a85 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Platform/Purley/Include/MemDefaults.h @@ -0,0 +1,17 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _mem_defaults_h +#define _mem_defaults_h + +#define MAX_PARTIAL_MIRROR 4 //Maximum number of partial mirror regions that can be created + +#define PPM_AUTO 0xFF + +#define MAX_AEP_DIMM_SETUP 48 //(MAX_CH * MAX_SOCKET * MAX_AEP_CH) + +#endif // _mem_platform_h diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Platform/Purley/Include/MemPlatform.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Platform/Purley/Include/MemPlatform.h new file mode 100644 index 0000000000..2171c762c8 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Platform/Purley/Include/MemPlatform.h @@ -0,0 +1,81 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _mem_platform_h +#define _mem_platform_h + +#include "DataTypes.h" + +#ifdef SERIAL_DBG_MSG +#define MRC_TRACE 1 +#endif + + +// +// Compatible BIOS Data Structure +// +#define BDAT_SUPPORT 0 //Memory Data Schema 4 and RMT Schema 5 of BDAT 4.0 + +// +// QR support +// +#define QR_DIMM_SUPPORT 1 + +// +// Define to enable DIMM margin checking +// +#define MARGIN_CHECK 1 + +// +// Define to enable SODIMM module support +// +#define SODIMM_SUPPORT 1 + +// +// Define to enable ME UMA support +// +//#define ME_SUPPORT_FLAG 1 + +// +// Define to enable XMP +// +#define XMP_SUPPORT 1 + +// Define to enable DEBUG for NVMCTLR (LATE CMD CLK) +//#define DEBUG_LATECMDCLK 1 + +// Define to enable MRS Stacking +//#define MRS_STACKING 1 + +// +// Define to max ppr +// +#define MAX_PPR_ADDR_ENTRIES 20 + +// +//------------------------------------- +// DVP Platform-specific defines +//------------------------------------- +// +#ifdef DVP_PLATFORM +#endif // DVP_PLATFORM + +// +//------------------------------------- +// CRB Platform-specific defines +//------------------------------------- +// +#ifdef CRB_PLATFORM +#endif // CRB_PLATFORM + +#ifndef MAX_HA +#define MAX_HA 2 // Number of Home Agents / IMCs +#endif + +//SKX_TODO: I have removed NonPOR elements, I will delete this line before submit + +#endif // _mem_platform_h diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Platform/Purley/Include/PlatformHost.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Platform/Purley/Include/PlatformHost.h new file mode 100644 index 0000000000..bc86d61b40 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/BaseMemoryCoreLib/Platform/Purley/Include/PlatformHost.h @@ -0,0 +1,176 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _platformhost_h +#define _platformhost_h + +// +// MAX Number of Processor supported by Intel platform +// +#include "MaxSocket.h" + +#ifndef MAX_CORE +#define MAX_CORE 28 // Maximum cores per CPU (SKX) +#define MAX_CORE_BITMASK 0xFFFFFFF // for SKX CPU +#endif + +#ifndef MAX_KTI_PORTS +#define MAX_KTI_PORTS 3 // Max KTI ports supported +#endif + +// +// Post Package Repair +// +#define PPR_SUPPORT 1 +#define MAX_PPR_ADDR_ENTRIES 20 + +// Select one of the following platforms +//#define DVP_PLATFORM 1 // DVP +// +#define CRB_PLATFORM 1 // SRP + +#ifndef DVP_PLATFORM +#ifndef CRB_PLATFORM + +/* + MULTIPLE_PLATFORM_SUPPORT should be defined when the user KNOWS that inputs + (the ones defined to zero under this flag below) are given via sysSetup structure +*/ +#define MULTIPLE_PLATFORM_SUPPORT 1 +#endif +#endif + +#if !defined(SILENT_MODE) +#define SERIAL_DBG_MSG 1 +#endif +#define RC_BEGIN_END_DEBUG_HOOKS + +//#define HW_EMULATION 1 + +#define SOFT_SDV_FLAG BIT0 // flag to indicate running on Soft SDV +#define VP_FLAG BIT1 // flag to indicate running on VP +#define SIMICS_FLAG BIT2 // flag to indicate running on Simics +#define RTL_SIM_FLAG BIT3 // flag to indicate running on the RTL simulator +#define QUIET_MODE BIT16 // flag to enable minimal debug messages +#define RANDOM_TRAINING BIT17 // flag to enable random training responses from Simics +#define FORCE_SETUP BIT18 // flag to force BIOS setup +#define DDR_TRAINING_EN BIT19 // flag to tell the BIOS to execute DDR training +// +// Enumerated Platform SMBUS controllers +// + +#define PLATFORM_SMBUS_CONTROLLER_PROCESSOR 0 +#define PLATFORM_SMBUS_CONTROLLER_PCH 1 + +#ifndef TypePlatformDefault +// +// Platform types - if not defined already +// +typedef enum { + TypeNeonCityEPRP = 0x00, + TypeNeonCityEPECB, + TypeOpalCitySTHI, + TypePurleyLBGEPDVP, + TypeWolfPass, + TypeBuchananPass, + TypeCrescentCity, + TypeHedtEV, + TypeHedtCRB, + TypeLightningRidgeEXRP, + TypeLightningRidgeEXECB1, + TypeLightningRidgeEXECB2, + TypeLightningRidgeEXECB3, + TypeLightningRidgeEXECB4, + TypeLightningRidgeEX8S1N, + TypeLightningRidgeEX8S2N, + TypeBarkPeak, + TypeKyanite, + TypeSawtoothPass, // We need to keep the value of TypeSawtoothPass unchanged + TypeNeonCityFPGA, + TypeOpalCityFPGA, + TypeYubaCityRP, + TypeDragonRock, + TypeBlueMountainPass, + TypeWolfPassFeatureRich, + TypeYubaCityRP48L, + TypeClx64L +} EFI_PLATFORM_TYPE; + + +#define TypePlatformUnknown 0xFF +#define TypePlatformMin TypeNeonCityEPRP +#define TypePlatformMax TypeClx64L + +#define TypePlatformDefault TypeNeonCityEPRP +#define TypePlatformOpalCityPPV 6 +#define TypePlatformOpalCityCPV 7 +#endif + + +// +// Enumerated Unique Platform Component IDs +// +#define NOT_INITIALIZED 0 +#define SPD 1 +#define DCP_ISL9072X 2 +#define DCP_AD5247 3 +#define MTS 4 //TSOD +#define RSTPLD 5 +#define NO_DEV 0xFFFF +// +// Default I/O base addresses +// +#define REG_ACPI_BASE_ADDRESS 0x40 +#define PM_ENABLE 0x44 +#define IO_REG_ACPI_TIMER 0x08 +#define REG_GPIO_BASE_ADDRESS 0x48 +#ifdef MINIBIOS_BUILD +#define ICH_PMBASE_ADDR 0x500 +#endif //MINIBIOS_BUILD + +// +//#define ICH_GPIOBASE_ADDR 0x500 +#define ICH_SMBBASE_ADDR 0x700 +#define R_PCH_SMBUS_PCICMD 0x04 +#define B_PCH_SMBUS_PCICMD_IOSE BIT0 +#define R_PCH_SMBUS_BASE 0x20 +#define B_PCH_SMBUS_BASE_BAR 0x0000FFE0 +#define R_PCH_SMBUS_HOSTC 0x40 +#define B_PCH_SMBUS_HOSTC_HST_EN BIT0 +// +#define SERIAL_DBG_COM_BASE 0x3F8 +// +// Platform SMBUS definitions +// +#define SMB_SEG0 0 +#define SMB_SEG1 1 +#define SMB_SEG2 2 +#define SMB_SEG3 3 + +// +// Major Warning codes +// +#define WARN_SETUP_INVALID 0x01 +#define WARN_MINOR_WILDCARD 0xff + +#define SMB_TIMEOUT 100000 // 100 ms +#define SMB_RETRY_LIMIT 20 // 2 sec +#define CATCHALL_TIMEOUT 100000 // 100 ms + +#define FOUR_GB_MEM 0x40 // 4GB in 64MB units +#define MAX_MEM_ADDR 0x40000 // 46-bit addressing (256MB units) +#define HIGH_GAP 1 // High gap (256 MB units) +#define MMCFG_SIZE 256*1024*1024 // MMCFG Size (in Bytes) +#define MMIOH_SIZE 0 // MMIOH Size Granularity per stack (1GB, (1<<(2*size))) +#define DEFAULT_COM_PORT 0x80 +// +//----------------------------------------------------------------------------- +// +#include "MemPlatform.h" + +#endif // _platformhost_h + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcieLib/CpuCsrAccessDefine.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcieLib/CpuCsrAccessDefine.h new file mode 100644 index 0000000000..ca98b502ed --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcieLib/CpuCsrAccessDefine.h @@ -0,0 +1,56 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _CPU_CSR_ACCESS_DEFINE_H_ +#define _CPU_CSR_ACCESS_DEFINE_H_ + +#include +#include +#include + +#include +#include + + +typedef enum { + BUS_CLASS = 0, + DEVICE_CLASS = 1, + FUNCTION_CLASS = 2 +} BDF_CLASS; + +UINT32 +GetSegmentNumber ( + IN USRA_ADDRESS *Address + ); + +UINT32 +GetBDFNumber ( + IN USRA_ADDRESS *Address, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar, + IN UINT8 BDFType + ); + +UINT32 +GetCpuCsrAddress ( + UINT8 SocId, + UINT8 BoxInst, + UINT32 Offset, + UINT8 *Size + ); + +UINT32 +GetMmcfgAddress( + PSYSHOST host + ); + +VOID +GetCpuCsrAccessVar_RC ( + PSYSHOST host, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar + ); + +#endif // _CPU_CSR_ACCESS_DEFINE_H_ diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcieLib/CsrToPcieDxeLib.inf b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcieLib/CsrToPcieDxeLib.inf new file mode 100644 index 0000000000..c976aa60b8 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcieLib/CsrToPcieDxeLib.inf @@ -0,0 +1,85 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = CsrToPcieDxeLib + FILE_GUID = FF3C93E7-30DE-49DE-9C02-56C2BC077561 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = CsrToPcieLib + +## {FF3C93E7-30DE-49DE-9C02-56C2BC077561} +##{ 0xff3c93e7, 0x30de, 0x49de, { 0x9c, 0x2, 0x56, 0xc2, 0xbc, 0x7, 0x75, 0x61 } }; + + +[Sources] + CsrToPcieLib.c + ../ProcMemInit/Chip/Common/CpuPciAccessCommon.c + +################################################################################ +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +################################################################################ + +[Packages] + MdePkg/MdePkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + +################################################################################ +# +# Library Class Section - list of Library Classes that are required for +# this module. +# +################################################################################ + +[LibraryClasses] + BaseLib + UefiRuntimeServicesTableLib + DebugLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[Protocols] + gEfiIioUdsProtocolGuid + +[Guids] + gEfiCpRcPkgTokenSpaceGuid + +[FixedPcd] + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount + +[Depex] + gEfiIioUdsProtocolGuid + +################################################################################ +# +# Protocol C Name Section - list of Protocol and Protocol Notify C Names +# that this module uses or produces. +# +################################################################################ +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + gEfiCpRcPkgTokenSpaceGuid.PcdPcieSegmentSize + gEfiCpRcPkgTokenSpaceGuid.PcdPcieMmcfgTablePtr + + +[BuildOptions.Ia32] + MSFT:*_*_*_CC_FLAGS = /W4 /Gs999999 /GF /GL- /wd4214 /wd4334 /wd4142 /wd4819 /DBUILDING_FOR_IA32 /DIA32 $(DSC_GLOBAL_BUILD_OPTIONS) + GCC:*_*_*_CC_FLAGS = -DBUILDING_FOR_IA32 -DIA32 $(DSC_GLOBAL_BUILD_OPTIONS) + +[BuildOptions.X64] + MSFT:*_*_X64_CC_FLAGS = /W2 /Gs32768 /DKTI_HW_PLATFORM /DBUILDING_FOR_X64 /UIA32 /DRAS_FEATURES /wd4142 /wd4819 $(DSC_GLOBAL_BUILD_OPTIONS) + GCC:*_*_X64_CC_FLAGS = -DKTI_HW_PLATFORM -DBUILDING_FOR_X64 -UIA32 -DRAS_FEATURES $(DSC_GLOBAL_BUILD_OPTIONS) diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcieLib/CsrToPcieLib.c b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcieLib/CsrToPcieLib.c new file mode 100644 index 0000000000..8fff1efec6 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcieLib/CsrToPcieLib.c @@ -0,0 +1,179 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "CpuCsrAccessDefine.h" +#include "CpuPciAccess.h" + +CPU_CSR_ACCESS_VAR *gCpuCsrAccessVarPtr = NULL; +CPU_CSR_ACCESS_VAR gCpuCsrAccessVar; + + +UINT32 +GetSegmentNumber ( + IN USRA_ADDRESS *Address + ) +{ + return 0; +}; + +UINT32 +GetBDFNumber ( + IN USRA_ADDRESS *Address, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar, + IN UINT8 BDFType +// UINT8 SocId, +// UINT8 BoxType + ) +/*++ + +Routine Description: + Indetifies the bus number for given SocId & BoxType + +Arguments: + Address - A pointer of the address of the USRA Address Structure with Csr or CsrEx type + +Returns: + PCI bus number + +--*/ +{ + UINT32 Data32 =0 ; + UINT8 SocId; + UINT8 BoxType; + UINT8 BoxInst; + UINT8 FuncBlk; + PSYSHOST host; + + SocId = (UINT8)Address->Csr.SocketId; + BoxType = (UINT8)((CSR_OFFSET *)(&Address->Csr.Offset))->Bits.boxtype; + BoxInst = (UINT8)Address->Csr.InstId; + FuncBlk = (UINT8)((CSR_OFFSET *)(&Address->Csr.Offset))->Bits.funcblk; +#ifdef IA32 + host = (PSYSHOST)Address->Attribute.HostPtr; +#else + host = (PSYSHOST)NULL; +#endif + if(BDFType == BUS_CLASS){ + Data32 = GetBusNumber(host, SocId, BoxType, BoxInst, FuncBlk, CpuCsrAccessVar); + } else if(BDFType == DEVICE_CLASS){ + Data32 = GetDeviceNumber(host, BoxType, BoxInst, FuncBlk, CpuCsrAccessVar); + } else { + Data32 = GetFunctionNumber(host, BoxType, BoxInst, FuncBlk, CpuCsrAccessVar); + } + return Data32; + +} + +VOID +GetBDF ( + IN USRA_ADDRESS *Address, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar, + USRA_PCIE_ADDR_TYPE *PcieAddress + ) +/*++ + +Routine Description: + Indetifies the bus number for given SocId & BoxType + +Arguments: + Address - A pointer of the address of the USRA Address Structure with Csr or CsrEx type + +Returns: + PCI bus number + +--*/ +{ + UINT8 SocId; + UINT8 BoxType; + UINT8 BoxInst; + UINT8 FuncBlk; + PSYSHOST host; + + SocId = (UINT8)Address->Csr.SocketId; + BoxType = (UINT8)((CSR_OFFSET *)(&Address->Csr.Offset))->Bits.boxtype; + BoxInst = (UINT8)Address->Csr.InstId; + FuncBlk = (UINT8)((CSR_OFFSET *)(&Address->Csr.Offset))->Bits.funcblk; +#ifdef IA32 + host = (PSYSHOST)Address->Attribute.HostPtr; +#else + host = (PSYSHOST)NULL; +#endif + PcieAddress->Bus = GetBusNumber(host, SocId, BoxType, BoxInst, FuncBlk, CpuCsrAccessVar); + PcieAddress->Dev = GetDeviceNumber(host, BoxType, BoxInst, FuncBlk, CpuCsrAccessVar); + PcieAddress->Func = GetFunctionNumber(host, BoxType, BoxInst, FuncBlk, CpuCsrAccessVar); + PcieAddress->Seg = SocId; // Refcode and EFI data structure difference. Refcode treats this array as 1 entry per socket, and not per segment, thus we index by SocId for now.. +} +////////////////////////////////////////////////////////////////////////// +// +// USRA Silicon Address Library +// This Lib provide the way use platform Library instance +// +////////////////////////////////////////////////////////////////////////// + +/** + This Lib Convert the logical address (CSR type, e.g. CPU ID, Boxtype, Box instance etc.) into physical address + + @param[in] Global Global pointer + @param[in] Virtual Virtual address + @param[in] Address A pointer of the address of the USRA Address Structure + @param[out] AlignedAddress A pointer of aligned address converted from USRA address + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +UINTN +EFIAPI +CsrGetPcieAlignAddress ( + IN VOID *Global, + IN BOOLEAN Virtual, + IN USRA_ADDRESS *Address, + OUT UINTN *AlignedAddress + ) +{ + CPU_CSR_ACCESS_VAR *pCpuCsrAccessVar; + USRA_ADDRESS UsraAddress; + INTN MmCfgBase; + + /********************************************************************************************************* + ToDo: + For now, this implementation only covers the Bus/Dev/Fun number generation for IVT and HSX CPUs. + Register offset and size information comes from the HSX style register offset passed to this function. + When the auto generation of header files using the new format is available, then we need to implement + the logic to translate the register pseudo offset into real offset. + *********************************************************************************************************/ + Address->Attribute.AccessWidth = (UINT8) (((((CSR_OFFSET *) &Address->Csr.Offset)->Bits.size) & 0x06) >> 1); + +#if defined (IA32) || defined (SIM_BUILD) || defined(KTI_SW_SIMULATION) || defined (HEADLESS_MRC) + CpuDeadLoop(); + pCpuCsrAccessVar = NULL; + +#else + gCpuCsrAccessVarPtr = &gCpuCsrAccessVar; + GetCpuCsrAccessVar_RC ((PSYSHOST)host, &gCpuCsrAccessVar); + + pCpuCsrAccessVar = &gCpuCsrAccessVar; +#endif // defined + + // + // Identify the PCI Bus/Device/Function number for the access + // + USRA_ZERO_ADDRESS_TYPE(UsraAddress, AddrTypePCIE); + GetBDF(Address, pCpuCsrAccessVar, &UsraAddress.Pcie); + + UsraAddress.Pcie.Offset = (UINT16)((CSR_OFFSET *) &Address->Csr.Offset)->Bits.offset; + UsraAddress.Attribute.HostPtr = Address->Attribute.HostPtr; + + MmCfgBase = GetPcieSegMmcfgBaseAddress(&UsraAddress); + *AlignedAddress = MmCfgBase + (UINTN)(UsraAddress.Attribute.RawData32[0] & 0x0fffffff); + +#if defined (IA32) || defined (SIM_BUILD) || defined(KTI_SW_SIMULATION) || defined (HEADLESS_MRC) + CpuDeadLoop(); +#endif + + return 0; +}; + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcieLib/CsrToPciePeiLib.inf b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcieLib/CsrToPciePeiLib.inf new file mode 100644 index 0000000000..ff9dfa4cbd --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcieLib/CsrToPciePeiLib.inf @@ -0,0 +1,81 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = CsrToPciePeiLib + FILE_GUID = C18FB69B-D1A7-4EF0-988D-2A40FE2E96B0 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = CsrToPcieLib + +## {C18FB69B-D1A7-4EF0-988D-2A40FE2E96B0} +##{ 0xc18fb69b, 0xd1a7, 0x4ef0, { 0x98, 0x8d, 0x2a, 0x40, 0xfe, 0x2e, 0x96, 0xb0 } }; + + +[Sources] + CsrToPcieLib.c + ../ProcMemInit/Chip/Common/CpuPciAccessCommon.c + +################################################################################ +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +################################################################################ + +[Packages] + MdePkg/MdePkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + +################################################################################ +# +# Library Class Section - list of Library Classes that are required for +# this module. +# +################################################################################ + +[LibraryClasses] + BaseLib + DebugLib + +[Protocols] + +[Guids] + gEfiCpRcPkgTokenSpaceGuid + +[FixedPcd] + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount + +[Depex] + + +################################################################################ +# +# Protocol C Name Section - list of Protocol and Protocol Notify C Names +# that this module uses or produces. +# +################################################################################ +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + gEfiCpRcPkgTokenSpaceGuid.PcdPcieSegmentSize + gEfiCpRcPkgTokenSpaceGuid.PcdPcieMmcfgTablePtr + + +[BuildOptions.Ia32] + MSFT:*_*_*_CC_FLAGS = /W4 /Gs999999 /GF /GL- /wd4214 /wd4334 /wd4142 /wd4819 /DBUILDING_FOR_IA32 /DIA32 $(DSC_GLOBAL_BUILD_OPTIONS) + GCC:*_*_*_CC_FLAGS = -DBUILDING_FOR_IA32 -DIA32 $(DSC_GLOBAL_BUILD_OPTIONS) + +[BuildOptions.X64] + MSFT:*_*_X64_CC_FLAGS = /W2 /Gs32768 /DKTI_HW_PLATFORM /DBUILDING_FOR_X64 /UIA32 /DRAS_FEATURES /wd4142 /wd4819 $(DSC_GLOBAL_BUILD_OPTIONS) + GCC:*_*_X64_CC_FLAGS = -DKTI_HW_PLATFORM -DBUILDING_FOR_X64 -UIA32 -DRAS_FEATURES $(DSC_GLOBAL_BUILD_OPTIONS) diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcieLibNull/BaseCsrToPcieLibNull.inf b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcieLibNull/BaseCsrToPcieLibNull.inf new file mode 100644 index 0000000000..32ea39bb1b --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcieLibNull/BaseCsrToPcieLibNull.inf @@ -0,0 +1,67 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = BaseCsrToPcieLibNull + FILE_GUID = 848E908E-BD11-428E-94F9-7A0EEFCD37A6 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = CsrToPcieLib + +## {848E908E-BD11-428E-94F9-7A0EEFCD37A6} +##{ 0x848e908e, 0xbd11, 0x428e, { 0x94, 0xf9, 0x7a, 0xe, 0xef, 0xcd, 0x37, 0xa6 } }; + + +[Sources] + CsrToPcieLib.c + +################################################################################ +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +################################################################################ + +[Packages] + MdePkg/MdePkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + + +################################################################################ +# +# Library Class Section - list of Library Classes that are required for +# this module. +# +################################################################################ + +[LibraryClasses] + BaseLib + PcdLib + + +[Guids] + gEfiCpRcPkgTokenSpaceGuid + +################################################################################ +# +# Protocol C Name Section - list of Protocol and Protocol Notify C Names +# that this module uses or produces. +# +################################################################################ +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + gEfiCpRcPkgTokenSpaceGuid.PcdPcieSegmentSize + gEfiCpRcPkgTokenSpaceGuid.PcdPcieMmcfgTablePtr + + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcieLibNull/CsrToPcieLib.c b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcieLibNull/CsrToPcieLib.c new file mode 100644 index 0000000000..41dfb9c0c3 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/CsrToPcieLibNull/CsrToPcieLib.c @@ -0,0 +1,41 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +////////////////////////////////////////////////////////////////////////// +// +// USRA Csr to PCIE Address Library +// This Lib provide the way use platform Library instance +// +////////////////////////////////////////////////////////////////////////// + +/** + This Lib Convert the logical address (CSR type, e.g. CPU ID, Boxtype, Box instance etc.) into physical address + + @param[in] Global Global pointer + @param[in] Virtual Virtual address + @param[in] Address A pointer of the address of the USRA Address Structure + @param[out] AlignedAddress A pointer of aligned address converted from USRA address + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +UINTN +EFIAPI +CsrGetPcieAlignAddress ( + IN VOID *Global, + IN BOOLEAN Virtual, + IN USRA_ADDRESS *Address, + OUT UINTN *AlignedAddress + ) +{ + USRA_ADDRESS PcieAddress; + USRA_ZERO_ADDRESS_TYPE(PcieAddress, AddrTypePCIE); + return 0; +}; + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/DxeMmPciBaseLib/DxeMmPciBaseLib.c b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/DxeMmPciBaseLib/DxeMmPciBaseLib.c new file mode 100644 index 0000000000..faefa3661e --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/DxeMmPciBaseLib/DxeMmPciBaseLib.c @@ -0,0 +1,89 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +USRA_PROTOCOL *mPciUsra = NULL; + +/** + The constructor function initialize UsraProtocol. + @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS. + +**/ +EFI_STATUS +EFIAPI +DxeMmPciLibConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + if (mPciUsra == NULL) + { + // + // USRA protocol need to be installed before the module access USRA. + // + Status = gBS->LocateProtocol (&gUsraProtocolGuid, NULL, (VOID **)&mPciUsra); + ASSERT_EFI_ERROR (Status); + ASSERT (mPciUsra != NULL); + } + return EFI_SUCCESS; +} + +/** + This procedure will get PCIE address + + @param[in] Bus Pci Bus Number + @param[in] Device Pci Device Number + @param[in] Function Pci Function Number + + @retval PCIE address +**/ +UINTN +MmPciBase ( + IN UINT32 Bus, + IN UINT32 Device, + IN UINT32 Function +) +{ + USRA_ADDRESS Address; + USRA_PCIE_ADDRESS(Address, UsraWidth32, Bus, Device, Function, 0); + return mPciUsra->GetRegAddr (&Address); +} + +/** + This procedure will get PCIE address + + @param[in] Seg Pcie Segment Number + @param[in] Bus Pcie Bus Number + @param[in] Device Pcie Device Number + @param[in] Function Pcie Function Number + + @retval PCIE address +**/ +UINTN +MmPciAddress( +IN UINT32 Seg, +IN UINT32 Bus, +IN UINT32 Device, +IN UINT32 Function, +IN UINT32 Register +) +{ + USRA_ADDRESS Address; + USRA_PCIE_SEG_ADDRESS(Address, UsraWidth32, Seg, Bus, Device, Function, Register); + return mPciUsra->GetRegAddr (&Address); +} diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/DxeMmPciBaseLib/DxeMmPciBaseLib.inf b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/DxeMmPciBaseLib/DxeMmPciBaseLib.inf new file mode 100644 index 0000000000..2b413621c5 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/DxeMmPciBaseLib/DxeMmPciBaseLib.inf @@ -0,0 +1,60 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = DxeSmmMmPciLib + FILE_GUID = 28D4B296-EFCE-46E4-8DA7-DA54D17AEDEF + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = MmPciLib + CONSTRUCTOR = DxeMmPciLibConstructor + + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# +[Sources] + DxeMmPciBaseLib.c + +################################################################################ +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +################################################################################ + +[Packages] + MdePkg/MdePkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + +################################################################################ +# +# Library Class Section - list of Library Classes that are required for +# this module. +# +################################################################################ + +[LibraryClasses] + BaseLib + UefiBootServicesTableLib + DxeServicesTableLib + UefiLib + IoLib + DebugLib + PcdLib + +[Protocols] + gEfiSmmCpuIo2ProtocolGuid + gUsraProtocolGuid ## CONSUMES + +[Depex] + gUsraProtocolGuid \ No newline at end of file diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/DxeMmPciBaseLib/SmmMmPciBaseLib.c b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/DxeMmPciBaseLib/SmmMmPciBaseLib.c new file mode 100644 index 0000000000..5479d173f5 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/DxeMmPciBaseLib/SmmMmPciBaseLib.c @@ -0,0 +1,86 @@ +/** @file + +Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include + +USRA_PROTOCOL *mPciUsra = NULL; + +/** + The constructor function initialize UsraProtocol. + @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS. + +**/ +EFI_STATUS +EFIAPI +SmmMmPciLibConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + if (mPciUsra == NULL) + { + // + // USRA protocol need to be installed before the module access USRA. + // + Status = gSmst->SmmLocateProtocol (&gUsraProtocolGuid, NULL, (VOID **) &mPciUsra); + ASSERT_EFI_ERROR (Status); + ASSERT (mPciUsra != NULL); + } + return EFI_SUCCESS; +} + +/** + This procedure will get PCIE address + + @param[in] Bus Pci Bus Number + @param[in] Device Pci Device Number + @param[in] Function Pci Function Number + + @retval PCIE address +**/ +UINTN +MmPciBase ( + IN UINT32 Bus, + IN UINT32 Device, + IN UINT32 Function +) +{ + USRA_ADDRESS Address; + USRA_PCIE_ADDRESS(Address, UsraWidth32, Bus, Device, Function, 0); + return mPciUsra->GetRegAddr (&Address); +} + +/** + This procedure will get PCIE address + + @param[in] Seg Pcie Segment Number + @param[in] Bus Pcie Bus Number + @param[in] Device Pcie Device Number + @param[in] Function Pcie Function Number + + @retval PCIE address +**/ +UINTN +MmPciAddress( +IN UINT32 Seg, +IN UINT32 Bus, +IN UINT32 Device, +IN UINT32 Function, +IN UINT32 Register +) +{ + USRA_ADDRESS Address; + USRA_PCIE_SEG_ADDRESS(Address, UsraWidth32, Seg, Bus, Device, Function, Register); + return mPciUsra->GetRegAddr (&Address); +} diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/DxeMmPciBaseLib/SmmMmPciBaseLib.inf b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/DxeMmPciBaseLib/SmmMmPciBaseLib.inf new file mode 100644 index 0000000000..069b5310b8 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/DxeMmPciBaseLib/SmmMmPciBaseLib.inf @@ -0,0 +1,60 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = DxeSmmMmPciLib + FILE_GUID = 96D31DB6-CCFC-4B80-B850-FC070806CA78 + MODULE_TYPE = DXE_SMM_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = MmPciLib|DXE_SMM_DRIVER + CONSTRUCTOR = SmmMmPciLibConstructor + + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# +[Sources] + SmmMmPciBaseLib.c + +################################################################################ +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +################################################################################ + +[Packages] + MdePkg/MdePkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + +################################################################################ +# +# Library Class Section - list of Library Classes that are required for +# this module. +# +################################################################################ + +[LibraryClasses] + BaseLib + UefiBootServicesTableLib + IoLib + DebugLib + UefiLib + SmmServicesTableLib + +[Protocols] + gEfiSmmCpuIo2ProtocolGuid + gUsraProtocolGuid ## CONSUMES + +[Depex.common.DXE_SMM_DRIVER] + gEfiSmmCpuIo2ProtocolGuid + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/MmPciBaseLib/MmPciBaseLib.c b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/MmPciBaseLib/MmPciBaseLib.c new file mode 100644 index 0000000000..c42c4503df --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/MmPciBaseLib/MmPciBaseLib.c @@ -0,0 +1,69 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +/** + This procedure will get PCIE address + + @param[in] Bus Pci Bus Number + @param[in] Device Pci Device Number + @param[in] Function Pci Function Number + + @retval PCIE address +**/ +UINTN +MmPciBase ( + IN UINT32 Bus, + IN UINT32 Device, + IN UINT32 Function +) +{ + USRA_ADDRESS Address; + USRA_PCIE_ADDRESS(Address, UsraWidth32, Bus, Device, Function, 0); + + if (!FeaturePcdGet (PcdSingleSegFixMmcfg)) + { + return GetRegisterAddress(&Address); + } + // + // If the PcdSingleSegFixMmcfg is true, do the following with static PcdPciExpressBaseAddress + // + return ((UINTN) (PcdGet64(PcdPciExpressBaseAddress)) + (UINTN) (Address.Attribute.RawData32[0] & 0x00ffffff)); +} + +/** + This procedure will get PCIE address + + @param[in] Seg Pcie Segment Number + @param[in] Bus Pcie Bus Number + @param[in] Device Pcie Device Number + @param[in] Function Pcie Function Number + + @retval PCIE address +**/ +UINTN +MmPciAddress( +IN UINT32 Seg, +IN UINT32 Bus, +IN UINT32 Device, +IN UINT32 Function, +IN UINT32 Register +) +{ + USRA_ADDRESS Address; + USRA_PCIE_SEG_ADDRESS(Address, UsraWidth32, Seg, Bus, Device, Function, Register); + + if (!FeaturePcdGet(PcdSingleSegFixMmcfg)) + { + return GetRegisterAddress(&Address); + } + // + // If the PcdSingleSegFixMmcfg is true, do the following with static PcdPciExpressBaseAddress + // + return ((UINTN)(PcdGet64(PcdPciExpressBaseAddress)) + (UINTN)(Address.Attribute.RawData32[0] & 0x00ffffff)); +} diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/MmPciBaseLib/MmPciBaseLib.inf b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/MmPciBaseLib/MmPciBaseLib.inf new file mode 100644 index 0000000000..ae6da88168 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/MmPciBaseLib/MmPciBaseLib.inf @@ -0,0 +1,55 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PeiDxeSmmMmPciLib + FILE_GUID = AA112999-A913-4F96-A9C4-28BFA0BD83EE + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = MmPciLib + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# +[Sources] + MmPciBaseLib.c + +################################################################################ +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +################################################################################ + + [Packages] + MdePkg/MdePkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + +################################################################################ +# +# Library Class Section - list of Library Classes that are required for +# this module. +# +################################################################################ + +[LibraryClasses] + BaseLib + IoLib + DebugLib + SiliconAccessLib + +[Guids] + gEfiCpRcPkgTokenSpaceGuid + +[Pcd] + gEfiCpRcPkgTokenSpaceGuid.PcdSingleSegFixMmcfg + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/PcieAddressLib/PcieAddressLib.c b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/PcieAddressLib/PcieAddressLib.c new file mode 100644 index 0000000000..c893b9b498 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/PcieAddressLib/PcieAddressLib.c @@ -0,0 +1,305 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include "PcieAddress.h" + +#if !defined(MINIBIOS_BUILD) && !defined(KTI_SW_SIMULATION) && !defined(SIM_BUILD) +#include +#endif + +#ifdef _MSC_VER +#pragma optimize ("",off) +#endif //_MSC_VER +////////////////////////////////////////////////////////////////////////// +// +// Common Silicon Address Library +// This Lib provide the way use platform Library instance +// +////////////////////////////////////////////////////////////////////////// + +PCIE_MMCFG_TABLE_TYPE mMmcfgTable =\ + { + { + {'M', 'C', 'F', 'G'}, // Signature + 0x00000090, // Length + 0x01, // Revision + 0x08, // The Maximum number of Segments + 0x00FF, // Valid Segment Bit Map, LSB Bit0 for Seg0, bit1 for seg1 ... + {0x00,0x00,0x00,0x00} // Reserved + }, + {{ + 0, //MMCFG_BASE_ADDRESS, // Base Address Low + 0x00000000, // Base Address High + 0x0000, // Segment 0 + 0x00, // Start Bus + 0xFF, // End Bus + {0x00,0x00,0x00,0x00} // Reserved + }} +}; +// +// Segment 1 ~ 7 +// +PCIE_MMCFG_BASE_ADDRESS_TYPE mMmcfgAddr[] = \ +{ + { + 0x00000000, // Base Address Low + 0x00000000, // Base Address High + 0x0001, // Segment 1 + 0x00, // Start Bus + 0xFF, // End Bus + {0x00,0x00,0x00,0x00} // Reserved + }, + { + 0x00000000, // Base Address Low + 0x00000000, // Base Address High + 0x0002, // Segment 2 + 0x00, // Start Bus + 0xFF, // End Bus + {0x00,0x00,0x00,0x00} // Reserved + }, + { + 0x00000000, // Base Address Low + 0x00000000, // Base Address High + 0x0003, // Segment 3 + 0x00, // Start Bus + 0xFF, // End Bus + {0x00,0x00,0x00,0x00} // Reserved + }, + + { + 0x00000000, // Base Address Low + 0x00000000, // Base Address High + 0x0004, // Segment 4 + 0x00, // Start Bus + 0xFF, // End Bus + {0x00,0x00,0x00,0x00} // Reserved + }, + { + 0x00000000, // Base Address Low + 0x00000000, // Base Address High + 0x0005, // Segment 5 + 0x00, // Start Bus + 0xFF, // End Bus + {0x00,0x00,0x00,0x00} // Reserved + }, + + { + 0x00000000, // Base Address Low + 0x00000000, // Base Address High + 0x0006, // Segment 6 + 0x00, // Start Bus + 0xFF, // End Bus + {0x00,0x00,0x00,0x00} // Reserved + }, + { + 0x00000000, // Base Address Low + 0x00000000, // Base Address High + 0x0007, // Segment 7 + 0x00, // Start Bus + 0xFF, // End Bus + {0x00,0x00,0x00,0x00} // Reserved + } +}; + + +/** + This Lib is used for platfor to set platform specific Pcie MMCFG Table + + @param MmcfgTable: A pointer of the MMCFG Table structure for PCIE_MMCFG_TABLE_TYPE type. + @param NumOfSeg: Sumber of Segments in the table. + + @retval <>NULL The function completed successfully. + @retval NULL Returen Error +**/ +UINTN +SetSocketMmcfgTable ( + IN UINT8 SocketLastBus[], + IN UINT8 SocketFirstBus[], + IN UINT8 segmentSocket[], + IN UINT32 mmCfgBaseH[], + IN UINT32 mmCfgBaseL[], + IN UINT8 NumOfSocket + ) +{ +#if !defined(MINIBIOS_BUILD) && !defined(KTI_SW_SIMULATION) && !defined(SIM_BUILD) + UINT32 MmcfgTableSize; + PCIE_MMCFG_TABLE_TYPE *HobMmcfgTable; + UINT8 i, *Dest, *Source; + + union { + UINT64 D64; + UINT32 D32[2]; + } Data; + + MmcfgTableSize = sizeof(PCIE_MMCFG_HEADER_TYPE) + (NumOfSocket * sizeof(PCIE_MMCFG_BASE_ADDRESS_TYPE)); + + HobMmcfgTable = (PCIE_MMCFG_TABLE_TYPE *) PcdGetPtr (PcdPcieMmcfgTablePtr); + ASSERT (MmcfgTableSize < PcdGetSize (PcdPcieMmcfgTablePtr)); + + Data.D64 = PcdGet64 (PcdPciExpressBaseAddress); + mMmcfgTable.MmcfgBase[0].BaseAddressL = Data.D32[0]; + mMmcfgTable.MmcfgBase[0].BaseAddressH = Data.D32[1]; + + //1. copy global variable mMcfgTable to HobMmcfgTable + // note that mMmcfgTable only has PCIE_MMCFG_BASE_ADDRESS_TYPE for segment 0 (for socket 0) + // need to copy base addresses for other segments corresponding to sockets 1 through NumOfSocket-1 + Dest = (UINT8*)HobMmcfgTable; + Source = (UINT8*)&mMmcfgTable; + for(i=0; i 1){ + Dest = (UINT8*)&HobMmcfgTable->MmcfgBase[1]; + Source = (UINT8*)&mMmcfgAddr[0];//array of base addresses starting with segment 1 (max segment = 7) + for(i = 0; i< (MmcfgTableSize - sizeof(PCIE_MMCFG_TABLE_TYPE)); i++){ + Dest[i] = Source[i]; + } + } + + HobMmcfgTable->Header.Length = MmcfgTableSize; + for(i=0; iMmcfgBase[i].StartBus = SocketFirstBus[i]; + HobMmcfgTable->MmcfgBase[i].EndBus = SocketLastBus[i]; + HobMmcfgTable->MmcfgBase[i].Segment = segmentSocket[i]; + HobMmcfgTable->MmcfgBase[i].BaseAddressH = mmCfgBaseH[i]; + HobMmcfgTable->MmcfgBase[i].BaseAddressL = mmCfgBaseL[i]; + } +#endif + return 0; +}; + + +/** + This Lib is used for platform to set platform specific Pcie MMCFG Table + + @param MmcfgTable: A pointer of the MMCFG Table structure for PCIE_MMCFG_TABLE_TYPE type. + @param NumOfSeg: Sumber of Segments in the table. + + @retval <>NULL The function completed successfully. + @retval NULL Returen Error +**/ +UINTN +EFIAPI +SetPcieSegMmcfgTable ( + IN PCIE_MMCFG_TABLE_TYPE *MmcfgTable, + IN UINT32 NumOfSeg + ) +{ +#if !defined(MINIBIOS_BUILD) && !defined(KTI_SW_SIMULATION) && !defined(SIM_BUILD) + UINT32 MmcfgTableSize; + PCIE_MMCFG_TABLE_TYPE *HobMmcfgTable; + + union { + UINT64 D64; + UINT32 D32[2]; + } Data; + + Data.D32[0] = Data.D32[1] = 0; + MmcfgTableSize = sizeof(PCIE_MMCFG_HEADER_TYPE) + (NumOfSeg * sizeof(PCIE_MMCFG_BASE_ADDRESS_TYPE)); + + HobMmcfgTable = (PCIE_MMCFG_TABLE_TYPE *) PcdGetPtr (PcdPcieMmcfgTablePtr); + //ASSERT (MmcfgTableSize < PcdGetSize (PcdPcieMmcfgTablePtr)); + + //InternalMemCopyMem(HobMmcfgTable, MmcfgTable, PcdGetSize (PcdPcieMmcfgTablePtr)); + MmcfgTable->Header.Length = MmcfgTableSize; + if((MmcfgTable->MmcfgBase[0].BaseAddressL == 0) && (MmcfgTable->MmcfgBase[0].BaseAddressH == 0)) + { + // + // The first time default should be the PcdPciExpressBaseAddress + // + Data.D64 = (UINTN) PcdGet64 (PcdPciExpressBaseAddress); + HobMmcfgTable->MmcfgBase[0].BaseAddressL = Data.D32[0]; + HobMmcfgTable->MmcfgBase[0].BaseAddressH = Data.D32[1]; + }; +#endif + return 0; +}; + + +/** + This Lib return PCIE MMCFG Base Address + + @param Address: A pointer of the address of the Common Address Structure for PCIE type. + @param Buffer: A pointer of buffer for the value read from platform. + + @retval <>NULL The function completed successfully. + @retval NULL Returen Error + **/ + +UINTN +EFIAPI +GetPcieSegMmcfgBaseAddress ( + IN USRA_ADDRESS *Address + ) +{ + UINT32 BaseAddressL=0; // Processor-relative Base Address (Lower 32-bit) for the Enhanced Configuration Access Mechanism + UINT32 BaseAddressH=0; + UINTN SegMmcfgBase; + +#if !defined(MINIBIOS_BUILD) && !defined(KTI_SW_SIMULATION) + PCIE_MMCFG_TABLE_TYPE *MmcfgTable=NULL; + union { + UINTN D64; + UINT32 D32[2]; + } Data; +#endif +#if !defined(MINIBIOS_BUILD) && !defined(KTI_SW_SIMULATION) + if(Address->Attribute.HostPtr == 0) { + MmcfgTable = (PCIE_MMCFG_TABLE_TYPE *) PcdGetPtr (PcdPcieMmcfgTablePtr); + if(MmcfgTable->Header.Length != 0) + { + BaseAddressH = MmcfgTable->MmcfgBase[Address->Pcie.Seg].BaseAddressH; + BaseAddressL = MmcfgTable->MmcfgBase[Address->Pcie.Seg].BaseAddressL; + } else { + // + // if it is not valid MMCFG pointer, initialize it to use the predefined default MMCFG Table + // + SetPcieSegMmcfgTable(&mMmcfgTable, PcdGet32 (PcdNumOfPcieSeg)); + BaseAddressH = mMmcfgTable.MmcfgBase[Address->Pcie.Seg].BaseAddressH; + BaseAddressL = mMmcfgTable.MmcfgBase[Address->Pcie.Seg].BaseAddressL; + + if((BaseAddressL == 0) && (BaseAddressH == 0)){ + Data.D32[0] = Data.D32[1] = 0; + Data.D64 = (UINTN) PcdGet64 (PcdPciExpressBaseAddress); + BaseAddressL = Data.D32[0]; + BaseAddressH = Data.D32[1]; + } + } + } + else +#endif + { + BaseAddressH = 0; + BaseAddressL = 0; + } + + if((BaseAddressL == 0) && (BaseAddressH == 0)) + { + +#if defined(MINIBIOS_BUILD) || defined(KTI_SW_SIMULATION) + BaseAddressL = 0x80000000; + BaseAddressH = 0; +#else + // + // The first time default should be the PcdPciExpressBaseAddress + // + Data.D32[0] = Data.D32[1] = 0; + Data.D64 = (UINTN) PcdGet64 (PcdPciExpressBaseAddress); + BaseAddressL = Data.D32[0]; + BaseAddressH = Data.D32[1]; +#endif + } + return SegMmcfgBase = BaseAddressL; + +}; + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/PcieAddressLib/PcieAddressLib.inf b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/PcieAddressLib/PcieAddressLib.inf new file mode 100644 index 0000000000..dad4871979 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/PcieAddressLib/PcieAddressLib.inf @@ -0,0 +1,70 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PcieAddrLib + FILE_GUID = 629E0F0C-073A-475F-BF23-1F39A5D6D1C7 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = PcieAddrLib + +## {629E0F0C-073A-475F-BF23-1F39A5D6D1C7} +##{ 0x629e0f0c, 0x73a, 0x475f, { 0xbf, 0x23, 0x1f, 0x39, 0xa5, 0xd6, 0xd1, 0xc7 } }; + + +[Sources] + PcieAddressLib.c + +################################################################################ +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +################################################################################ + +[Packages] + MdePkg/MdePkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + +################################################################################ +# +# Library Class Section - list of Library Classes that are required for +# this module. +# +################################################################################ + +[LibraryClasses] + BaseLib + PcdLib + BaseMemoryLib + + +[Guids] + gEfiCpRcPkgTokenSpaceGuid + +################################################################################ +# +# Protocol C Name Section - list of Protocol and Protocol Notify C Names +# that this module uses or produces. +# +################################################################################ +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + gEfiCpRcPkgTokenSpaceGuid.PcdPcieSegmentSize + gEfiCpRcPkgTokenSpaceGuid.PcdPcieMmcfgTablePtr + gEfiCpRcPkgTokenSpaceGuid.PcdNumOfPcieSeg + +[FixedPcd] + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/ProcMemInit/Chip/Common/CpuPciAccessCommon.c b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/ProcMemInit/Chip/Common/CpuPciAccessCommon.c new file mode 100644 index 0000000000..292dbec37b --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/ProcMemInit/Chip/Common/CpuPciAccessCommon.c @@ -0,0 +1,812 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include "CpuPciAccess.h" + +#if !defined(MINIBIOS_BUILD) && !defined(KTI_SW_SIMULATION) && !defined(SIM_BUILD) +#include +#endif + + + + +#ifndef IA32 + +#include "Library/IoLib.h" +#include +#include + + +static EFI_IIO_UDS_PROTOCOL *mIioUds; +IIO_UDS *mIioUdsDataPtr; +CPU_CSR_ACCESS_VAR *PCpuCsrAccessVarGlobal = NULL; +#endif +#ifndef IA32 +CPU_CSR_ACCESS_VAR CpuCsrAccessVarGlobal; +#endif + +// +// Disable warning for unsued input parameters +// +#ifdef _MSC_VER +#pragma warning(disable : 4100) +#pragma warning(disable : 4013) +#pragma warning(disable : 4306) +#endif + +// +// PCI function translation table; note that this table doesn't capture the function +// information for all instances of a box. It only captures for the first instance. +// It has to be translated for other instances after the look up is done. +// +STATIC UINT8 FunTbl[MAX_CPU_TYPES][MAX_BOX_TYPES][8] = { + { + {0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, // CHA MISC 0 + {0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, // CHA PMA 1 + {0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, // CHA CMS 2 + {0, 1, 2, 3, 0xFF, 0xFF, 0xFF, 0xFF}, // CHABC 3 + {0, 1, 2, 3, 4, 5, 6, 7 }, // PCU 4 + {0, 1, 2, 3, 4, 5, 6, 7 }, // VCU 5 + {0, 1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, // M2MEM 6 + {0, 4, 0, 0, 4, 0, 0xFF, 0xFF}, // MC 7 //SKX:Should be {0, 1, 4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF} + {0, 2, 4, 0, 2, 4, 0xFF, 0xFF}, // MCIO DDRIO 8 //SKX:should be {0, 1, 6, 7, 0xFF, 0xFF, 0xFF, 0xFF} + {0, 1, 2, 3, 0xFF, 0xFF, 0xFF, 0xFF}, // KTI 9 + {0, 1, 2, 3, 0xFF, 0xFF, 0xFF, 0xFF}, // M3KTI 10 + {2, 6, 2, 2, 6, 2, 0xFF, 0xFF}, // MCDDC 11 //SKX:SHould be {2, 3, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, // MCDDC These entries all seem wrong but work + {0, 1, 3, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, // M2UPCIE 12 + {0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, // IIO DMI 13 + {0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, // IIO PCIE 14 + {0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, // IIO PCIENTB 15 + {0, 1, 2, 3, 4, 5, 6, 7 }, // IIOCB 16 + {0, 1, 2, 4, 5, 6, 0xFF, 0xFF}, // IIO VTD 17 + {0, 0, 7, 7, 4, 4, 0xFF, 0xFF}, // IIO_RTO 18 + {0, 1, 2, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, // UBOX 19 + }, // SKX +}; + +STATIC UINT8 m2pcieDevTable[MAX_SKX_M2PCIE] = { 22, 21, 22, 23, 21}; + +/** + + Populate CpuCsrAccessVar structure. + + @param host - pointer to the system host root structure + @param CpuCsrAccessVar - pointer to CpuCsrAccessVar structure to be populated + + @retval None + +**/ +VOID +GetCpuCsrAccessVar_RC ( + PSYSHOST host, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar + ) +{ +#ifndef IA32 + EFI_STATUS Status; +#endif + + if (host != NULL) { + CpuDeadLoop (); + } + +#ifndef IA32 + if (host == NULL) { + if(PCpuCsrAccessVarGlobal == NULL){ //check if 1st time, if yes, then need to update + // Locate the IIO Protocol Interface + Status = gBS->LocateProtocol (&gEfiIioUdsProtocolGuid, NULL, &mIioUds); + mIioUdsDataPtr = (IIO_UDS *)mIioUds->IioUdsPtr; + //ASSERT_EFI_ERROR (Status); + + PCpuCsrAccessVarGlobal = &CpuCsrAccessVarGlobal; + for (socket = 0; socket < MAX_SOCKET; socket++) { + CpuCsrAccessVarGlobal.stackPresentBitmap[socket] = mIioUdsDataPtr->PlatformData.CpuQpiInfo[socket].stackPresentBitmap; + CpuCsrAccessVarGlobal.SocketFirstBus[socket] = mIioUdsDataPtr->PlatformData.CpuQpiInfo[socket].SocketFirstBus; + CpuCsrAccessVarGlobal.SocketLastBus[socket] = mIioUdsDataPtr->PlatformData.CpuQpiInfo[socket].SocketLastBus; + CpuCsrAccessVarGlobal.segmentSocket[socket] = mIioUdsDataPtr->PlatformData.CpuQpiInfo[socket].segmentSocket; + + for (ctr = 0; ctr < MAX_IIO_STACK; ctr++) { + CpuCsrAccessVarGlobal.StackBus[socket][ctr] = mIioUdsDataPtr->PlatformData.CpuQpiInfo[socket].StackBus[ctr]; + } + } + + CpuCsrAccessVarGlobal.cpuType = mIioUdsDataPtr->SystemStatus.cpuType; + CpuCsrAccessVarGlobal.stepping = mIioUdsDataPtr->SystemStatus.MinimumCpuStepping; + CpuCsrAccessVarGlobal.socketPresentBitMap = mIioUdsDataPtr->SystemStatus.socketPresentBitMap; + CpuCsrAccessVarGlobal.FpgaPresentBitMap = mIioUdsDataPtr->SystemStatus.FpgaPresentBitMap; + CpuCsrAccessVarGlobal.mmCfgBase = (UINT32)mIioUdsDataPtr->PlatformData.PciExpressBase; + CpuCsrAccessVarGlobal.numChPerMC = mIioUdsDataPtr->SystemStatus.numChPerMC; + CpuCsrAccessVarGlobal.maxCh = mIioUdsDataPtr->SystemStatus.maxCh; + CpuCsrAccessVarGlobal.maxIMC = mIioUdsDataPtr->SystemStatus.maxIMC; + } + + if ((PCpuCsrAccessVarGlobal != NULL) && (CpuCsrAccessVarGlobal.socketPresentBitMap != mIioUdsDataPtr->SystemStatus.socketPresentBitMap)) { + for (socket = 0; socket < MAX_SOCKET; socket++) { + CpuCsrAccessVarGlobal.stackPresentBitmap[socket] = mIioUdsDataPtr->PlatformData.CpuQpiInfo[socket].stackPresentBitmap; + CpuCsrAccessVarGlobal.SocketFirstBus[socket] = mIioUdsDataPtr->PlatformData.CpuQpiInfo[socket].SocketFirstBus; + CpuCsrAccessVarGlobal.SocketLastBus[socket] = mIioUdsDataPtr->PlatformData.CpuQpiInfo[socket].SocketLastBus; + CpuCsrAccessVarGlobal.segmentSocket[socket] = mIioUdsDataPtr->PlatformData.CpuQpiInfo[socket].segmentSocket; + + for (ctr = 0; ctr < MAX_IIO_STACK; ctr++) { + CpuCsrAccessVarGlobal.StackBus[socket][ctr] = mIioUdsDataPtr->PlatformData.CpuQpiInfo[socket].StackBus[ctr]; + } + } + + CpuCsrAccessVarGlobal.cpuType = mIioUdsDataPtr->SystemStatus.cpuType; + CpuCsrAccessVarGlobal.stepping = mIioUdsDataPtr->SystemStatus.MinimumCpuStepping; + CpuCsrAccessVarGlobal.socketPresentBitMap = mIioUdsDataPtr->SystemStatus.socketPresentBitMap; + CpuCsrAccessVarGlobal.FpgaPresentBitMap = mIioUdsDataPtr->SystemStatus.FpgaPresentBitMap; + CpuCsrAccessVarGlobal.mmCfgBase = (UINT32)mIioUdsDataPtr->PlatformData.PciExpressBase; + CpuCsrAccessVarGlobal.numChPerMC = mIioUdsDataPtr->SystemStatus.numChPerMC; + CpuCsrAccessVarGlobal.maxCh = mIioUdsDataPtr->SystemStatus.maxCh; + CpuCsrAccessVarGlobal.maxIMC = mIioUdsDataPtr->SystemStatus.maxIMC; + } + + for (socket = 0; socket < MAX_SOCKET; socket++) { + CpuCsrAccessVar->stackPresentBitmap[socket] = CpuCsrAccessVarGlobal.stackPresentBitmap[socket]; + + + CopyMem (&CpuCsrAccessVar->StackBus[socket], &CpuCsrAccessVarGlobal.StackBus[socket], MAX_IIO_STACK); + } + CpuCsrAccessVar->cpuType = CpuCsrAccessVarGlobal.cpuType; + //CpuCsrAccessVar->stepping = CpuCsrAccessVarGlobal.stepping; + CpuCsrAccessVar->socketPresentBitMap = CpuCsrAccessVarGlobal.socketPresentBitMap; + CpuCsrAccessVar->FpgaPresentBitMap = CpuCsrAccessVarGlobal.FpgaPresentBitMap; + //CpuCsrAccessVar->mmCfgBase = CpuCsrAccessVarGlobal.mmCfgBase; + CpuCsrAccessVar->numChPerMC = CpuCsrAccessVarGlobal.numChPerMC; + CpuCsrAccessVar->maxCh = CpuCsrAccessVarGlobal.maxCh; + //CpuCsrAccessVar->maxIMC = CpuCsrAccessVarGlobal.maxIMC; + } +#endif +} + +/** + + Stall execution after internal assertion fails + + @param haltOnError - 1 stalls in infinite loop; 0 returns to caller + + @retval None + +**/ +VOID RcDeadLoop ( + UINT8 haltOnError + ) +{ + // + // Prevent from optimizing out + // + while (*(volatile UINT8 *) &haltOnError); +} + +/** + + CsrAccess specific print to serial output + + @param host - Pointer to the system host (root) structure + @param Format - string format + + @retval N/A + +**/ +VOID +CpuCsrAccessError ( + PSYSHOST host, + char* Format, + ... + ) +{ + UINT8 haltOnError; +#ifdef SERIAL_DBG_MSG +#if !defined(MINIBIOS_BUILD) && !defined(KTI_SW_SIMULATION) && !defined(SIM_BUILD) + UINT32 *pData32; +#endif + va_list Marker; + va_start (Marker, Format); +#if !defined(MINIBIOS_BUILD) && !defined(KTI_SW_SIMULATION) && !defined(SIM_BUILD) + if (host != NULL) { + pData32 = (UINT32 *)Marker; + if( (*pData32 & 0xFFFFFF00) == 0xFFFFFF00){ // check if input is one byte only + *pData32 = *pData32 & 0x000000FF; + } if( (*pData32 & 0xFFFF0000) == 0xFFFF0000){ // check if input is word only + *pData32 = *pData32 & 0x0000FFFF; + } + DEBUG (( + DEBUG_ERROR, Format, *pData32 + )); + } +#else + if (host != NULL) { + rcVprintf (host, Format, Marker); + } +#endif + va_end (Marker); +#endif + haltOnError = 1; + RcDeadLoop (haltOnError); + + return; +} + +/** + + Returns the CPU Index for MC func tbl lookup based on CPU type and CPU sub type. + This index will be used for MC box instance -> function mapping look-up + + @param host - Pointer to the system host (root) structure + + @retval Index for CPU type + +**/ +STATIC +UINT8 +GetCpuIndex ( + PSYSHOST host + ) +{ + UINT8 cpuIndex = 0xFF; + + cpuIndex = 0; + return cpuIndex; +} + +/** + + Indetifies the bus number for given SocId & BoxType + + @param host - Pointer to the system host (root) structure + @param SocId - CPU Socket Node number (Socket ID) + @param BoxType - Box Type; values come from CpuPciAccess.h + + @retval PCI bus number + +**/ +UINT32 +GetBusNumber ( + PSYSHOST host, + UINT8 SocId, + UINT8 BoxType, + UINT8 BoxInst, + UINT8 FuncBlk, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar + ) +{ + UINT32 Bus = 0; + UINT8 TempStack = 0; + + + + // Make sure SocId or Fpga is valid + if ((!((CpuCsrAccessVar->socketPresentBitMap & (1 << SocId)) && (BoxType != BOX_FPGA)))) { + if ((!((CpuCsrAccessVar->FpgaPresentBitMap & (1 << SocId)) && (BoxType == BOX_FPGA)))) { + CpuCsrAccessError (host, "\nInvalid Socket Id %d. \n", SocId); + } + } + + // + // Each socket is assigned multiple buses + // Check the box type and return the appropriate bus number. + // + if ((BoxType == BOX_MC) || + (BoxType == BOX_MCDDC) || + (BoxType == BOX_MCIO) || + (BoxType == BOX_M2MEM)) { + Bus = CpuCsrAccessVar->StackBus[SocId][IIO_PSTACK1]; + + } else if (BoxType == BOX_UBOX) { + Bus = CpuCsrAccessVar->StackBus[SocId][IIO_CSTACK]; + } else if ((BoxType == BOX_IIO_PCIE_DMI) || + (BoxType == BOX_IIO_CB)) { + Bus = CpuCsrAccessVar->StackBus[SocId][IIO_CSTACK]; + } else if (BoxType == BOX_IIO_PCIE) { + // + // IIO_PCIE is used to access all pcie ports in all stacks + // + if (BoxInst == 0) { + Bus = CpuCsrAccessVar->StackBus[SocId][IIO_CSTACK]; + } else { + TempStack = IIO_PSTACK0 + ((BoxInst-1) / 4); + if (TempStack < MAX_IIO_STACK) { + Bus = CpuCsrAccessVar->StackBus[SocId][TempStack]; + } else { + CpuCsrAccessError (host, "\nInvalid IIO_PCIE BoxInstance %d. \n", BoxInst); + } + } + } else if (BoxType == BOX_IIO_VTD) { + TempStack = IIO_CSTACK + BoxInst; + if (TempStack < MAX_IIO_STACK) { + Bus = CpuCsrAccessVar->StackBus[SocId][TempStack]; + } else { + CpuCsrAccessError (host, "\nInvalid BOX_IIO_VTD BoxInstance %d. \n", BoxInst); + } + } else if (BoxType == BOX_IIO_PCIE_NTB) { + if (BoxInst > 0) { + TempStack = IIO_PSTACK0 + ((BoxInst-1) / 4); + if (TempStack < MAX_IIO_STACK) { + Bus = CpuCsrAccessVar->StackBus[SocId][TempStack]; + } else { + CpuCsrAccessError (host, "\nInvalid BOX_IIO_PCIE_NTB BoxInstance %d. \n", BoxInst); + } + } else { + CpuCsrAccessError (host, "\nInvalid BOX_IIO_PCIE_NTB BoxInstance %d. \n", BoxInst); + } + } else if (BoxType == BOX_IIO_RTO) { + if (FuncBlk == IIO_RTO) { + // + // IIO_RTO is used to access all pcie ports in all stacks same as iio_pcie + // + if (BoxInst == 0) { + Bus = CpuCsrAccessVar->StackBus[SocId][IIO_CSTACK]; + } else { + TempStack = IIO_PSTACK0 + ((BoxInst-1) / 4); + if (TempStack < MAX_IIO_STACK) { + Bus = CpuCsrAccessVar->StackBus[SocId][TempStack]; + } else { + CpuCsrAccessError (host, "\nInvalid IIO_PCIE BoxInstance %d. \n", BoxInst); + } + } + } else if ((FuncBlk == IIO_RTO_GLOBAL) || (FuncBlk == IIO_RTO_VTD)) { + // + // IIO_RTO_GLOBAL and IIO_RTO_VTD maps 1 instance per c/p/m stack + // + if ((IIO_CSTACK + BoxInst) < MAX_IIO_STACK) { + Bus = CpuCsrAccessVar->StackBus[SocId][IIO_CSTACK + BoxInst]; + } + } else if ((FuncBlk == IIO_RTO_VTD_DMI) || + (FuncBlk == IIO_RTO_DMI) || + (FuncBlk == IIO_RTO_GLOBAL_DMI)) { + Bus = CpuCsrAccessVar->StackBus[SocId][IIO_CSTACK]; + } else { + CpuCsrAccessError (host, "\nInvalid BoxType %d, Functional block %d. \n", BoxType, FuncBlk); + } + } else if ((BoxType == BOX_CHA_MISC) || + (BoxType == BOX_CHA_PMA) || + (BoxType == BOX_CHA_CMS) || + (BoxType == BOX_CHABC) || + (BoxType == BOX_PCU) || + (BoxType == BOX_VCU)) { + Bus = CpuCsrAccessVar->StackBus[SocId][IIO_PSTACK0]; + } else if ((BoxType == BOX_M2UPCIE) || + (BoxType == BOX_KTI) || + (BoxType == BOX_M3KTI)) { + Bus = CpuCsrAccessVar->StackBus[SocId][IIO_PSTACK2]; + } else if (BoxType == BOX_FPGA) { + Bus = CpuCsrAccessVar->StackBus[SocId][IIO_CSTACK]; + + } else { + // Error + CpuCsrAccessError (host, "\nInvalid BoxType %d. \n", BoxType); + } + + return Bus; +} + +/** + + Indetifies the device number for given Box Type & Box Instance + + @param host - Pointer to the system host (root) structure + @param BoxType - Box Type; values come from CpuPciAccess.h + @param BoxInst - Box Instance, 0 based + @param FuncBlk - Functional Block; values come from CpuPciAccess.h + + @retval PCI Device number + +**/ +UINT32 +GetDeviceNumber ( + PSYSHOST host, + UINT8 BoxType, + UINT8 BoxInst, + UINT8 FuncBlk, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar + ) +{ + UINT32 Dev = 0; + UINT8 CpuType, NumChPerMC; + + CpuType = CpuCsrAccessVar->cpuType; + NumChPerMC = CpuCsrAccessVar->numChPerMC; + + + // + // Translate the Box Type & Instance into PCI Device number. + // + switch (BoxType) { + case BOX_MC: + case BOX_MCDDC: + if (CpuType == CPU_SKX) { + switch (BoxInst) { + case 0: + case 1: + Dev = 10; + break; + case 2: + Dev = 11; + break; + case 3: + case 4: + Dev = 12; + break; + case 5: + Dev = 13; + break; + } + } else { + CpuCsrAccessError (host, "\nInvalid Cpu type.\n"); + } + break; + + case BOX_MCIO: + if (CpuType == CPU_SKX) { + Dev = 22 + (BoxInst / NumChPerMC); + } else { + CpuCsrAccessError (host, "\nInvalid Cpu type.\n"); + } + break; + + case BOX_M2MEM: + if ((CpuType == CPU_SKX) && (BoxInst < MAX_SKX_M2MEM)) { + Dev = 8 + BoxInst; + } else { + CpuCsrAccessError (host, "\nInvalid M2MEM Box Instance Number %d. \n", BoxInst); + } + break; + + case BOX_CHA_MISC: + if ((CpuType == CPU_SKX) && (BoxInst < MAX_SKX_CHA)) { + if (BoxInst < 8) { + Dev = 8; + } else if (BoxInst < 16) { + Dev = 9; + } else if (BoxInst < 24) { + Dev = 10; + } else if (BoxInst < 28) { + Dev = 11; + } + } else { + CpuCsrAccessError (host, "\nInvalid CHA Box Instance Number %d. \n", BoxInst); + } + break; + + case BOX_CHA_PMA: + if ((CpuType == CPU_SKX) && (BoxInst < MAX_SKX_CHA)) { + if (BoxInst < 8) { + Dev = 14; + } else if (BoxInst < 16) { + Dev = 15; + } else if (BoxInst < 24) { + Dev = 16; + } else if (BoxInst < 28) { + Dev = 17; + } + } else { + CpuCsrAccessError (host, "\nInvalid CHA Box Instance Number %d. \n", BoxInst); + } + break; + + case BOX_CHA_CMS: + if ((CpuType == CPU_SKX) && (BoxInst < MAX_SKX_CHA)) { + if (BoxInst < 8) { + Dev = 20; + } else if (BoxInst < 16) { + Dev = 21; + } else if (BoxInst < 24) { + Dev = 22; + } else if (BoxInst < 28) { + Dev = 23; + } + } else { + CpuCsrAccessError (host, "\nInvalid CHA Box Instance Number %d. \n", BoxInst); + } + break; + + case BOX_CHABC: + if ((CpuType == CPU_SKX) && (BoxInst == 0)) { + Dev = 29; + } else { + CpuCsrAccessError (host, "\nInvalid CHABC Box Instance Number %d. \n", BoxInst); + } + break; + + case BOX_PCU: + if ((CpuType == CPU_SKX) && (BoxInst < MAX_ALL_PCU)) { + Dev = 30; + } else { + CpuCsrAccessError (host, "\nInvalid PCU Box Instance Number %d. \n", BoxInst); + } + break; + + case BOX_VCU: + if ((CpuType == CPU_SKX) && (BoxInst < MAX_ALL_VCU)) { + Dev = 31; + } else { + CpuCsrAccessError (host, "\nInvalid VCU Box Instance Number %d. \n", BoxInst); + } + break; + + case BOX_KTI: + /* + Dev # KTI(phy,logic)# + 14 0 0 + 15 1 1 + 16 2 2 + */ + if (CpuType == CPU_SKX) { + if (BoxInst < MAX_SKX_KTIAGENT ) { + Dev = 14 + BoxInst; + } else { + CpuCsrAccessError (host, "\nInvalid KTI Box Instance Number %d. \n", BoxInst); + } + } else { + CpuCsrAccessError (host, "\nInvalid Cpu type.\n"); + } + break; + + case BOX_M3KTI: + /* + Logical M3KTI # Dev # Fun # + KTI01 0 18 0 + KTI23 1 18 4 + */ + + if (CpuType == CPU_SKX) { + if (BoxInst < 2 ) { + Dev = 18; + } else { + CpuCsrAccessError (host, "\nInvalid Box instance.\n"); + } + } else { + CpuCsrAccessError (host, "\nInvalid Cpu type.\n"); + } + break; + + case BOX_M2UPCIE: + if (CpuType == CPU_SKX) { + if (BoxInst < MAX_SKX_M2PCIE) { + Dev = m2pcieDevTable[BoxInst]; + } else { + CpuCsrAccessError (host, "\nInvalid KTI Box Instance Number %d. \n", BoxInst); + } + } else { + CpuCsrAccessError (host, "\nInvalid Cpu type.\n"); + } + break; + + case BOX_IIO_PCIE_DMI: + if ((CpuType == CPU_SKX) && (BoxInst < MAX_ALL_IIO)) { + Dev = 0; + } else { + CpuCsrAccessError (host, "\nInvalid IIO PCIE DMI Box Instance Number %d. \n", BoxInst); + } + break; + + case BOX_IIO_PCIE: + if ((CpuType == CPU_SKX) && (BoxInst < MAX_ALL_IIO_PCIE)) { + if (BoxInst == 0) { + // Cstack + Dev = 0; + } else { + // M/Pstacks + Dev = 0 + ((BoxInst-1) % 4); + } + } else { + CpuCsrAccessError (host, "\nInvalid IIO PCIE Box Instance Number %d. \n", BoxInst); + } + break; + + case BOX_IIO_PCIE_NTB: + if ((CpuType == CPU_SKX)) { + Dev = 0; + } else { + CpuCsrAccessError (host, "\nInvalid IIO PCIE Box Instance Number %d. \n", BoxInst); + } + break; + + case BOX_IIO_CB: + if ((CpuType == CPU_SKX)) { + Dev = 4; + } else { + CpuCsrAccessError (host, "\nInvalid IIO CB Box Instance Number %d. \n", BoxInst); + } + break; + + case BOX_IIO_VTD: + if ((CpuType == CPU_SKX)) { + Dev = 5; + } else { + CpuCsrAccessError (host, "\nInvalid IIO VTD Box Instance Number %d. \n", BoxInst); + } + break; + + case BOX_IIO_RTO: + if ((CpuType == CPU_SKX) && (BoxInst < MAX_ALL_IIO_RTO)) { + Dev = 7; + } else { + CpuCsrAccessError (host, "\nInvalid IIO RTO Box Instance Number %d. \n", BoxInst); + } + break; + + case BOX_UBOX: + if ((CpuType == CPU_SKX) && (BoxInst < MAX_ALL_UBOX)) { + Dev = 8; + } else { + CpuCsrAccessError (host, "\nInvalid Ubox Instance Number %d. \n", BoxInst); + //Note: the fatal error function writes to UBOX CSR and recurses forever (until stack is gone). + } + break; + case BOX_FPGA: + if ((CpuType == CPU_SKX) && (BoxInst == 0)) { + Dev = 16; + } else { + CpuCsrAccessError (host, "\nInvalid FPGA Instance number %d. \n", BoxInst); + } + break; + + default: + CpuCsrAccessError (host, "\nInvalid Box Type %d. \n", BoxType); + } + + if (Dev > 31) { + CpuCsrAccessError (host, "\nInvalid Device %d accessed for Box Type %d and Box Instance %d. \n", Dev, BoxType, BoxInst); + } + return Dev; +} + +/** + + Indetifies the function number for given BoxType, BoxInst & Functional Block + + @param host - Pointer to the system host (root) structure + @param BoxType - Box Type; values come from CpuPciAccess.h + @param BoxInst - Box Instance, 0 based + @param FuncBlk - Functional Block; values come from CpuPciAccess.h + + @retval PCI Function number + +**/ +UINT32 +GetFunctionNumber ( + PSYSHOST host, + UINT8 BoxType, + UINT8 BoxInst, + UINT8 FuncBlk, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar + ) +{ + UINT32 Fun = 0; + UINT8 CpuIndex, CpuType, NumChPerMC; + + CpuType = CpuCsrAccessVar->cpuType; + NumChPerMC = CpuCsrAccessVar->numChPerMC; + + // Get the CPU type, sub type + CpuIndex = GetCpuIndex(host); + + // + // Translate the Box Type & Functional Block into PCI function number. Note that the box type & instance number + // passed to this routine are assumed to be valid; here we only need to validate if the function number is correct + // after the look up is done. + // + + switch (BoxType) { + + case BOX_MC: + + if (FuncBlk == 0 || FuncBlk == 1) { + Fun = FunTbl[CpuType][BoxType][BoxInst % NumChPerMC] + FuncBlk; + } else { + Fun = 4; + } + break; + + case BOX_MCDDC: + + Fun = FunTbl[CpuType][BoxType][BoxInst % NumChPerMC] + FuncBlk; + break; + + case BOX_MCIO: + + if (FuncBlk == 2) { + Fun = FunTbl[CpuType][BoxType][BoxInst % NumChPerMC] + 3; + + } else { + Fun = FunTbl[CpuType][BoxType][BoxInst % NumChPerMC] + FuncBlk; + } + break; + + case BOX_CHA_MISC: + case BOX_CHA_PMA: + case BOX_CHA_CMS: + // + // For Cha, no table look up is needed; the function number can be obtained from instance number. + // + if ((CpuType == CPU_SKX) && (BoxInst < MAX_SKX_CHA)) { + Fun = (BoxInst % 8); + } + break; + + case BOX_M3KTI: + /* + Logical M3KTI # Dev # Fun # + KTI01 0 18 0 + KTI23 1 18 4 + */ + + Fun = FunTbl[CpuType][BoxType][FuncBlk]; + if (BoxInst == 1) { + Fun = Fun + 4; + } + break; + + case BOX_M2MEM: + case BOX_CHABC: + case BOX_PCU: + case BOX_VCU: + case BOX_IIO_PCIE_DMI: + case BOX_IIO_PCIE: + case BOX_IIO_PCIE_NTB: + case BOX_IIO_CB: + case BOX_IIO_VTD: + case BOX_UBOX: + Fun = FunTbl[CpuType][BoxType][FuncBlk]; + break; + + case BOX_M2UPCIE: + Fun = FunTbl[CpuType][BoxType][FuncBlk]; + if (BoxInst == 2 || BoxInst == 4) { // M2PCIE2 & M2MCP1 + Fun = Fun + 4; + } + break; + + case BOX_KTI: + Fun = FunTbl[CpuType][BoxType][FuncBlk]; + if (BoxInst >=9 ) { + Fun = Fun + 4; + } + break; + + case BOX_IIO_RTO: + if ((BoxInst < MAX_ALL_IIO_RTO) && (FunTbl[CpuType][BoxType][FuncBlk] != 0xFF)) { + if (FuncBlk == IIO_RTO) { + if (BoxInst == 0) { + // Cstack + Fun = 0; + } else { + // M/Pstacks + Fun = 0 + ((BoxInst-1) % 4); + } + } else { + Fun = FunTbl[CpuType][BoxType][FuncBlk]; + } + } else { + CpuCsrAccessError (host, "\nInvalid IIO RTO Box Instance Number %d. \n", BoxInst); + } + break; + + case BOX_FPGA: + if (BoxInst == 0) { + Fun = 0; + } else { + CpuCsrAccessError (host, "\nInvalid FPGA Box Instance Number %d. \n", BoxInst); + } + break; + + default: + CpuCsrAccessError (host, "\nInvalid Box Type %d. \n", BoxType); + } + + if (Fun > 7) { + CpuCsrAccessError (host, "\nInvalid Functional Block %d accessed for CPUType %d CPUIndex %d Box Type %d and Box Instance %d. \n", + FuncBlk, CpuType, CpuIndex, BoxType, BoxInst); + } + + return Fun; +} + + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/ProcMemInit/Chip/Include/CpuCsrAccessDefine.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/ProcMemInit/Chip/Include/CpuCsrAccessDefine.h new file mode 100644 index 0000000000..bee66dbed9 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/ProcMemInit/Chip/Include/CpuCsrAccessDefine.h @@ -0,0 +1,52 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _CPU_CSR_ACCESS_DEFINE_H_ +#define _CPU_CSR_ACCESS_DEFINE_H_ + +#include +#include + + +typedef enum { + BUS_CLASS = 0, + DEVICE_CLASS = 1, + FUNCTION_CLASS = 2 +} BDF_CLASS; + +UINT32 +GetSegmentNumber ( + IN USRA_ADDRESS *Address + ); + +UINT32 +GetBDFNumber ( + IN USRA_ADDRESS *Address, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar, + IN UINT8 BDFType + ); + +UINT32 +GetCpuCsrAddress ( + UINT8 SocId, + UINT8 BoxInst, + UINT32 Offset, + UINT8 *Size + ); + +UINT32 +GetMmcfgAddress( + PSYSHOST host + ); + +VOID +GetCpuCsrAccessVar_RC ( + PSYSHOST host, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar + ); + +#endif // _CPU_CSR_ACCESS_DEFINE_H_ diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/ProcMemInit/Chip/Include/CpuPciAccess.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/ProcMemInit/Chip/Include/CpuPciAccess.h new file mode 100644 index 0000000000..6ace86975a --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/ProcMemInit/Chip/Include/CpuPciAccess.h @@ -0,0 +1,117 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _CPU_PCI_ACCESS_H_ +#define _CPU_PCI_ACCESS_H_ + +#include "DataTypes.h" + + + +// +// CPU Types; this needs to be contiguous to assist in table look up +// +#define MAX_CPU_TYPES 1 + +// +// CPU Index for MC function look-up +// +#define MAX_CPU_INDEX 1 + + +// +// Box Types; this needs to be contiguous to assist in table look up +// +#define BOX_CHA_MISC 0 +#define BOX_CHA_PMA 1 +#define BOX_CHA_CMS 2 +#define BOX_CHABC 3 +#define BOX_PCU 4 +#define BOX_VCU 5 +#define BOX_M2MEM 6 +#define BOX_MC 7 +#define BOX_MCIO 8 +#define BOX_KTI 9 +#define BOX_M3KTI 10 +#define BOX_MCDDC 11 +#define BOX_M2UPCIE 12 +#define BOX_IIO_PCIE_DMI 13 +#define BOX_IIO_PCIE 14 +#define BOX_IIO_PCIE_NTB 15 +#define BOX_IIO_CB 16 +#define BOX_IIO_VTD 17 +#define BOX_IIO_RTO 18 +#define BOX_UBOX 19 +#define BOX_FPGA 20 +#define MAX_BOX_TYPES 21 + + +// +// Maximum Number of Instances supported by each box type. Note that if the number of instances +// are same for all supported CPUs, then we will have only one #define here (i.e MAX_ALL_XXXXX) +// +#define MAX_SKX_CHA 28 + +#define MAX_SKX_M2PCIE 5 + +#define MAX_ALL_CBOBC 1 + +#define MAX_SKX_M3KTI 2 + +#define MAX_SKX_KTIAGENT 3 + +#define MAX_SKX_M2MEM 2 + +#define MAX_ALL_M2PCIE 1 +#define MAX_ALL_UBOX 1 +#define MAX_ALL_IIO 4 +#define MAX_ALL_PCU 1 +#define MAX_ALL_VCU 1 + +#define MAX_ALL_IIO_CB 1 // 1 instance per CB function block +#define MAX_ALL_IIO_PCIE_DMI 1 // 0:0:0 +#define MAX_ALL_IIO_PCIE_NTB 3 // 4 instances in PCIE_NTB (0:3:0/1/2/3) +#define MAX_ALL_IIO_RTO 21 // 4 instances per M/PSTACK + 1 Cstack +#define MAX_ALL_IIO_RTO_DMI 4 // 4 instances in C stack +#define MAX_ALL_IIO_RTO_VTD 6 // 6 instances in IIO_RTO block across C/P/MCP stacks +#define MAX_ALL_IIO_RTO_VTD_DMI 1 // 1 instances in IIO_RTO block across C stack +#define MAX_ALL_IIO_PCIE 21 // 4 instances per M/PSTACK + 1 Cstack + + +#define IIO_RTO 0 +#define IIO_RTO_DMI 1 +#define IIO_RTO_GLOBAL 2 +#define IIO_RTO_GLOBAL_DMI 3 +#define IIO_RTO_VTD 4 +#define IIO_RTO_VTD_DMI 5 + +// +// Format of CSR register offset passed to helper functions. +// This must be kept in sync with the CSR XML parser tool that generates CSR offset definitions in the CSR header files. +// +typedef union { + struct { + UINT32 offset : 12; // bits <11:0> + UINT32 size : 3; // bits <14:12> + UINT32 pseudo : 1; // bit <15> + UINT32 funcblk : 8; // bits <23:16> + UINT32 boxtype : 8; // bits <31:24> + } Bits; + UINT32 Data; +} CSR_OFFSET; + + +// +// Format of CSR register offset passed to helper functions. +// This must be kept in sync with the CSR XML parser tool that generates CSR offset definitions in the CSR header files. +// +#define PCI_REG_ADDR(Bus,Device,Function,Offset) \ + (((Offset) & 0xff) | (((Function) & 0x07) << 8) | (((Device) & 0x1f) << 11) | (((Bus) & 0xff) << 16)) +#define PCIE_REG_ADDR(Bus,Device,Function,Offset) \ + (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20)) + +#endif // _CPU_PCI_ACCESS_H_ diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/ProcMemInit/Chip/Include/CpuPciAccessCommon.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/ProcMemInit/Chip/Include/CpuPciAccessCommon.h new file mode 100644 index 0000000000..b949d7073f --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/ProcMemInit/Chip/Include/CpuPciAccessCommon.h @@ -0,0 +1,83 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _CPU_PCI_ACCESS_COMMON_H_ +#define _CPU_PCI_ACCESS_COMMON_H_ + +#include + +/** + + Indetifies the bus number for given SocId & BoxType + + @param host - Pointer to sysHost, the system host (root) structure + @param SocId - CPU Socket Node number (Socket ID) + @param BoxType - Box Type; values come from CpuPciAccess.h + @param BoxInst - IIO PCIE Box Instance + @param FuncBlk - Function Block within IIO + @param CpuCsrAccessVar - Pointer to CSR access data + + @retval (UINT32) PCI bus number + +**/ +UINT32 +GetBusNumber ( + PSYSHOST host, + UINT8 SocId, + UINT8 BoxType, + UINT8 BoxInst, + UINT8 FuncBlk, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar + ); + +/** + + Indetifies the device number for given SocId & BoxType + + @param host - Pointer to sysHost, the system host (root) structure + @param BoxType - Box Type; values come from CpuPciAccess.h + @param BoxInst - IIO PCIE Box Instance + @param FuncBlk - Function Block within IIO + @param CpuCsrAccessVar - Pointer to CSR access data + + @retval (UINT32) PCI device number + +**/ +UINT32 +GetDeviceNumber ( + PSYSHOST host, + UINT8 BoxType, + UINT8 BoxInst, + UINT8 FuncBlk, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar + ); + +/** + + Indetifies the function number for given SocId & BoxType + + @param host - Pointer to sysHost, the system host (root) structure + @param BoxType - Box Type; values come from CpuPciAccess.h + @param BoxInst - IIO PCIE Box Instance + @param FuncBlk - Function Block within IIO + @param CpuCsrAccessVar - Pointer to CSR access data + + @retval (UINT32) PCI function number + +**/ +UINT32 +GetFunctionNumber ( + PSYSHOST host, + UINT8 BoxType, + UINT8 BoxInst, + UINT8 FuncBlk, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar + ); + +#endif // _CPU_PCI_ACCESS_COMMON_H_ + + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/ProcMemInit/Chip/Include/Rc_Revision.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/ProcMemInit/Chip/Include/Rc_Revision.h new file mode 100644 index 0000000000..8f8e123f3a --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/ProcMemInit/Chip/Include/Rc_Revision.h @@ -0,0 +1,13 @@ +/** @file + Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// Declarations and directives +// ------------------------------------- +// Reference Code (RC) revision in BCD format: +// [31:20] = Major revision number +// [19:12] = Minor revision number +// [11:0] = Release Candidate number / Reserved +#define RC_REVISION 0x06104402 diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/UsraAccessLib/CsrAccess.c b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/UsraAccessLib/CsrAccess.c new file mode 100644 index 0000000000..ef179d9bae --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/UsraAccessLib/CsrAccess.c @@ -0,0 +1,118 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "UsraAccessLib.h" + +/** + This API get the CSR address from the given USRA Address. + + @param[in] Global Global pointer + @param[in] Virtual Virtual address + @param[in] Address A pointer of the address of the USRA Address Structure + @param[out] AlignedAddress A pointer of aligned address converted from USRA address + + @retval NONE +**/ +VOID +GetCsrAccessAddress ( + IN VOID *Global, + IN BOOLEAN Virtual, + IN USRA_ADDRESS *Address, + OUT UINTN *AlignedAddress + ) +{ + CsrGetPcieAlignAddress (Global, Virtual, Address, AlignedAddress); +} + +/** + This API performs 8-bit, 16-bit, 32-bit or 64-bit CSR silicon register read operations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + @param[in] Buffer A pointer of buffer for the value read from the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +CsrRegisterRead ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ) +{ + UINTN AlignedAddress = 0; + + GetCsrAccessAddress (NULL, 0, Address, &AlignedAddress); + + UsraRegAlignedRead((UINT32)Address->Attribute.AccessWidth, AlignedAddress, Buffer); + + return RETURN_SUCCESS; +} + +/** + This API performs 8-bit, 16-bit, 32-bit or 64-bit CSR silicon register write operations. + It transfers data from a naturally aligned data buffer into a register. + + @param[in] Address A pointer of the address of the USRA Address Structure to be written + @param[in] Buffer A pointer of buffer for the value write to the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +CsrRegisterWrite ( + IN USRA_ADDRESS *Address, + OUT VOID *Buffer + ) +{ + UINTN AlignedAddress = 0; + + GetCsrAccessAddress (NULL, 0, Address, &AlignedAddress); + + UsraRegAlignedWrite((UINT32)Address->Attribute.AccessWidth, AlignedAddress, Buffer); + + if (FeaturePcdGet (PcdUsraSupportS3)) + { + if(Address->Attribute.S3Enable) + { + S3BootScriptSaveMemWrite ((S3_BOOT_SCRIPT_LIB_WIDTH)Address->Attribute.AccessWidth, (UINT64)AlignedAddress, 1, Buffer); + } + } + + return RETURN_SUCCESS; +} + +/** + This API performs 8-bit, 16-bit, 32-bit or 64-bit CSR silicon register AND then OR operations. It read data from a + register, And it with the AndBuffer, then Or it with the OrBuffer, and write the result back to the register + + @param[in] Address A pointer of the address of the silicon register to be written + @param[in] AndBuffer A pointer of buffer for the value used for AND operation + A NULL pointer means no AND operation. RegisterModify() equivalents to RegisterOr() + @param[in] OrBuffer A pointer of buffer for the value used for OR operation + A NULL pointer means no OR operation. RegisterModify() equivalents to RegisterAnd() + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +CsrRegisterModify ( + IN USRA_ADDRESS *Address, + IN VOID *AndBuffer, + IN VOID *OrBuffer + ) +{ + + UINT64 Data; + UINT8 WidthTable[] = {1,2,4,8}; + UINTN AlignedAddress = 0; + + GetCsrAccessAddress (NULL, 0, Address, &AlignedAddress); + + UsraRegAlignedRead((UINT32)Address->Attribute.AccessWidth, AlignedAddress, &Data); + DataAndOr (&Data, AndBuffer, OrBuffer, WidthTable[(UINT8)Address->Attribute.AccessWidth]); + UsraRegAlignedWrite((UINT32)Address->Attribute.AccessWidth, AlignedAddress, &Data); + + return RETURN_SUCCESS; +} diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/UsraAccessLib/PcieAccess.c b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/UsraAccessLib/PcieAccess.c new file mode 100644 index 0000000000..c8df71a3f9 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/UsraAccessLib/PcieAccess.c @@ -0,0 +1,354 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "UsraAccessLib.h" + +#define MAX_IO_PORT_ADDRESS 0xFFFF + +// +// Lookup table for increment values based on transfer widths +// +UINT8 mInStride[] = { + 1, // UsraWidth8 + 2, // UsraWidth16 + 4, // UsraWidth32 + 8, // UsraWidth64 + 0, // UsraWidthFifo8 + 0, // UsraWidthFifo16 + 0, // UsraWidthFifo32 + 0, // UsraWidthFifo64 + 1, // UsraWidthFill8 + 2, // UsraWidthFill16 + 4, // UsraWidthFill32 + 8 // UsraWidthFill64 +}; + +// +// Lookup table for increment values based on transfer widths +// +UINT8 mOutStride[] = { + 1, // UsraWidth8 + 2, // UsraWidth16 + 4, // UsraWidth32 + 8, // UsraWidth64 + 1, // UsraWidthFifo8 + 2, // UsraWidthFifo16 + 4, // UsraWidthFifo32 + 8, // UsraWidthFifo64 + 0, // UsraWidthFill8 + 0, // UsraWidthFill16 + 0, // UsraWidthFill32 + 0 // UsraWidthFill64 +}; + + +/** + This API gets the Pcie address from the given USRA Address. + + @param[in] Global Global pointer + @param[in] Virtual Virtual address + @param[in] Address A pointer of the address of the USRA Address Structure + @param[out] AlignedAddress A pointer of aligned address converted from USRA address + + @retval NONE +**/ +VOID +GetPcieAccessAddress ( + IN VOID *Global, + IN BOOLEAN Virtual, + IN USRA_ADDRESS *Address, + OUT UINTN *AlignedAddress + ) +{ + INTN MmCfgBase; + + MmCfgBase = GetPcieSegMmcfgBaseAddress(Address); + // TODO: add Error Check for NULL later + *AlignedAddress = MmCfgBase + (UINTN)(Address->Attribute.RawData32[0] & 0x0fffffff); +} + +/** + This API performs 8-bit, 16-bit, 32-bit or 64-bit Pcie silicon register read operations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + @param[in] Buffer A pointer of buffer for the value read from the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +PcieRegisterRead ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ) +{ + UINTN AlignedAddress; + + GetPcieAccessAddress (NULL, 0, Address, &AlignedAddress); + UsraRegAlignedRead((UINT32)Address->Attribute.AccessWidth, AlignedAddress, Buffer); + + return RETURN_SUCCESS; +} + +/** + Check parameters to PcieBlkRegisterRead() function request. + + The I/O operations are carried out exactly as requested. The caller is responsible + for satisfying any alignment and I/O width restrictions that a PI System on a + platform might require. For example on some platforms, width requests of + UsraWidth64 do not work. Misaligned buffers, on the other hand, will + be handled by the driver. + + @param[in] MmioOperation TRUE for an MMIO operation, FALSE for I/O Port operation. + @param[in] Width Signifies the width of the I/O or Memory operation. + @param[in] Address The base address of the I/O operation. + @param[in] Count The number of I/O operations to perform. The number of + bytes moved is Width size * Count, starting at Address. + @param[in] Buffer For read operations, the destination buffer to store the results. + For write operations, the source buffer from which to write data. + + @retval EFI_SUCCESS The parameters for this request pass the checks. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width. + @retval EFI_UNSUPPORTED The address range specified by Address, Width, + and Count is not valid for this PI system. + +**/ +STATIC +RETURN_STATUS +CpuIoCheckParameter ( + IN BOOLEAN MmioOperation, + IN USRA_ACCESS_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN VOID *Buffer + ) +{ + UINT64 MaxCount; + UINT64 Limit; + + // + // Check to see if Buffer is NULL + // + if (Buffer == NULL) { + return RETURN_INVALID_PARAMETER; + } + + // + // Check to see if Width is in the valid range + // + if ((UINT32)Width >= UsraWidthMaximum) { + return RETURN_INVALID_PARAMETER; + } + + // + // For FIFO type, the target address won't increase during the access, + // so treat Count as 1 + // + if (Width >= UsraWidthFifo8 && Width <= UsraWidthFifo64) { + Count = 1; + } + + // + // Check to see if Width is in the valid range for I/O Port operations + // + Width = (USRA_ACCESS_WIDTH) (Width & 0x03); + if (!MmioOperation && (Width == UsraWidth64)) { + return RETURN_INVALID_PARAMETER; + } + + // + // Check to see if Address is aligned + // + if ((Address & (UINT64)(mInStride[Width] - 1)) != 0) { + return RETURN_UNSUPPORTED; + } + + // + // Check to see if any address associated with this transfer exceeds the maximum + // allowed address. The maximum address implied by the parameters passed in is + // Address + Size * Count. If the following condition is met, then the transfer + // is not supported. + // + // Address + Size * Count > (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS) + 1 + // + // Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count + // can also be the maximum integer value supported by the CPU, this range + // check must be adjusted to avoid all oveflow conditions. + // + // The following form of the range check is equivalent but assumes that + // MAX_ADDRESS and MAX_IO_PORT_ADDRESS are of the form (2^n - 1). + // + Limit = (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS); + if (Count == 0) { + if (Address > Limit) { + return RETURN_UNSUPPORTED; + } + } else { + MaxCount = RShiftU64 (Limit, Width); + if (MaxCount < (Count - 1)) { + return RETURN_UNSUPPORTED; + } + if (Address > LShiftU64 (MaxCount - Count + 1, Width)) { + return RETURN_UNSUPPORTED; + } + } + + // + // Check to see if Buffer is aligned + // (IA-32 allows UINT64 and INT64 data types to be 32-bit aligned.) + // + if (((UINTN)Buffer & ((MIN (sizeof (UINTN), mInStride[Width]) - 1))) != 0) { + return RETURN_UNSUPPORTED; + } + + return RETURN_SUCCESS; +} + +/** + This API performs 8-bit, 16-bit, 32-bit or 64-bit Pcie block silicon register read operations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + @param[in] Buffer A pointer of buffer for the value read from the register + + @retval RETURN_SUCCESS The function completed successfully. + @retval Others Some error occurs when executing CpuIoCheckParameter function. +**/ +RETURN_STATUS +PcieBlkRegisterRead ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ) +{ + UINT8 InStride; + UINT8 OutStride; + RETURN_STATUS Status; + UINTN AlignedAddress; + UINT32 ReadCount = Address->PcieBlk.Count; + UINT8 *UINT8Buffer; + + GetPcieAccessAddress (NULL, 0, Address, &AlignedAddress); + Status = CpuIoCheckParameter (TRUE, Address->Attribute.AccessWidth, AlignedAddress, ReadCount, Buffer); + if (RETURN_ERROR (Status)) { + return Status; + } + + InStride = mInStride[Address->Attribute.AccessWidth]; + OutStride = mOutStride[Address->Attribute.AccessWidth]; + for (UINT8Buffer = Buffer; ReadCount > 0; AlignedAddress += InStride, UINT8Buffer += OutStride, ReadCount--) { + UsraRegAlignedRead((USRA_ACCESS_WIDTH) (Address->Attribute.AccessWidth & 0x03), AlignedAddress, (VOID *)UINT8Buffer); + } + + return RETURN_SUCCESS; +} + +/** + This API performs 8-bit, 16-bit, 32-bit or 64-bit Pcie silicon register write operations. + It transfers data from a naturally aligned data buffer into a register. + + @param[in] Address A pointer of the address of the USRA Address Structure to be written + @param[in] Buffer A pointer of buffer for the value write to the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +PcieRegisterWrite ( + IN USRA_ADDRESS *Address, + OUT VOID *Buffer + ) +{ + UINTN AlignedAddress; + + GetPcieAccessAddress(NULL, 0, Address, &AlignedAddress); + UsraRegAlignedWrite((UINT32)Address->Attribute.AccessWidth, AlignedAddress, Buffer); + + if (FeaturePcdGet (PcdUsraSupportS3)) + { + if(Address->Attribute.S3Enable) + { + S3BootScriptSaveMemWrite ((S3_BOOT_SCRIPT_LIB_WIDTH)Address->Attribute.AccessWidth, (UINT64)AlignedAddress, 1, Buffer); + } + } + + return RETURN_SUCCESS; +} + +/** + This API performs 8-bit, 16-bit, 32-bit or 64-bit Pcie block silicon register write operations. + It transfers data from a naturally aligned data buffer into a register. + + @param[in] Address A pointer of the address of the USRA Address Structure to be written + @param[in] Buffer A pointer of buffer for the value write to the register + + @retval RETURN_SUCCESS The function completed successfully. + @retval Others Some error occurs when executing CpuIoCheckParameter function. +**/ +RETURN_STATUS +PcieBlkRegisterWrite ( + IN USRA_ADDRESS *Address, + OUT VOID *Buffer + ) +{ + UINT8 InStride; + UINT8 OutStride; + RETURN_STATUS Status; + UINTN AlignedAddress; + UINT32 WriteCount = Address->PcieBlk.Count; + UINT8 *UINT8Buffer; + + GetPcieAccessAddress (NULL, 0, Address, &AlignedAddress); + Status = CpuIoCheckParameter (TRUE, Address->Attribute.AccessWidth, AlignedAddress, WriteCount, Buffer); + if (RETURN_ERROR (Status)) { + return Status; + } + + InStride = mInStride[Address->Attribute.AccessWidth]; + OutStride = mOutStride[Address->Attribute.AccessWidth]; + for (UINT8Buffer = Buffer; WriteCount > 0; AlignedAddress += InStride, UINT8Buffer += OutStride, WriteCount--) { + UsraRegAlignedWrite((USRA_ACCESS_WIDTH) (Address->Attribute.AccessWidth & 0x03), AlignedAddress, (VOID *)UINT8Buffer); + + if (FeaturePcdGet (PcdUsraSupportS3)) { + if(Address->Attribute.S3Enable) { + S3BootScriptSaveMemWrite ((S3_BOOT_SCRIPT_LIB_WIDTH)(Address->Attribute.AccessWidth & 0x03), (UINT64)AlignedAddress, 1, (VOID *)UINT8Buffer); + } + } + } + + return RETURN_SUCCESS; +} + +/** + This API performs 8-bit, 16-bit, 32-bit or 64-bit Pcie silicon register AND then OR operations. It read data from a + register, And it with the AndBuffer, then Or it with the OrBuffer, and write the result back to the register + + @param[in] Address A pointer of the address of the silicon register to be modified + @param[in] AndBuffer A pointer of buffer for the value used for AND operation + A NULL pointer means no AND operation. RegisterModify() equivalents to RegisterOr() + @param[in] OrBuffer A pointer of buffer for the value used for OR operation + A NULL pointer means no OR operation. RegisterModify() equivalents to RegisterAnd() + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +PcieRegisterModify ( + IN USRA_ADDRESS *Address, + IN VOID *AndBuffer, + IN VOID *OrBuffer + ) +{ + UINT64 Data; + UINT8 WidthTable[] = {1,2,4,8}; + + PcieRegisterRead(Address, &Data); + DataAndOr (&Data, AndBuffer, OrBuffer, WidthTable[(UINT8)Address->Attribute.AccessWidth]); + PcieRegisterWrite(Address, &Data); + + return RETURN_SUCCESS; +} + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/UsraAccessLib/UsraAccessLib.c b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/UsraAccessLib/UsraAccessLib.c new file mode 100644 index 0000000000..d67d04a0cf --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/UsraAccessLib/UsraAccessLib.c @@ -0,0 +1,235 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "UsraAccessLib.h" + +GET_ALLIGNED_ACCESS_ADDRESS mAccessAddrPtr[] = +{ + &GetPcieAccessAddress, // AddrTypePCIE + &GetPcieAccessAddress, // AddrTypePCIEBLK + &GetCsrAccessAddress, // AddrTypeCSR +}; + +REGISTER_READ mRegisterReadPtr[] = +{ + &PcieRegisterRead, // AddrTypePCIE + &PcieBlkRegisterRead, // AddrTypePCIEBLK + &CsrRegisterRead, // AddrTypeCSR +}; + +REGISTER_WRITE mRegisterWritePtr[] = +{ + &PcieRegisterWrite, // AddrTypePCIE + &PcieBlkRegisterWrite, // AddrTypePCIEBLK + &CsrRegisterWrite, // AddrTypeCSR +}; + +REGISTER_MODIFY mRegisterModifyPtr[] = +{ + &PcieRegisterModify, // AddrTypePCIE + &PcieRegisterModify, // AddrTypePCIEBLK + &CsrRegisterModify, // AddrTypeCSR +}; + +/** + Perform MMIO read + + @param[in] AccessWidth Access Width + @param[in] AlignedAddress An address to be read out + @param[in] Buffer A pointer of buffer contains the data to be read out + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +UsraRegAlignedRead ( + IN UINT32 AccessWidth, + IN UINTN AlignedAddress, + OUT VOID *Buffer + ) +{ + switch (AccessWidth) + { + case UsraWidth8: + *((UINT8*)Buffer) = MmioRead8 (AlignedAddress); + break; + case UsraWidth16: + *((UINT16*)Buffer) = MmioRead16 (AlignedAddress); + break; + case UsraWidth32: + *((UINT32*)Buffer) = MmioRead32 (AlignedAddress); + break; + default: + *((UINT64*)Buffer) = MmioRead64 (AlignedAddress); + break; + } + + return RETURN_SUCCESS; +}; + +/** + Perform MMIO write + + @param[in] AccessWidth Access Width + @param[in] AlignedAddress An address to be written + @param[in] Buffer A pointer of buffer contains the data to be written + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +UsraRegAlignedWrite ( + IN UINT32 AccessWidth, + IN UINTN AlignedAddress, + OUT VOID *Buffer + ) +{ + switch (AccessWidth) + { + case UsraWidth8: + MmioWrite8 (AlignedAddress,*((UINT8*)Buffer)); + break; + case UsraWidth16: + MmioWrite16 (AlignedAddress,*((UINT16*)Buffer)); + break; + case UsraWidth32: + MmioWrite32 (AlignedAddress,*((UINT32*)Buffer)); + break; + default: + MmioWrite64 (AlignedAddress, *((UINT64*)Buffer)); + break; + } + return RETURN_SUCCESS; +} + +/** + Perform AND then OR operations for a input data + + @param[in out] Data A pointer of the address of the register to be modified + @param[in] AndBuffer A pointer of buffer for the value used for AND operation + A NULL pointer means no AND operation. RegisterModify() equivalents to RegisterOr() + @param[in] OrBuffer A pointer of buffer for the value used for OR operation + A NULL pointer means no OR operation. RegisterModify() equivalents to RegisterAnd() + @param[in] NumOfByte NumOfByte Count of byte data to be performed + + @retval NONE +**/ +VOID +DataAndOr ( + IN UINT64 *Data, + IN VOID *AndBuffer, + IN VOID *OrBuffer, + IN UINT8 NumOfByte +) +{ + union{ + UINT64 QW; + UINT8 Byte[8]; + } Buffer; + UINT8 AndData[8], OrData[8], i; + + Buffer.QW = *Data; + for(i=0;iAttribute.AddrType] (NULL, 0, Address, &AlignedAddress); + + return AlignedAddress; +}; + +/** + This API performs 8-bit, 16-bit, 32-bit or 64-bit silicon register read operations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + @param[in] Buffer A pointer of buffer for the value read from the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +EFIAPI +RegisterRead ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ) +{ + return mRegisterReadPtr[Address->Attribute.AddrType] (Address, Buffer); +}; + +/** + This API performs 8-bit, 16-bit, 32-bit or 64-bit silicon register write operations. + It transfers data from a naturally aligned data buffer into a silicon register. + + @param[in] Address A pointer of the address of the USRA Address Structure to be written + @param[in] Buffer A pointer of buffer for the value write to the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +EFIAPI +RegisterWrite ( + IN USRA_ADDRESS *Address, + OUT VOID *Buffer + ) +{ + return mRegisterWritePtr[Address->Attribute.AddrType] (Address, Buffer); +}; + +/** + This API performs 8-bit, 16-bit, 32-bit or 64-bit silicon register AND then OR operations. It read data from a + register, And it with the AndBuffer, then Or it with the OrBuffer, and write the result back to the register + + @param[in] Address A pointer of the address of the silicon register to be written + @param[in] AndBuffer A pointer of buffer for the value used for AND operation + A NULL pointer means no AND operation. RegisterModify() equivalents to RegisterOr() + @param[in] OrBuffer A pointer of buffer for the value used for OR operation + A NULL pointer means no OR operation. RegisterModify() equivalents to RegisterAnd() + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +EFIAPI +RegisterModify ( + IN USRA_ADDRESS *Address, + IN VOID *AndBuffer, + IN VOID *OrBuffer + ) +{ + return mRegisterModifyPtr[Address->Attribute.AddrType] (Address, AndBuffer, OrBuffer); +}; diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/UsraAccessLib/UsraAccessLib.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/UsraAccessLib/UsraAccessLib.h new file mode 100644 index 0000000000..b699a71683 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/UsraAccessLib/UsraAccessLib.h @@ -0,0 +1,257 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __USRA_ACCESS_LIB_H__ +#define __USRA_ACCESS_LIB_H__ + +#include +#include +#include +#include +#include +#include +#include + +// +// Get Aligned Access Address +// +typedef + VOID + (EFIAPI *GET_ALLIGNED_ACCESS_ADDRESS) (VOID*, BOOLEAN, USRA_ADDRESS*, UINTN*); + +// +// Register Read +// +typedef + RETURN_STATUS + (EFIAPI *REGISTER_READ) (USRA_ADDRESS *, VOID *); + +// +// Register Write +// +typedef + RETURN_STATUS + (EFIAPI *REGISTER_WRITE) (USRA_ADDRESS *, VOID *); + +// +// Register Write +// +typedef + RETURN_STATUS + (EFIAPI *REGISTER_MODIFY) (USRA_ADDRESS *, VOID *, VOID *); + +/** + This API get the Pcie address from the given USRA Address. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + + @retval NONE +**/ +VOID +GetPcieAccessAddress ( + IN VOID *Global, + IN BOOLEAN Virtual, + IN USRA_ADDRESS *Address, + OUT UINTN *AlignedAddress + ); + +/** + This API get the CSR address from the given USRA Address. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + @param[in] Buffer A pointer of buffer for the value read from the register + + @retval NONE +**/ +VOID +GetCsrAccessAddress ( + IN VOID *Global, + IN BOOLEAN Virtual, + IN USRA_ADDRESS *Address, + OUT UINTN *AlignedAddress + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit Pcie silicon register read operations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + @param[in] Buffer A pointer of buffer for the value read from the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +PcieRegisterRead ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit Pcie block silicon register read operations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + @param[in] Buffer A pointer of buffer for the value read from the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +PcieBlkRegisterRead ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit CSR silicon register read operations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + @param[in] Buffer A pointer of buffer for the value read from the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +CsrRegisterRead ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit Pcie silicon register write operations. + It transfers data from a naturally aligned data buffer into a register. + + @param[in] Address A pointer of the address of the USRA Address Structure to be written + @param[in] Buffer A pointer of buffer for the value write to the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +PcieRegisterWrite ( + IN USRA_ADDRESS *Address, + OUT VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit Pcie block silicon register write operations. + It transfers data from a naturally aligned data buffer into a register. + + @param[in] Address A pointer of the address of the USRA Address Structure to be written + @param[in] Buffer A pointer of buffer for the value write to the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +PcieBlkRegisterWrite ( + IN USRA_ADDRESS *Address, + OUT VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit CSR silicon register write operations. + It transfers data from a naturally aligned data buffer into a register. + + @param[in] Address A pointer of the address of the USRA Address Structure to be written + @param[in] Buffer A pointer of buffer for the value write to the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +CsrRegisterWrite ( + IN USRA_ADDRESS *Address, + OUT VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit Pcie silicon register AND then OR operations. It read data from a + register, And it with the AndBuffer, then Or it with the OrBuffer, and write the result back to the register + + @param[in] Address A pointer of the address of the silicon register to be modified + @param[in] AndBuffer A pointer of buffer for the value used for AND operation + A NULL pointer means no AND operation. RegisterModify() equivalents to RegisterOr() + @param[in] OrBuffer A pointer of buffer for the value used for OR operation + A NULL pointer means no OR operation. RegisterModify() equivalents to RegisterAnd() + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +PcieRegisterModify ( + IN USRA_ADDRESS *Address, + IN VOID *AndBuffer, + IN VOID *OrBuffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit CSR silicon register AND then OR operations. It read data from a + register, And it with the AndBuffer, then Or it with the OrBuffer, and write the result back to the register + + @param[in] Address A pointer of the address of the silicon register to be modified + @param[in] AndBuffer A pointer of buffer for the value used for AND operation + A NULL pointer means no AND operation. RegisterModify() equivalents to RegisterOr() + @param[in] OrBuffer A pointer of buffer for the value used for OR operation + A NULL pointer means no OR operation. RegisterModify() equivalents to RegisterAnd() + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +CsrRegisterModify ( + IN USRA_ADDRESS *Address, + IN VOID *AndBuffer, + IN VOID *OrBuffer + ); + +/** + Perform MMIO read + + @param[in] AccessWidth Access Width + @param[in] AlignedAddress An address to be read out + @param[in] Buffer A pointer of buffer contains the data to be read out + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +UsraRegAlignedRead ( + IN UINT32 AccessWidth, + IN UINTN AlignedAddress, + OUT VOID *Buffer + ); + +/** + Perform AND then OR operations for a input data + + @param[in out] Data A pointer of the address of the register to be modified + @param[in] AndBuffer A pointer of buffer for the value used for AND operation + A NULL pointer means no AND operation. RegisterModify() equivalents to RegisterOr() + @param[in] OrBuffer A pointer of buffer for the value used for OR operation + A NULL pointer means no OR operation. RegisterModify() equivalents to RegisterAnd() + @param[in] NumOfByte NumOfByte Count of byte data to be performed + + @retval NONE +**/ +VOID +DataAndOr ( + IN UINT64 *Data, + IN VOID *AndBuffer, + IN VOID *OrBuffer, + IN UINT8 NumOfByte +); + +/** + Perform MMIO write + + @param[in] AccessWidth Access Width + @param[in] AlignedAddress An address to be written + @param[in] Buffer A pointer of buffer contains the data to be written + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +UsraRegAlignedWrite ( + IN UINT32 AccessWidth, + IN UINTN AlignedAddress, + OUT VOID *Buffer + ); +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Library/UsraAccessLib/UsraAccessLib.inf b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/UsraAccessLib/UsraAccessLib.inf new file mode 100644 index 0000000000..e5f335539f --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Library/UsraAccessLib/UsraAccessLib.inf @@ -0,0 +1,62 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = SiliconAccessLib + FILE_GUID = 6CF9B31D-C5E9-4F5F-8030-78883D66CDF0 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = SiliconAccessLib + +## { 0x6cf9b31d, 0xc5e9, 0x4f5f, { 0x80, 0x30, 0x78, 0x88, 0x3d, 0x66, 0xcd, 0xf0 } }; + +[Sources] + UsraAccessLib.c + CsrAccess.c + PcieAccess.c + +################################################################################ +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +################################################################################ + +[Packages] + MdePkg/MdePkg.dec + PurleyRefreshSiliconPkg/SiPkg.dec + + +################################################################################ +# +# Library Class Section - list of Library Classes that are required for +# this module. +# +################################################################################ + +[LibraryClasses] + S3BootScriptLib + CsrToPcieLib + PcieAddrLib + HobLib + BaseLib + IoLib + +[Guids] + +[FeaturePcd] + gEfiCpRcPkgTokenSpaceGuid.PcdUsraSupportS3 + + + diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Override/IA32FamilyCpuPkg/IA32FamilyCpuPkg.dec b/Silicon/Intel/PurleyRefreshSiliconPkg/Override/IA32FamilyCpuPkg/IA32FamilyCpuPkg.dec new file mode 100644 index 0000000000..47ee1dde5a --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Override/IA32FamilyCpuPkg/IA32FamilyCpuPkg.dec @@ -0,0 +1,609 @@ +## @file +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + DEC_SPECIFICATION = 0x00010005 + PACKAGE_NAME = IA32FamilyCpuPkg + PACKAGE_GUID = 7dbe088f-2e1a-475c-b006-55632c2a5489 + PACKAGE_VERSION = 0.5 + +[Includes] + Include + +[LibraryClasses] + CpuConfigLib|Include/Library/CpuConfigLib.h + CpuOnlyResetLib|Include/Library/CpuOnlyResetLib.h + Socket775LgaLib|Include/Library/SocketLga775Lib.h + SocketLga1156Lib|Include/Library/SocketLga1156Lib.h + +[Guids] + ## Include/Guid/HtBistHob.h + gEfiHtBistHobGuid = { 0xBE644001, 0xE7D4, 0x48B1, { 0xB0, 0x96, 0x8B, 0xA0, 0x47, 0xBC, 0x7A, 0xE7 }} + ## Include/Guid/IA32FamilyCpuPkgTokenSpace.h + gEfiCpuTokenSpaceGuid = { 0x2ADA836D, 0x0A3D, 0x43D6, { 0xA2, 0x5A, 0x38, 0x45, 0xCA, 0xD2, 0xD4, 0x00 }} + + ## IntelFrameworkModule package token space guid + # Include/Guid/IntelFrameworkModulePkgTokenSpace.h + gEfiIntelFrameworkModulePkgTokenSpaceGuid = { 0xD3705011, 0xBC19, 0x4af7, { 0xBE, 0x16, 0xF6, 0x80, 0x30, 0x37, 0x8C, 0x15 }} + +[Ppis] + ## Include/Ppi/Cache.h + gPeiCachePpiGuid = { 0xC153205A, 0xE898, 0x4C24, { 0x86, 0x89, 0xA4, 0xB4, 0xBC, 0xC5, 0xC8, 0xA2 }} + +[Protocols] + gSmmCpuSyncProtocolGuid = { 0xd5950985, 0x8be3, 0x4b1c, { 0xb6, 0x3f, 0x95, 0xd1, 0x5a, 0xb3, 0xb6, 0x5f }} + gSmmCpuSync2ProtocolGuid = { 0x9db72e22, 0x9262, 0x4a18, { 0x8f, 0xe0, 0x85, 0xe0, 0x3d, 0xfa, 0x96, 0x73 }} + gIntelCpuPcdsSetDoneProtocolGuid = { 0xadb7b9e6, 0x70b7, 0x48d4, { 0xb6, 0xa5, 0x18, 0xfa, 0x15, 0xeb, 0xcd, 0x78 }} + +# +# [Error.gEfiCpuTokenSpaceGuid] +# 0x80000001 | Invalid value provided. +# + +[PcdsFeatureFlag] + ## Indicates if the support for Intel(R) Pentium(R) 4 (90nm) processor with HT + # Technology, Intel(R) Celeron D Processor, Intel(R) Pentium(R) 4 Processor + # Extreme Edition Supporting HT Technology Processor, and Mobile Intel(R) + # Pentium(R) 4 Processor supporting HT Technology is included in the CPU MP driver.

+ # TRUE - The support is included in the CPU MP driver.
+ # FALSE - The support is not included in the CPU MP driver.
+ # @Prompt CPU MP driver Processor Family. + gEfiCpuTokenSpaceGuid.PcdCpuPrescottFamilyFlag|TRUE|BOOLEAN|0x00000001 + ## Indicates if the support for Intel(R) Pentium(R) 4 (65nm) processor supporting HT Technology and Intel(R) + # Celeron D Processor is included in the CPU MP driver.

+ # TRUE - The support is included in the CPU MP driver.
+ # FALSE - The support is not included in the CPU MP driver.
+ # @Prompt CPU MP driver Intel(R) Pentium(R) 4 (65nm) processor supporting HT Technology and Intel(R) Celeron D Processor Support. + gEfiCpuTokenSpaceGuid.PcdCpuCedarMillFamilyFlag|TRUE|BOOLEAN|0x00000002 + ## Indicates if the support for Intel(R) Core(TM)2 Processor, Intel(R) Celeron(R) Processor, + # Intel (R) Pentium(R) Processor, and Intel(R) Xeon(R) Processor is included in + # the CPU MP driver.

+ # TRUE - The support is included in the CPU MP driver.
+ # FALSE - The support is not included in the CPU MP driver.
+ # @Prompt CPU MP driver Intel(R) Core(TM)2 Processor, Intel(R) Celeron(R) Processor, Intel (R) Pentium(R) Processor, and Intel(R) Xeon(R) Processor Support. + gEfiCpuTokenSpaceGuid.PcdCpuConroeFamilyFlag|TRUE|BOOLEAN|0x00000003 + ## Indicates if the support for Intel(R) Atom(TM) E6xx processor family is + # included in the CPU MP driver.

+ # TRUE - The support for Intel(R) Atom(TM) E6xx processor family is included in the CPU MP driver.
+ # FALSE - The support for Intel(R) Atom(TM) E6xx processor family is not included in the CPU MP driver.
+ # @Prompt CPU MP driver Intel(R) Atom(TM) E6xx processor family Support. + gEfiCpuTokenSpaceGuid.PcdCpuTunnelCreekFamilyFlag|FALSE|BOOLEAN|0x10000033 + ## Indicates if the support for Intel(R) Xeon(R) (45nm QPI) processor family is included + # in the CPU MP driver.

+ # TRUE - The support for Intel(R) Xeon(R) Processor family (45nm QPI)is included in the CPU MP driver.
+ # FALSE - The support for Intel(R) Xeon(R) Processor family (45nm QPI)is not included in the CPU MP driver.
+ # @Prompt CPU MP driver Intel(R) Xeon(R) Processor family (45nm QPI) Support. + gEfiCpuTokenSpaceGuid.PcdCpuNehalemFamilyFlag|TRUE|BOOLEAN|0x10000019 + ## Indicates if the support for Intel(R) Core(TM) 2xxx processor family is + # included in the CPU MP driver.

+ # TRUE - The support is included in the CPU MP driver.
+ # FALSE - The support is not included in the CPU MP driver.
+ # @Prompt CPU MP driver Intel(R) Xeon(R) Processor, Intel (R) Pentium(R) Processor, Intel(R) Core(TM) Processor, Intel(R) Celeron(R) Processor Support. + gEfiCpuTokenSpaceGuid.PcdCpuSandyBridgeFamilyFlag|TRUE|BOOLEAN|0x10000030 + ## Indicates if the support for Intel(R) Atom(TM) C2xxx processor family is + # included in the CPU MP driver.

+ # TRUE - The support is included in the CPU MP driver.
+ # FALSE - The support is not included in the CPU MP driver.
+ # @Prompt CPU MP driver Intel(R) Atom(TM) C2xxx processor family Support. + gEfiCpuTokenSpaceGuid.PcdCpuSilvermontFamilyFlag|FALSE|BOOLEAN|0x10000034 + ## Indicates if the support for Intel(R) Core(TM) 3xxx processor family is + # included in the CPU MP driver.

+ # TRUE - The support is included in the CPU MP driver.
+ # FALSE - The support is not included in the CPU MP driver.
+ # @Prompt CPU MP driver Intel(R) Xeon(R) Processor, Intel (R) Pentium(R) Processor, Intel(R) Core(TM) Processor Support. + gEfiCpuTokenSpaceGuid.PcdCpuIvyBridgeFamilyFlag|TRUE|BOOLEAN|0x10000031 + ## Indicates if the support for 4th Generation Intel(R) Core(TM) processor family is included in the CPU + # MP driver.

+ # TRUE - The support for 4th Generation Intel(R) Core(TM) processor is included in the CPU MP driver.
+ # FALSE - The support for 4th Generation Intel(R) Core(TM) processor is not included in the CPU MP driver.
+ # @Prompt CPU MP driver 4th Generation Intel(R) Core(TM) processor support. + gEfiCpuTokenSpaceGuid.PcdCpuHaswellFamilyFlag|TRUE|BOOLEAN|0x10000032 + ## Indicates if the support for 5th Generation Intel(R) Core(TM) processor family is included in the CPU + # MP driver.

+ # TRUE - The support for 5th Generation Intel(R) Core(TM) processor is included in the CPU MP driver.
+ # FALSE - The support for 5th Generation Intel(R) Core(TM) processor is not included in the CPU MP driver.
+ # @Prompt CPU MP driver 5th Generation Intel(R) Core(TM) processor support. + gEfiCpuTokenSpaceGuid.PcdCpuBroadwellFamilyFlag|FALSE|BOOLEAN|0x10000035 + ## Indicates if the support for 6th Generation Intel(R) Core(TM) processor family is included in the CPU + # MP driver.

+ # TRUE - The support for 6th Generation Intel(R) Core(TM) processor is included in the CPU MP driver.
+ # FALSE - The support for 6th Generation Intel(R) Core(TM) processor is not included in the CPU MP driver.
+ # @Prompt CPU MP driver 6th Generation Intel(R) Core(TM) processor support. + gEfiCpuTokenSpaceGuid.PcdCpuSkylakeFamilyFlag|FALSE|BOOLEAN|0x10000036 + ## Indicates if the support for 16nm Intel(R) Atom(TM) processor family is included in the CPU + # MP driver.

+ # TRUE - The support for 16nm Intel(R) Atom(TM) processor family is included in the CPU MP driver.
+ # FALSE - The support for 16nm Intel(R) Atom(TM) processor family is not included in the CPU MP driver.
+ # @Prompt CPU MP driver 16nm Intel(R) Atom(TM) processor family support. + gEfiCpuTokenSpaceGuid.PcdCpuGoldmontFamilyFlag|FALSE|BOOLEAN|0x10000037 + ## Indicates if the support for 14nm Intel(R) Xeon Phi(TM) Coprocessor family is included in the CPU MP driver.

+ # TRUE - The support for 14nm Intel(R) Xeon Phi(TM) Coprocessor family is included in the CPU MP driver.
+ # FALSE - The support for 14nm Intel(R) Xeon Phi(TM) Coprocessor family is not included in the CPU MP driver.
+ # @Prompt CPU MP driver 14nm Intel(R) Xeon Phi(TM) Coprocessor family support. + gEfiCpuTokenSpaceGuid.PcdCpuKnightsLandingFamilyFlag|FALSE|BOOLEAN|0x10000038 + ## Indicates if the support for thermal management features is included in the CPU MP driver. + # Thermal management features include TM1, TM2 and bi-directional PROCHOT.

+ # TRUE - The support for thermal management features is included in the CPU MP driver.
+ # FALSE - The support for thermal management features is not included in the CPU MP driver.
+ # @Prompt CPU MP driver thermal management features support. + gEfiCpuTokenSpaceGuid.PcdCpuThermalManagementFlag|TRUE|BOOLEAN|0x10000001 + ## Indicates if the support for enhanced C-State feature (including C1e) is included in the CPU MP driver.

+ # TRUE - The support for enhanced C-State feature is included in the CPU MP driver.
+ # FALSE - The support for enhanced C-State feature is not included in the CPU MP driver.
+ # @Prompt CPU MP driver enhanced C-State feature support. + gEfiCpuTokenSpaceGuid.PcdCpuEnhancedCStateFlag|TRUE|BOOLEAN|0x10000006 + ## Indicates if the support for Limit CPUID Maxval feature is included in the CPU MP driver.

+ # TRUE - The support for Limit CPUID Maxval feature is included in the CPU MP driver.
+ # FALSE - The support for Limit CPUID Maxval feature is not included in the CPU MP driver.
+ # @Prompt CPU MP driver Limit CPUID Maxval feature support. + gEfiCpuTokenSpaceGuid.PcdCpuMaxCpuIDValueLimitFlag|TRUE|BOOLEAN|0x10000008 + ## Indicates if the support for CPU microcode update is included in the CPU MP driver.

+ # TRUE - The support for CPU microcode update is included in the CPU MP driver.
+ # FALSE - The support for CPU microcode update is not included in the CPU MP driver.
+ # @Prompt CPU MP driver CPU microcode update support. + gEfiCpuTokenSpaceGuid.PcdCpuMicrocodeUpdateFlag|TRUE|BOOLEAN|0x1000000D + ## Indicates if the support for Machine Check feature is included in the CPU MP driver.

+ # TRUE - The support for Machine Check feature is included in the CPU MP driver.
+ # FALSE - The support for Machine Check feature is not included in the CPU MP driver.
+ # @Prompt CPU MP driver Machine Check feature support. + gEfiCpuTokenSpaceGuid.PcdCpuMachineCheckFlag|TRUE|BOOLEAN|0x1000000E + ## Indicates if the support for Select Least Featured Processor as BSP feature is included in the CPU MP driver.

+ # TRUE - The support for Select Least Featured Processor as BSP feature is included in the CPU MP driver.
+ # FALSE - The support for Select Least Featured Processor as BSP feature is not included in the CPU MP driver.
+ # @Prompt CPU MP driver Select Least Featured Processor as BSP feature support. + gEfiCpuTokenSpaceGuid.PcdCpuSelectLfpAsBspFlag|FALSE|BOOLEAN|0x1000000F + ## Indicates if BSP election in SMM will be enabled. + # If enabled, a BSP will be dynamically elected among all processors in each SMI. + # Otherwise, processor 0 is always as BSP in each SMI.

+ # TRUE - BSP election in SMM will be enabled.
+ # FALSE - BSP election in SMM will be disabled.
+ # @Prompt Enable BSP election in SMM. + gEfiCpuTokenSpaceGuid.PcdCpuSmmEnableBspElection|TRUE|BOOLEAN|0x32132106 + ## Indicates if the support for Enhanced Intel Speed Step (EIST) feature is included in the CPU MP driver.

+ # TRUE - The support for EIST feature is included in the CPU MP driver.
+ # FALSE - The support for EIST feature is not included in the CPU MP driver.
+ # @Prompt CPU MP driver EIST feature support. + gEfiCpuTokenSpaceGuid.PcdCpuEistFlag|TRUE|BOOLEAN|0x10000004 + ## Indicates if the support for VT-x and TXT initialization is included in the CPU MP driver. + # VT-x - Intel Virtualization Technology for IA-32 Intel Architecture. + # TXT - Intel(R) Trusted Execution Technology.

+ # TRUE - The support for VT and LT initialization is included in the CPU MP driver.
+ # FALSE - The support for VT and LT initialization is not included in the CPU MP driver.
+ # @Prompt CPU MP driver VT-x and TXT initialization support. + gEfiCpuTokenSpaceGuid.PcdCpuVtLtFlag|TRUE|BOOLEAN|0x10000007 + ## Indicates if the support for Execute Disable Bit feature is included in the CPU MP driver.

+ # TRUE - The support for Execute Disable Bit feature is included in the CPU MP driver.
+ # FALSE - The support for Execute Disable Bit feature is not included in the CPU MP driver.
+ # @Prompt CPU MP driver Execute Disable Bit feature support. + gEfiCpuTokenSpaceGuid.PcdCpuExecuteDisableBitFlag|TRUE|BOOLEAN|0x10000009 + ## Indicates if the support for Fast Strings for REP MOVS and REP STOS feature is included in the CPU MP driver.

+ # TRUE - The support for Fast Strings feature is included in the CPU MP driver.
+ # FALSE - The support for Fast Strings feature is not included in the CPU MP driver.
+ # @Prompt CPU MP driver Fast Strings feature support. + gEfiCpuTokenSpaceGuid.PcdCpuFastStringFlag|TRUE|BOOLEAN|0x10000012 + ## Indicates if the support for Hardware Prefetcher feature is included in the CPU MP driver.

+ # TRUE - The support for Hardware Prefetcher feature is included in the CPU MP driver.
+ # FALSE - The support for Hardware Prefetcher feature is not included in the CPU MP driver.
+ # @Prompt CPU MP driver Hardware Prefetcher feature support. + gEfiCpuTokenSpaceGuid.PcdCpuHardwarePrefetcherFlag|TRUE|BOOLEAN|0x10000013 + ## Indicates if the support for Adjacent Cache Line Prefetcher feature is included in the CPU MP driver.

+ # TRUE - The support for Adjacent Cache Line Prefetcher feature is included in the CPU MP driver.
+ # FALSE - The support for Adjacent Cache Line Prefetcher feature is not included in the CPU MP driver.
+ # @Prompt CPU MP driver Adjacent Cache Line Prefetcher feature support. + gEfiCpuTokenSpaceGuid.PcdCpuAdjacentCacheLinePrefetchFlag|TRUE|BOOLEAN|0x10000014 + ## Indicates if the support for DCU Streamer Prefetcher feature is included in the CPU MP driver.

+ # TRUE - The support for DCU Streamer Prefetcher feature is included in the CPU MP driver.
+ # FALSE - The support for DCU Streamer Prefetcher feature is not included in the CPU MP driver.
+ # @Prompt CPU MP driver DCU Streamer Prefetcher feature support. + gEfiCpuTokenSpaceGuid.PcdCpuDcuPrefetcherFlag|TRUE|BOOLEAN|0x10000015 + ## Indicates if the support for DCU IP Prefetcher feature is included in the CPU MP driver.

+ # TRUE - The support for DCU IP Prefetcher feature is included in the CPU MP driver.
+ # FALSE - The support for DCU IP Prefetcher feature is not included in the CPU MP driver.
+ # @Prompt CPU MP driver DCU IP Prefetcher feature support. + gEfiCpuTokenSpaceGuid.PcdCpuIpPrefetcherFlag|TRUE|BOOLEAN|0x10000016 + ## Indicates if the support for MLC Streamer Prefetcher feature is included in the CPU MP driver.

+ # TRUE - The support for MLC Streamer Prefetcher feature is included in the CPU MP driver.
+ # FALSE - The support for MLC Streamer Prefetcher feature is not included in the CPU MP driver.
+ # @Prompt CPU MP driver MLC Streamer Prefetcher feature support. + gEfiCpuTokenSpaceGuid.PcdCpuMlcStreamerPrefetcherFlag|TRUE|BOOLEAN|0x1000001D + ## Indicates if the support for MLC Spatial Prefetcher feature is included in the CPU MP driver.

+ # TRUE - The support for MLC Spatial Prefetcher feature is included in the CPU MP driver.
+ # FALSE - The support for MLC Spatial Prefetcher feature is not included in the CPU MP driver.
+ # @Prompt CPU MP driver MLC Spatial Prefetcher feature support. + gEfiCpuTokenSpaceGuid.PcdCpuMlcSpatialPrefetcherFlag|TRUE|BOOLEAN|0x1000001E + ## Indicates if the support for L2 Prefetcher feature is included in the CPU MP driver.

+ # TRUE - The support for L2 Prefetcher feature is included in the CPU MP driver.
+ # FALSE - The support for L2 Prefetcher feature is not included in the CPU MP driver.
+ # @Prompt CPU MP driver L2 Prefetcher feature support. + gEfiCpuTokenSpaceGuid.PcdCpuL2PrefetcherFlag|TRUE|BOOLEAN|0x1000002B + ## Indicates if the support for L1 Data Prefetcher feature is included in the CPU MP driver.

+ # TRUE - The support for L1 Data Prefetcher feature is included in the CPU MP driver.
+ # FALSE - The support for L1 Data Prefetcher feature is not included in the CPU MP driver.
+ # @Prompt CPU MP driver L1 Data Prefetcher feature support. + gEfiCpuTokenSpaceGuid.PcdCpuL1DataPrefetcherFlag|TRUE|BOOLEAN|0x1000002C + ## Indicates if the support for Pending Break Enable feature is included in the CPU MP driver. + # This feature uses the FERR#/PBE# pin when the processor is in the stop-clock state to signal the processor + # that an interrupt is pending and that the processor should return to normal operation to handle the interrupt.

+ # TRUE - The support for Pending Break Enable feature is included in the CPU MP driver.
+ # FALSE - The support for Pending Break Enable feature is not included in the CPU MP driver.
+ # @Prompt CPU MP driver Pending Break Enable feature support. + gEfiCpuTokenSpaceGuid.PcdCpuFerrSignalBreakFlag|TRUE|BOOLEAN|0x10000017 + ## Indicates if the support for Platform Enviroment Control Interface (PECI) feature is included in the CPU MP driver.

+ # TRUE - The support for PECI feature is included in the CPU MP driver.
+ # FALSE - The support for PECI feature is not included in the CPU MP driver.
+ # @Prompt CPU MP driver Platform Environment Control Interface (PECI) feature support. + gEfiCpuTokenSpaceGuid.PcdCpuPeciFlag|TRUE|BOOLEAN|0x10000018 + ## Indicates if the support for MONITOR (MONITOR and MWAIT instructions) feature is included in the CPU MP driver.

+ # TRUE - The support for MONITOR feature is included in the CPU MP driver.
+ # FALSE - The support for MONITOR feature is not included in the CPU MP driver.
+ # @Prompt CPU MP driver MONITOR feature support. + gEfiCpuTokenSpaceGuid.PcdCpuMonitorMwaitFlag|TRUE|BOOLEAN|0x1000001F + ## Indicates if the support for Three Strike Counter feature is included in the CPU MP driver.

+ # TRUE - The support for Three Strike Counter feature is included in the CPU MP driver.
+ # FALSE - The support for Three Strike Counter feature is not included in the CPU MP driver.
+ # @Prompt CPU MP driver Three Strike Counter feature support. + gEfiCpuTokenSpaceGuid.PcdCpuThreeStrikeCounterFlag|TRUE|BOOLEAN|0x10000020 + ## Indicates if the support for CPU Energy Efficiency Policy feature is included in the CPU MP driver.

+ # TRUE - The support for CPU Energy Efficiency Policy feature is included in the CPU MP driver.
+ # FALSE - The support for CPU Energy Efficiency Policy feature is not included in the CPU MP driver.
+ # @Prompt CPU MP driver CPU Energy Efficiency Policy feature support. + gEfiCpuTokenSpaceGuid.PcdCpuEnergyPerformanceBiasFlag|TRUE|BOOLEAN|0x10000021 + ## Indicates if the support for T-State feature is included in the CPU MP driver.

+ # TRUE - The support for T-State feature is included in the CPU MP driver.
+ # FALSE - The support for T-State feature is not included in the CPU MP driver.
+ # @Prompt CPU MP driver T-State feature support. + gEfiCpuTokenSpaceGuid.PcdCpuTStateFlag|TRUE|BOOLEAN|0x10000022 + ## Indicates if the support for Advanced Encryption Standard (AES) feature is included in the CPU MP driver.

+ # TRUE - The support for AES feature is included in the CPU MP driver.
+ # FALSE - The support for AES feature is not included in the CPU MP driver.
+ # @Prompt CPU MP driver Advanced Encryption Standard (AES) feature support. + gEfiCpuTokenSpaceGuid.PcdCpuAesFlag|TRUE|BOOLEAN|0x10000023 + ## Indicates if the support for Direct Cache Access (DCA) feature is included in the CPU MP driver.

+ # TRUE - The support for DCA feature is included in the CPU MP driver.
+ # FALSE - The support for DCA feature is not included in the CPU MP driver.
+ # @Prompt CPU MP driver Direct Cache Access (DCA) feature support. + gEfiCpuTokenSpaceGuid.PcdCpuDcaFlag|TRUE|BOOLEAN|0x10000024 + ## Indicates if the support for C-State feature is included in the CPU MP driver.

+ # TRUE - The support for C-State feature is included in the CPU MP driver.
+ # FALSE - The support for C-State feature is not included in the CPU MP driver.
+ # @Prompt CPU MP driver C-State feature support. + gEfiCpuTokenSpaceGuid.PcdCpuCStateFlag|TRUE|BOOLEAN|0x10000025 + ## Indicates if the support for x2APIC mode is included in the CPU MP driver.

+ # TRUE - The support for x2APIC mode is included in the CPU MP driver.
+ # FALSE - The support for x2APIC mode is not included in the CPU MP driver.
+ # @Prompt CPU MP driver x2APIC mode support. + gEfiCpuTokenSpaceGuid.PcdCpuX2ApicFlag|TRUE|BOOLEAN|0x10000026 + ## Indicates if the support for APIC TPR Update message feature is included in the CPU MP driver.

+ # TRUE - The support for APIC TPR Update message feature is included in the CPU MP driver.
+ # FALSE - The support for APIC TPR Update message feature is not included in the CPU MP driver.
+ # @Prompt CPU MP driver APIC TPR Update message feature support. + gEfiCpuTokenSpaceGuid.PcdCpuApicTprUpdateMessageFlag|TRUE|BOOLEAN|0x10000027 + ## Indicates if the support for Data Cache Unit (DCU) mode selection feature is included in the CPU MP driver.

+ # TRUE - The support for Data Cache Unit (DCU) mode selection feature is included in the CPU MP driver.
+ # FALSE - The support for Data Cache Unit (DCU) mode selection feature is not included in the CPU MP driver.
+ # @Prompt CPU MP driver DCU mode selection feature support. + gEfiCpuTokenSpaceGuid.PcdCpuDcuModeSelectionFlag|TRUE|BOOLEAN|0x10000028 + ## Indicates if the support for A20M Disable feature is included in the CPU MP driver. + # When the A20M #pin (Address 20 Mask) is asserted, the processor will mask physical address bit 20 (A20#). + # The A20M Disable can disable this legacy A20M feature.

+ # TRUE - The support for A20M Disable feature is included in the CPU MP driver.
+ # FALSE - The support for A20M Disable feature is not included in the CPU MP driver.
+ # @Prompt CPU MP driver A20M Disable feature support. + gEfiCpuTokenSpaceGuid.PcdCpuGateA20MDisableFlag|TRUE|BOOLEAN|0x1000001A + ## Indicates if the support for CPU socket ID re-assignment feature is included in the CPU MP driver. + # This feature allows re-assignment of CPU socket ID over hardware power-on default value, which in turn + # changes the APIC ID of logical processors in the CPU socket.

+ # TRUE - The support for CPU socket ID re-assignment feature is included in the CPU MP driver.
+ # FALSE - The support for CPU socket ID re-assignment feature is not included in the CPU MP driver.
+ # @Prompt CPU MP driver CPU socket ID re-assignment feature support. + gEfiCpuTokenSpaceGuid.PcdCpuSocketIdReassignmentFlag|FALSE|BOOLEAN|0x10000029 + ## Indicates if SMM Debug will be enabled. + # If enabled, hardware breakpoints in SMRAM can be set outside of SMM mode and take effect in SMM.

+ # TRUE - SMM Debug will be enabled.
+ # FALSE - SMM Debug will be disabled.
+ # @Prompt Enable SMM Debug. + gEfiCpuTokenSpaceGuid.PcdCpuSmmDebug|FALSE|BOOLEAN|0x1000001B + ## Indicates if SMM Stack Guard will be enabled. + # If enabled, stack overflow in SMM can be caught which eases debugging.

+ # TRUE - SMM Stack Guard will be enabled.
+ # FALSE - SMM Stack Guard will be disabled.
+ # @Prompt Enable SMM Stack Guard. + gEfiCpuTokenSpaceGuid.PcdCpuSmmStackGuard|FALSE|BOOLEAN|0x1000001C + ## Indicates if SMM Startup AP in a blocking fashion. + # TRUE - SMM Startup AP in a blocking fashion.
+ # FALSE - SMM Startup AP in a non-blocking fashion.
+ # @Prompt SMM Startup AP in a blocking fashion. + gEfiCpuTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp|FALSE|BOOLEAN|0x32132108 + ## Indicates if SMM Profile will be enabled. + # If enabled, instruction executions in and data accesses to memory outside of SMRAM will be logged. + # This PCD is only for validation purpose. It should be set to false in production.

+ # TRUE - SMM Profile will be enabled.
+ # FALSE - SMM Profile will be disabled.
+ # @Prompt Enable SMM Profile. + gEfiCpuTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE|BOOLEAN|0x32132109 + ## Indicates if the SMM profile log buffer is a ring buffer. + # If disabled, no additional log can be done when the buffer is full.

+ # TRUE - the SMM profile log buffer is a ring buffer.
+ # FALSE - the SMM profile log buffer is a normal buffer.
+ # @Prompt The SMM profile log buffer is a ring buffer. + gEfiCpuTokenSpaceGuid.PcdCpuSmmProfileRingBuffer|FALSE|BOOLEAN|0x3213210a + ## Indicates if SMM MP sync data resides in un-cached RAM.

+ # TRUE - SMM MP sync data will be resided in un-cached RAM.
+ # FALSE - SMM MP sync data will be resided in cached RAM.
+ # @Prompt SMM MP sync data resides in un-cached RAM. + gEfiCpuTokenSpaceGuid.PcdCpuSmmUncacheCpuSyncData|FALSE|BOOLEAN|0x3213210D + ## Indidates if CPU SMM hot-plug will be enabled.

+ # TRUE - SMM CPU hot-plug will be enabled.
+ # FALSE - SMM CPU hot-plug will be disabled.
+ # @Prompt SMM CPU hot-plug. + gEfiCpuTokenSpaceGuid.PcdCpuHotPlugSupport|FALSE|BOOLEAN|0x3213210C + ## Indidates if lock SMM Feature Control MSR.

+ # TRUE - SMM Feature Control MSR will be locked.
+ # FALSE - SMM Feature Control MSR will not be locked.
+ # @Prompt Lock SMM Feature Control MSR. + gEfiCpuTokenSpaceGuid.PcdCpuSmmFeatureControlMsrLock|TRUE|BOOLEAN|0x3213210B + ## Whether to set the IA untrusted lock feature of SAI-capable processors. + # TRUE - IA untrusted lock feature is supported.
+ # FALSE - IA untrusted lock feature is not supported.
+ # @Prompt Enabled the IA untrusted lock feature. + gEfiCpuTokenSpaceGuid.PcdCpuEnableIaUntrustedModeFlag|TRUE|BOOLEAN|0x3213210E + ## Indicates if the support for Peci Downstream Write feature is included in the CPU MP driver.

+ # TRUE - The support for Peci Downstream Write feature is included in the CPU MP driver.
+ # FALSE - The support for Peci Downstream Write feature is not included in the CPU MP driver.
+ # @Prompt CPU MP driver Peci Downstream Write feature support. + gEfiCpuTokenSpaceGuid.PcdCpuPeciDownstreamWriteFlag|TRUE|BOOLEAN|0x1000002E + + gEfiCpuTokenSpaceGuid.PcdCpuPCIeDownStreamPECIFlag|TRUE|BOOLEAN|0x1000002F + +[PcdsFixedAtBuild] + ## Specifies maximum number of PPIs provided by SecCore. + # @Prompt Maximum number of PPIs provided by SecCore. + gEfiCpuTokenSpaceGuid.PcdSecCoreMaxPpiSupported|0x6|UINT32|0x10001010 + +[PcdsFixedAtBuild, PcdsPatchableInModule] + ## Specifies maximum number of processors supported by the platform. + # @Prompt Maximum number of processors supported by the platform. + gEfiCpuTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|64|UINT32|0x30000002 + ## Specifies timeout value in microseconds for the BSP in SMM to wait for all APs to come into SMM. + # @Prompt AP synchronization timeout value in SMM. + gEfiCpuTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000000|UINT64|0x32132104 + ## Specifies stack size in bytes for each processor in SMM. + # @Prompt Processor stack size in SMM. + gEfiCpuTokenSpaceGuid.PcdCpuSmmStackSize|0x2000|UINT32|0x32132105 + ## Specifies buffer size in bytes to save SMM profile data. The value should be a multiple of 4KB. + # @Prompt SMM profile data buffer size. + gEfiCpuTokenSpaceGuid.PcdCpuSmmProfileSize|0x200000|UINT32|0x32132107 + ## Specifies the temporary RAM base address. + # @Prompt Temporary RAM base address. + gEfiCpuTokenSpaceGuid.PcdTemporaryRamBase|0xfef00000|UINT32|0x10001001 + ## Specifies the temporary RAM size in bytes. + # @Prompt Temporary RAM size. + gEfiCpuTokenSpaceGuid.PcdTemporaryRamSize|0x2000|UINT32|0x10001002 + ## Maximum number of processors in SEC (Not used). + # @Prompt Maximum number of processors in SEC. + gEfiCpuTokenSpaceGuid.PcdSecMaximumNumberOfProcessors|1|UINT32|0x10001000 + ## Specifies stack size in the temporary RAM. 0 means half of TemporaryRamSize. + # @Prompt Stack size in the temporary RAM. + gEfiCpuTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0|UINT32|0x10001003 + ## Indidates if SMM Code Access Check is enabled. + # If enabled, the SMM handler cannot execut the code outside ranges defined by SMRR/SMRR2. + # This PCD is suggested to TRUE in production image.

+ # TRUE - SMM Code Access Check will be enabled.
+ # FALSE - SMM Code Access Check will be disabled.
+ # @Prompt SMM Code Access Check. + gEfiCpuTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable|TRUE|BOOLEAN|0x60000013 + +[PcdsDynamicEx] + ## Specifies timeout value in microseconds for the BSP to detect all APs for the first time. + # @Prompt Timeout for the BSP to detect all APs for the first time. + gEfiCpuTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|50000|UINT32|0x30000001 + ## Specifies user's desired settings for enabling/disabling processor features, each bit corresponding to a specific feature. + # @Prompt User settings for enabling/disabling processor features. + gEfiCpuTokenSpaceGuid.PcdCpuProcessorFeatureUserConfiguration|0|UINT32|0x40000001 + ## Specifies desired settings for enabling/disabling processor features, each bit corresponding to a specific feature. + # @Prompt User extension1 settings for enabling/disabling processor features. + gEfiCpuTokenSpaceGuid.PcdCpuProcessorFeatureUserConfigurationEx1|0|UINT32|0x40000006 + ## Specifies the Energy efficiency policy when Energy Performance Bias feature is enabled. + # 0 - indicates preference to highest performance. + # 15 - indicates preference to maximize energy saving. + # @Prompt The Energy efficiency policy. + # @ValidRange 0x80000001 | 0 - 15 + gEfiCpuTokenSpaceGuid.PcdCpuEnergyPolicy|0x0|UINT8|0x60008000 + ## Specifies the 16-bit IO port base address of the LVL_2 register visible to software. + # @Prompt LVL_2 register IO port base address. + gEfiCpuTokenSpaceGuid.PcdCpuAcpiLvl2Addr|0x0|UINT16|0x60008001 + ## Specifies the package C-State limit. + # @Prompt The package C-State limit. + # @ValidRange 0x80000001 | 0 - 7 + gEfiCpuTokenSpaceGuid.PcdCpuPackageCStateLimit|0x0|UINT8|0x60008002 + ## Specifies the On-demand clock modulation duty cycle when T-State feature is enabled. + # @Prompt The encoded values for target duty cycle modulation. + # @ValidRange 0x80000001 | 0 - 15 + gEfiCpuTokenSpaceGuid.PcdCpuClockModulationDutyCycle|0x0|UINT8|0x60008003 + ## Indicates if HW Coordination is enabled when EIST feature is enabled.

+ # TRUE - HW Coordination will be enabled.
+ # FALSE - HW Coordination will be disabled.
+ # @Prompt Enable HW Coordination. + gEfiCpuTokenSpaceGuid.PcdCpuHwCoordination|FALSE|BOOLEAN|0x60008004 + ## Selects the DCU (Data Cache Unit) mode.

+ # 0 - 32-KB 8-way without ECC.
+ # 1 - 16-KB 4-way with ECC.
+ # @Prompt The DCU (Data Cache Unit) mode. + # @ValidRange 0x80000001 | 0 - 1 + gEfiCpuTokenSpaceGuid.PcdCpuDcuMode|0x0|UINT8|0x60008005 + +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] + ## Specifies stack size in bytes for each AP. + # @Prompt AP stack size. + gEfiCpuTokenSpaceGuid.PcdCpuApStackSize|0x8000|UINT32|0x30000003 + ## Indicates if the platform supports high power load line. + # @Prompt The platform supports high power load line. + gEfiCpuTokenSpaceGuid.PcdPlatformHighPowerLoadLineSupport|TRUE|BOOLEAN|0x60000001 + ## Platform dynamic Vid support (not used). + # @Prompt Platform dynamic Vid support. + gEfiCpuTokenSpaceGuid.PcdPlatformDynamicVidSupport|TRUE|BOOLEAN|0x60000002 + ## Indicates the platform type: desktop, mobile or server.

+ # 0 - desktop
+ # 1 - mobile
+ # 2 - server
+ # @Prompt Platform type. + # @ValidRange 0x80000001 | 0 - 2 + gEfiCpuTokenSpaceGuid.PcdPlatformType|0|UINT8|0x60000003 + ## Indicates the maximum CPU core frequency in the platform. + # @Prompt Maximum CPU core frequency in the platform. + gEfiCpuTokenSpaceGuid.PcdPlatformCpuMaxCoreFrequency|0x0|UINT32|0x60000004 + ## Platform CPU maximum FSB frequency (not used). + # @Prompt Platform CPU maximum FSB frequency. + gEfiCpuTokenSpaceGuid.PcdPlatformCpuMaxFsbFrequency|0x0|UINT32|0x60000005 + ## Specifies the base address of the first microcode Patch in the microcode Region. + # @Prompt Microcode Region base address. + gEfiCpuTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|0x60000009 + ## Specifies the size of the microcode Region. + # @Prompt Microcode Region size. + gEfiCpuTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0|UINT64|0x6000000A + ## Indicates if Intel Enhanced Debug (IED) will be enabled. + # Note that for some processors, IED is optional, but for others, IED is required.

+ # TRUE - IED will be enabled.
+ # FALSE - IED will be disabled.
+ # @Prompt Enable IED. + gEfiCpuTokenSpaceGuid.PcdCpuIEDEnabled|FALSE|BOOLEAN|0x6000000B + ## Specifies the IEDRAM size. + # Note that there is a minimum size requirement for a processor. + # @Prompt IEDRAM size. + gEfiCpuTokenSpaceGuid.PcdCpuIEDRamSize|0x20000|UINT32|0x6000000C + + ## Specifies the AP wait loop mode during POST. + # The value is defined as below.

+ # 1: ApInHltLoop, AP is in the Hlt-Loop state.
+ # 2: ApInMwaitLoop, AP is in the Mwait-Loop state.
+ # 3: ApInRunLoop, AP is in the Run-Loop state.
+ # @Prompt The AP wait loop mode. + # @ValidRange 0x80000001 | 1 - 3 + gEfiCpuTokenSpaceGuid.PcdCpuApLoopMode|1|UINT8|0x60008006 + ## Specifies the SMRR2 base address.

+ # @Prompt SMRR2 base address. + # @Expression 0x80000001 | (gEfiCpuTokenSpaceGuid.PcdCpuSmmSmrr2Base & 0xfff) == 0 + gEfiCpuTokenSpaceGuid.PcdCpuSmmSmrr2Base|0|UINT32|0x60000015 + ## Specifies the SMRR2 range size.

+ # @Prompt SMRR2 range size. + # @Expression 0x80000001 | (gEfiCpuTokenSpaceGuid.PcdCpuSmmSmrr2Size & 0xfff) == 0 + gEfiCpuTokenSpaceGuid.PcdCpuSmmSmrr2Size|0|UINT32|0x60000016 + ## Specifies the SMRR2 range cache type. + # If SMRR2 is used to map a flash/ROM based handler, it would be configured as WP.

+ # 5: WP(Write Protect).
+ # 6: WB(Write Back).
+ # @Prompt SMRR2 range cache type. + # @ValidList 0x80000001 | 5, 6 + gEfiCpuTokenSpaceGuid.PcdCpuSmmSmrr2CacheType|5|UINT8|0x60000017 + ## Indidates if SMM Delay feature is supported.

+ # TRUE - SMM Delay feature is supported.
+ # FALSE - SMM Delay feature is not supported.
+ # @Prompt SMM Delay feature. + gEfiCpuTokenSpaceGuid.PcdCpuSmmUseDelayIndication|TRUE|BOOLEAN|0x60000018 + ## Indidates if SMM Block feature is supported.

+ # TRUE - SMM Block feature is supported.
+ # FALSE - SMM Block feature is not supported.
+ # @Prompt SMM Block feature. + gEfiCpuTokenSpaceGuid.PcdCpuSmmUseBlockIndication|TRUE|BOOLEAN|0x60000019 + ## Indidates if SMM Enable/Disable feature is supported.

+ # TRUE - SMM Enable/Disable feature is supported.
+ # FALSE - SMM Enable/Disable feature is not supported.
+ # @Prompt SMM Enable/Disable feature. + gEfiCpuTokenSpaceGuid.PcdCpuSmmUseSmmEnableIndication|TRUE|BOOLEAN|0x6000001A + ## Specifies the TCC Activation Offset value.

+ # @Prompt TCC Activation Offset value. + gEfiCpuTokenSpaceGuid.PcdCpuTccActivationOffset|0|UINT8|0x6000001B + + +[PcdsDynamicEx] + ## Indidates if SMM Save State saved in MSRs. + # if enabled, SMM Save State will use the MSRs instead of the memory.

+ # TRUE - SMM Save State will use the MSRs.
+ # FALSE - SMM Save State will use the memory.
+ # @Prompt SMM Save State uses MSRs. + gEfiCpuTokenSpaceGuid.PcdCpuSmmMsrSaveStateEnable|FALSE|BOOLEAN|0x60000014 + ## Indidates if SMM PROT MODE feature is supported.

+ # TRUE - SMM PROT MODE feature is supported.
+ # FALSE - SMM PROT MODE feature is not supported.
+ # @Prompt SMM PROT MODE feature. + gEfiCpuTokenSpaceGuid.PcdCpuSmmProtectedModeEnable|FALSE|BOOLEAN|0x6000001C + gEfiCpuTokenSpaceGuid.PcdCpuCoreCStateValue|0x0|UINT8|0x60008009 + + ## Indicates processor feature capabilities, each bit corresponding to a specific feature. + # @Prompt Processor feature capabilities. + # @ValidList 0x80000001 | 0 + gEfiCpuTokenSpaceGuid.PcdCpuProcessorFeatureCapability|0|UINT32|0x40000002 + ## Specifies actual settings for processor features, each bit corresponding to a specific feature. + # @Prompt Actual processor feature settings. + # @ValidList 0x80000001 | 0 + gEfiCpuTokenSpaceGuid.PcdCpuProcessorFeatureSetting|0|UINT32|0x40000003 + ## Indicates processor feature capabilities, each bit corresponding to a specific feature. + # @Prompt Processor feature extension1 capabilities. + # @ValidList 0x80000001 | 0 + gEfiCpuTokenSpaceGuid.PcdCpuProcessorFeatureCapabilityEx1|0|UINT32|0x40000004 + ## Specifies actual settings for processor features, each bit corresponding to a specific feature. + # @Prompt Actual processor feature extension1 settings. + # @ValidList 0x80000001 | 0 + gEfiCpuTokenSpaceGuid.PcdCpuProcessorFeatureSettingEx1|0|UINT32|0x40000005 + ## Contains the pointer to CPU Configuration Context Buffer defined in the CpuConfigLib. + # @Prompt The pointer to CPU Configuration Context Buffer. + # @ValidList 0x80000001 | 0 + gEfiCpuTokenSpaceGuid.PcdCpuConfigContextBuffer|0x0|UINT64|0x50000001 + ## Used for a callback mechanism for the CPU MP driver. + # The CPU MP driver will set this PCD at pre-defined points. If there is callback function registered on it, + # the callback function will be triggered, and it may change the value of PcdCpuCallbackSignal. + # @Prompt PCD for CPU callback signal. + # @ValidList 0x80000001 | 0 + gEfiCpuTokenSpaceGuid.PcdCpuCallbackSignal|0x0|UINT8|0x50000002 + ## Platform CPU frequency lists (not used). + # @Prompt Platform CPU frequency lists. + gEfiCpuTokenSpaceGuid.PcdPlatformCpuFrequencyLists|0x0|UINT64|0x60000006 + ## Specifies the number of CPU sockets in the platform. + # @Prompt The number of CPU sockets in the platform. + gEfiCpuTokenSpaceGuid.PcdPlatformCpuSocketCount|0x0|UINT32|0x60000012 + ## Contains the pointer to a pointer array of which each item points to a unicode string of CPU socket name. + # @Prompt The name of each CPU socket. + # @ValidList 0x80000001 | 0 + gEfiCpuTokenSpaceGuid.PcdPlatformCpuSocketNames|0x0|UINT64|0x60000007 + ## Contains the pointer to a pointer array of which each item points to a unicode string of CPU asset tag. + # @Prompt The asset tag of each CPU socket. + # @ValidList 0x80000001 | 0 + gEfiCpuTokenSpaceGuid.PcdPlatformCpuAssetTags|0x0|UINT64|0x60000008 + ## Indicates if the current boot is a power-on reset.

+ # TRUE - Current boot is a power-on reset.
+ # FALSE - Current boot is not a power-on reset.
+ # @Prompt Current boot is a power-on reset. + gEfiCpuTokenSpaceGuid.PcdIsPowerOnReset|FALSE|BOOLEAN|0x6000000F + ## CPU page table address (not used). + # @Prompt CPU page table address. + gEfiCpuTokenSpaceGuid.PcdCpuPageTableAddress|0x0|UINT64|0x6000000E + ## Contains the pointer to a MTRR table buffer of structure MTRR_SETTINGS. + # @Prompt The pointer to a MTRR table buffer. + # @ValidList 0x80000001 | 0 + gEfiCpuTokenSpaceGuid.PcdCpuMtrrTableAddress|0x0|UINT64|0x6000000D + ## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA. + # @Prompt The pointer to a CPU S3 data buffer. + # @ValidList 0x80000001 | 0 + gEfiCpuTokenSpaceGuid.PcdCpuS3DataAddress|0x0|UINT64|0x60000010 + + ## Contains the pointer to a buffer where new socket IDs to be assigned are stored. + # @Prompt The pointer to a new socket ID buffer. +# gEfiCpuTokenSpaceGuid.PcdCpuSocketId|{0x0}|VOID*|0x60008007 + + ## Contains the pointer to a CPU Hot Plug Data structure if CPU hot-plug is supported. + # @Prompt The pointer to CPU Hot Plug Data. + # @ValidList 0x80000001 | 0 + gEfiCpuTokenSpaceGuid.PcdCpuHotPlugDataAddress|0x0|UINT64|0x60000011 + + ## Contains the pointer to a buffer where new socket IDs to be assigned are stored. + # @Prompt The pointer to a new socket ID buffer. + gEfiCpuTokenSpaceGuid.PcdCpuSocketId|{0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x1,0x0,0x0,0x0,0x1,0x0,0x0,0x0,0x2,0x0,0x0,0x0,0x2,0x0,0x0,0x0,0x3,0x0,0x0,0x0,0x3,0x0,0x0,0x0}|VOID*|0x60008007 + gEfiCpuTokenSpaceGuid.PcdCpuSmmRuntimeCtlHooks|FALSE|BOOLEAN|0x6000001D + +[PcdsFixedAtBuild, PcdsDynamic, PcdsDynamicEx, PcdsPatchableInModule] + gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdEbdaReservedMemorySize|0x8000|UINT32|0x30000005 diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Override/IA32FamilyCpuPkg/Include/Library/CpuConfigLib.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Override/IA32FamilyCpuPkg/Include/Library/CpuConfigLib.h new file mode 100644 index 0000000000..83daf1b06e --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Override/IA32FamilyCpuPkg/Include/Library/CpuConfigLib.h @@ -0,0 +1,667 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _CPU_CONFIG_LIB_H_ +#define _CPU_CONFIG_LIB_H_ + +#include +#include + +// +// Bits definition of PcdProcessorFeatureUserConfiguration, +// PcdProcessorFeatureCapability, and PcdProcessorFeatureSetting +// +#define PCD_CPU_HT_BIT 0x00000001 +#define PCD_CPU_CMP_BIT 0x00000002 +#define PCD_CPU_L2_CACHE_BIT 0x00000004 +#define PCD_CPU_L2_ECC_BIT 0x00000008 +#define PCD_CPU_VT_BIT 0x00000010 +#define PCD_CPU_LT_BIT 0x00000020 +#define PCD_CPU_EXECUTE_DISABLE_BIT 0x00000040 +#define PCD_CPU_L3_CACHE_BIT 0x00000080 +#define PCD_CPU_MAX_CPUID_VALUE_LIMIT_BIT 0x00000100 +#define PCD_CPU_FAST_STRING_BIT 0x00000200 +#define PCD_CPU_FERR_SIGNAL_BREAK_BIT 0x00000400 +#define PCD_CPU_PECI_BIT 0x00000800 +#define PCD_CPU_HARDWARE_PREFETCHER_BIT 0x00001000 +#define PCD_CPU_ADJACENT_CACHE_LINE_PREFETCH_BIT 0x00002000 +#define PCD_CPU_DCU_PREFETCHER_BIT 0x00004000 +#define PCD_CPU_IP_PREFETCHER_BIT 0x00008000 +#define PCD_CPU_MACHINE_CHECK_BIT 0x00010000 +#define PCD_CPU_THERMAL_MANAGEMENT_BIT 0x00040000 +#define PCD_CPU_EIST_BIT 0x00080000 +#define PCD_CPU_C1E_BIT 0x00200000 +#define PCD_CPU_C2E_BIT 0x00400000 +#define PCD_CPU_C3E_BIT 0x00800000 +#define PCD_CPU_C4E_BIT 0x01000000 +#define PCD_CPU_HARD_C4E_BIT 0x02000000 +#define PCD_CPU_DEEP_C4_BIT 0x04000000 +#define PCD_CPU_A20M_DISABLE_BIT 0x08000000 +#define PCD_CPU_MONITOR_MWAIT_BIT 0x10000000 +#define PCD_CPU_TSTATE_BIT 0x20000000 +#define PCD_CPU_TURBO_MODE_BIT 0x80000000 + +// +// Bits definition of PcdProcessorFeatureUserConfigurationEx1, +// PcdProcessorFeatureCapabilityEx1, and PcdProcessorFeatureSettingEx1 +// +#define PCD_CPU_C_STATE_BIT 0x00000001 +#define PCD_CPU_C1_AUTO_DEMOTION_BIT 0x00000002 +#define PCD_CPU_C3_AUTO_DEMOTION_BIT 0x00000004 +#define PCD_CPU_MLC_STREAMER_PREFETCHER_BIT 0x00000008 +#define PCD_CPU_MLC_SPATIAL_PREFETCHER_BIT 0x00000010 +#define PCD_CPU_THREE_STRIKE_COUNTER_BIT 0x00000020 +#define PCD_CPU_ENERGY_PERFORMANCE_BIAS_BIT 0x00000040 +#define PCD_CPU_DCA_BIT 0x00000080 +#define PCD_CPU_X2APIC_BIT 0x00000100 +#define PCD_CPU_AES_BIT 0x00000200 +#define PCD_CPU_APIC_TPR_UPDATE_MESSAGE_BIT 0x00000400 +#define PCD_CPU_SOCKET_ID_REASSIGNMENT_BIT 0x00000800 +#define PCD_CPU_PECI_DOWNSTREAM_WRITE_BIT 0x00001000 +#define PCD_CPU_ENABLE_IA_UNTRUSTED_MODE_BIT 0x00002000 +#define PCD_CPU_L2_PREFETCHER_BIT 0x00004000 +#define PCD_CPU_L1_DATA_PREFETCHER_BIT 0x00008000 +#define PCD_CPU_C1_AUTO_UNDEMOTION_BIT 0x00010000 +#define PCD_CPU_C3_AUTO_UNDEMOTION_BIT 0x00020000 + +// +// Value definition for PcdCpuCallbackSignal +// +#define CPU_BYPASS_SIGNAL 0x00000000 +#define CPU_DATA_COLLECTION_SIGNAL 0x00000001 +#define CPU_PROCESSOR_FEATURE_LIST_CONFIG_SIGNAL 0x00000002 +#define CPU_REGISTER_TABLE_TRANSLATION_SIGNAL 0x00000003 +#define CPU_PROCESSOR_SETTING_SIGNAL 0x00000004 +#define CPU_PROCESSOR_SETTING_END_SIGNAL 0x00000005 + +// CPU C State Settings +#define C3_ENABLE 0x02 +#define C6_ENABLE 0x03 +#define C7_ENABLE 0x04 +#define C8_ENABLE 0x05 +#define C9_ENABLE 0x06 +#define C10_ENABLE 0x07 + +typedef struct { + UINT32 RegEax; + UINT32 RegEbx; + UINT32 RegEcx; + UINT32 RegEdx; +} EFI_CPUID_REGISTER; + +// +// Enumeration of processor features +// +typedef enum { + Ht, + Cmp, + Vt, + ExecuteDisableBit, + L3Cache, + MaxCpuidValueLimit, + FastString, + FerrSignalBreak, + Peci, + HardwarePrefetcher, + AdjacentCacheLinePrefetch, + DcuPrefetcher, + IpPrefetcher, + ThermalManagement, + Eist, + BiDirectionalProchot, + Forcepr, + C1e, + C2e, + C3e, + C4e, + HardC4e, + DeepC4, + Microcode, + Microcode2, + MachineCheck, + GateA20MDisable, + MonitorMwait, + TState, + TurboMode, + CState, + C1AutoDemotion, + C3AutoDemotion, + MlcStreamerPrefetcher, + MlcSpatialPrefetcher, + ThreeStrikeCounter, + EnergyPerformanceBias, + Dca, + X2Apic, + Aes, + ApicTprUpdateMessage, + TccActivation, + PeciDownstreamWrite, + IaUntrustedMode, + L2Prefetcher, + L1DataPrefetcher, + C1AutoUndemotion, + C3AutoUndemotion, + Dbp, + PpinCtl, + CpuFeatureMaximum +} CPU_FEATURE_ID; + +// +// Structure for collected processor feature capability, +// and feature-specific attribute. +// +typedef struct { + BOOLEAN Capability; + VOID *Attribute; +} CPU_FEATURE_DATA; + +// +// Structure for collected CPUID data. +// +typedef struct { + EFI_CPUID_REGISTER *CpuIdLeaf; + UINTN NumberOfBasicCpuidLeafs; + UINTN NumberOfExtendedCpuidLeafs; + UINTN NumberOfCacheAndTlbCpuidLeafs; + UINTN NumberOfDeterministicCacheParametersCpuidLeafs; + UINTN NumberOfExtendedTopologyEnumerationLeafs; +} CPU_CPUID_DATA; + +typedef struct { + UINTN Ratio; + UINTN Vid; + UINTN Power; + UINTN TransitionLatency; + UINTN BusMasterLatency; +} FVID_ENTRY; + +// +// Miscellaneous processor data +// +typedef struct { + // + // Local Apic Data + // + UINT32 InitialApicID; ///< Initial APIC ID + UINT32 ApicID; ///< Current APIC ID + EFI_PHYSICAL_ADDRESS ApicBase; + UINT32 ApicVersion; + // + // Frequency data + // + UINTN IntendedFsbFrequency; + UINTN ActualFsbFrequency; + BOOLEAN FrequencyLocked; + UINTN MaxCoreToBusRatio; + UINTN MinCoreToBusRatio; + UINTN MaxTurboRatio; + UINTN MaxVid; + UINTN MinVid; + UINTN PackageTdp; + UINTN CoreTdp; + UINTN NumberOfPStates; + FVID_ENTRY *FvidTable; + // + // Config TDP data + // + UINTN PkgMinPwrLvl1; + UINTN PkgMaxPwrLvl1; + UINTN ConfigTDPLvl1Ratio; + UINTN PkgTDPLvl1; + UINTN PkgMinPwrLvl2; + UINTN PkgMaxPwrLvl2; + UINTN ConfigTDPLvl2Ratio; + UINTN PkgTDPLvl2; + + // + // Other data + // + UINT32 PlatformRequirement; + UINT64 HealthData; + UINT32 MicrocodeRevision; + UINT64 EnabledThreadCountMsr; +} CPU_MISC_DATA; + +// +// Structure for all collected processor data +// +typedef struct { + CPU_CPUID_DATA CpuidData; + EFI_CPU_PHYSICAL_LOCATION ProcessorLocation; + CPU_MISC_DATA CpuMiscData; + CPU_FEATURE_DATA FeatureData[CpuFeatureMaximum]; + UINT8 PackageIdBitOffset; + BOOLEAN PackageBsp; +} CPU_COLLECTED_DATA; + +#define GET_CPU_MISC_DATA(ProcessorNumber, Item) \ + ((mCpuConfigLibConfigContextBuffer->CollectedDataBuffer[ProcessorNumber]).CpuMiscData.Item) + +// +// Signature for feature list entry +// +#define EFI_CPU_FEATURE_ENTRY_SIGNATURE SIGNATURE_32 ('C', 'f', 't', 'r') + +// +// Node of processor feature list +// +typedef struct { + UINT32 Signature; + CPU_FEATURE_ID FeatureID; + VOID *Attribute; + LIST_ENTRY Link; +} CPU_FEATURE_ENTRY; + +#define CPU_FEATURE_ENTRY_FROM_LINK(link) CR (link, CPU_FEATURE_ENTRY, Link, EFI_CPU_FEATURE_ENTRY_SIGNATURE) + +// +// Definition of Processor Configuration Context Buffer +// +typedef struct { + UINTN NumberOfProcessors; + UINTN BspNumber; + CPU_COLLECTED_DATA *CollectedDataBuffer; + LIST_ENTRY *FeatureLinkListEntry; + CPU_REGISTER_TABLE *PreSmmInitRegisterTable; + CPU_REGISTER_TABLE *RegisterTable; + UINTN *SettingSequence; +} CPU_CONFIG_CONTEXT_BUFFER; + +// +// Structure conveying socket ID configuration information. +// +typedef struct { + UINT32 DefaultSocketId; + UINT32 NewSocketId; +} CPU_SOCKET_ID_INFO; + +extern CPU_CONFIG_CONTEXT_BUFFER *mCpuConfigLibConfigContextBuffer; + +/** + Set feature capability and related attribute. + + This function sets the feature capability and its attribute. + + @param ProcessorNumber Handle number of specified logical processor + @param FeatureID The ID of the feature. + @param Attribute Feature-specific data. + +**/ +VOID +EFIAPI +SetProcessorFeatureCapability ( + IN UINTN ProcessorNumber, + IN CPU_FEATURE_ID FeatureID, + IN VOID *Attribute + ); + +/** + Clears feature capability and related attribute. + + This function clears the feature capability and its attribute. + + @param ProcessorNumber Handle number of specified logical processor + @param FeatureID The ID of the feature. + +**/ +VOID +EFIAPI +ClearProcessorFeatureCapability ( + IN UINTN ProcessorNumber, + IN CPU_FEATURE_ID FeatureID + ); + +/** + Get feature capability and related attribute. + + This function gets the feature capability and its attribute. + + @param ProcessorNumber Handle number of specified logical processor + @param FeatureID The ID of the feature. + @param Attribute Pointer to the output feature-specific data. + + @retval TRUE The feature is supported by the processor + @retval FALSE The feature is not supported by the processor + +**/ +BOOLEAN +EFIAPI +GetProcessorFeatureCapability ( + IN UINTN ProcessorNumber, + IN CPU_FEATURE_ID FeatureID, + OUT VOID **Attribute OPTIONAL + ); + +typedef enum { + BasicCpuidLeaf, + ExtendedCpuidLeaf, + CacheAndTlbCpuidLeafs, + DeterministicCacheParametersCpuidLeafs, + ExtendedTopologyEnumerationCpuidLeafs +} CPUID_TYPE; + +/** + Get the number of CPUID leafs of various types. + + This function get the number of CPUID leafs of various types. + + @param ProcessorNumber Handle number of specified logical processor + @param CpuidType The type of the CPU id. + + @return Maximal index of CPUID instruction for basic leafs. + +**/ +UINTN +EFIAPI +GetNumberOfCpuidLeafs ( + IN UINTN ProcessorNumber, + IN CPUID_TYPE CpuidType + ); + +/** + Get the pointer to specified CPUID leaf. + + This function gets the pointer to specified CPUID leaf. + + @param ProcessorNumber Handle number of specified logical processor + @param Index Index of the CPUID leaf. + + @return Pointer to specified CPUID leaf + +**/ +EFI_CPUID_REGISTER* +EFIAPI +GetProcessorCpuid ( + IN UINTN ProcessorNumber, + IN UINTN Index + ); + +/** + Get the pointer to specified CPUID leaf of cache and TLB parameters. + + This function gets the pointer to specified CPUID leaf of cache and TLB parameters. + + @param ProcessorNumber Handle number of specified logical processor + @param Index Index of the CPUID leaf. + + @return Pointer to specified CPUID leaf. + +**/ +EFI_CPUID_REGISTER* +EFIAPI +GetCacheAndTlbCpuidLeaf ( + IN UINTN ProcessorNumber, + IN UINTN Index + ); + +/** + Get the pointer to specified CPUID leaf of deterministic cache parameters. + + This function gets the pointer to specified CPUID leaf of deterministic cache parameters. + + @param ProcessorNumber Handle number of specified logical processor + @param Index Index of the CPUID leaf. + + @return Pointer to specified CPUID leaf. + +**/ +EFI_CPUID_REGISTER* +EFIAPI +GetDeterministicCacheParametersCpuidLeaf ( + IN UINTN ProcessorNumber, + IN UINTN Index + ); + +/** + Get the pointer to specified CPUID leaf of Extended Topology Enumeration. + + This function gets the pointer to specified CPUID leaf of Extended Topology Enumeration. + + @param ProcessorNumber Handle number of specified logical processor. + @param Index Index of the CPUID leaf. + + @return Pointer to specified CPUID leaf. + +**/ +EFI_CPUID_REGISTER* +EFIAPI +GetExtendedTopologyEnumerationCpuidLeafs ( + IN UINTN ProcessorNumber, + IN UINTN Index + ); + +/** + Get the version information of specified logical processor. + + This function gets the version information of specified logical processor, + including family ID, model ID, stepping ID and processor type. + + @param ProcessorNumber Handle number of specified logical processor + @param DisplayedFamily Pointer to family ID for output + @param DisplayedModel Pointer to model ID for output + @param SteppingId Pointer to stepping ID for output + @param ProcessorType Pointer to processor type for output + +**/ +VOID +EFIAPI +GetProcessorVersionInfo ( + IN UINTN ProcessorNumber, + OUT UINT32 *DisplayedFamily OPTIONAL, + OUT UINT32 *DisplayedModel OPTIONAL, + OUT UINT32 *SteppingId OPTIONAL, + OUT UINT32 *ProcessorType OPTIONAL + ); + +/** + Get initial local APIC ID of specified logical processor + + This function gets initial local APIC ID of specified logical processor. + + @param ProcessorNumber Handle number of specified logical processor + + @return Initial local APIC ID of specified logical processor + +**/ +UINT32 +EFIAPI +GetInitialLocalApicId ( + UINTN ProcessorNumber + ); + +/** + Get the location of specified processor. + + This function gets the location of specified processor, including + package number, core number within package, thread number within core. + + @param ProcessorNumber Handle number of specified logical processor. + @param PackageNumber Pointer to the output package number. + @param CoreNumber Pointer to the output core number. + @param ThreadNumber Pointer to the output thread number. + +**/ +VOID +EFIAPI +GetProcessorLocation ( + IN UINTN ProcessorNumber, + OUT UINT32 *PackageNumber OPTIONAL, + OUT UINT32 *CoreNumber OPTIONAL, + OUT UINT32 *ThreadNumber OPTIONAL + ); + +/** + Get the Feature entry at specified position in a feature list. + + This function gets the Feature entry at specified position in a feature list. + + @param ProcessorNumber Handle number of specified logical processor + @param FeatureIndex The index of the node in feature list. + @param Attribute Pointer to output feature-specific attribute + + @return Feature ID of specified feature. CpuFeatureMaximum means not found + +**/ +CPU_FEATURE_ID +EFIAPI +GetProcessorFeatureEntry ( + IN UINTN ProcessorNumber, + IN UINTN FeatureIndex, + OUT VOID **Attribute OPTIONAL + ); + +/** + Append a feature entry at the end of a feature list. + + This function appends a feature entry at the end of a feature list. + + @param ProcessorNumber Handle number of specified logical processor + @param FeatureID ID of the specified feature. + @param Attribute Feature-specific attribute. + + @retval EFI_SUCCESS This function always return EFI_SUCCESS + +**/ +EFI_STATUS +EFIAPI +AppendProcessorFeatureIntoList ( + IN UINTN ProcessorNumber, + IN CPU_FEATURE_ID FeatureID, + IN VOID *Attribute + ); + +/** + Delete a feature entry in a feature list. + + This function deletes a feature entry in a feature list. + + @param ProcessorNumber Handle number of specified logical processor + @param FeatureIndex The index of the node in feature list. + + @retval EFI_SUCCESS The feature node successfully removed. + @retval EFI_INVALID_PARAMETER Index surpasses the length of list. + +**/ +EFI_STATUS +EFIAPI +DeleteProcessorFeatureFromList ( + IN UINTN ProcessorNumber, + IN UINTN FeatureIndex + ); + +/** + Insert a feature entry into a feature list. + + This function insert a feature entry into a feature list before a node specified by FeatureIndex. + + @param ProcessorNumber Handle number of specified logical processor + @param FeatureIndex The index of the new node in feature list. + @param FeatureID ID of the specified feature. + @param Attribute Feature-specific attribute. + + @retval EFI_SUCCESS The feature node successfully inserted. + @retval EFI_INVALID_PARAMETER Index surpasses the length of list. + +**/ +EFI_STATUS +EFIAPI +InsertProcessorFeatureIntoList ( + IN UINTN ProcessorNumber, + IN UINTN FeatureIndex, + IN CPU_FEATURE_ID FeatureID, + IN VOID *Attribute + ); + +/** + Add an entry in the post-SMM-init register table. + + This function adds an entry in the post-SMM-init register table, with given register type, + register index, bit section and value. + + @param ProcessorNumber Handle number of specified logical processor + @param RegisterType Type of the register to program + @param Index Index of the register to program + @param ValidBitStart Start of the bit section + @param ValidBitLength Length of the bit section + @param Value Value to write + +**/ +VOID +EFIAPI +WriteRegisterTable ( + IN UINTN ProcessorNumber, + IN REGISTER_TYPE RegisterType, + IN UINT32 Index, + IN UINT8 ValidBitStart, + IN UINT8 ValidBitLength, + IN UINT64 Value + ); + +/** + Add an entry in the pre-SMM-init register table. + + This function adds an entry in the pre-SMM-init register table, with given register type, + register index, bit section and value. + + @param ProcessorNumber Handle number of specified logical processor + @param RegisterType Type of the register to program + @param Index Index of the register to program + @param ValidBitStart Start of the bit section + @param ValidBitLength Length of the bit section + @param Value Value to write + +**/ +VOID +EFIAPI +WritePreSmmInitRegisterTable ( + IN UINTN ProcessorNumber, + IN REGISTER_TYPE RegisterType, + IN UINT32 Index, + IN UINT8 ValidBitStart, + IN UINT8 ValidBitLength, + IN UINT64 Value + ); + +/** + Set the sequence of processor setting. + + This function sets the a processor setting at the position in + setting sequence specified by Index. + + @param Index The zero-based index in the sequence. + @param ProcessorNumber Handle number of the processor to set. + + @retval EFI_SUCCESS The sequence successfully modified. + @retval EFI_INVALID_PARAMETER Index surpasses the boundary of sequence. + @retval EFI_NOT_FOUND Processor specified by ProcessorNumber does not exist. + +**/ +EFI_STATUS +SetSettingSequence ( + IN UINTN Index, + IN UINTN ProcessorNumber + ); + +/** + Set PcdCpuCallbackSignal, and then read the value back. + + This function sets PCD entry PcdCpuCallbackSignal. If there is callback + function registered on it, the callback function will be triggered, and + it may change the value of PcdCpuCallbackSignal. This function then reads + the value of PcdCpuCallbackSignal back, the check whether it has been changed. + + @param Value The value to set to PcdCpuCallbackSignal. + + @return The value of PcdCpuCallbackSignal read back. + +**/ +UINT8 +SetAndReadCpuCallbackSignal ( + IN UINT8 Value + ); + +#endif diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/Override/IA32FamilyCpuPkg/Include/Protocol/IntelCpuPcdsSetDone.h b/Silicon/Intel/PurleyRefreshSiliconPkg/Override/IA32FamilyCpuPkg/Include/Protocol/IntelCpuPcdsSetDone.h new file mode 100644 index 0000000000..e21cf0b679 --- /dev/null +++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Override/IA32FamilyCpuPkg/Include/Protocol/IntelCpuPcdsSetDone.h @@ -0,0 +1,18 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _INTEL_CPU_PCDS_SET_DONE_PROTOCOL_H_ +#define _INTEL_CPU_PCDS_SET_DONE_PROTOCOL_H_ + +#define INTEL_CPU_PCDS_SET_DONE_PROTOCOL_GUID \ + { \ + 0xadb7b9e6, 0x70b7, 0x48d4, { 0xb6, 0xa5, 0x18, 0xfa, 0x15, 0xeb, 0xcd, 0x78 } \ + } + +extern EFI_GUID gIntelCpuPcdsSetDoneProtocolGuid; + +#endif -- 2.27.0.windows.1