From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web09.2702.1620795212027889012 for ; Tue, 11 May 2021 21:53:32 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.65, mailfrom: ray.ni@intel.com) IronPort-SDR: 4vAKuts4pM+MyWrdYIKt7JjVei51zBTVa6Srue8AjkqIN9OgvftY9ha1jGxpn5WwlvhV0sz8wC 9qxNu7mk9NLA== X-IronPort-AV: E=McAfee;i="6200,9189,9981"; a="199666940" X-IronPort-AV: E=Sophos;i="5.82,293,1613462400"; d="scan'208";a="199666940" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2021 21:53:30 -0700 IronPort-SDR: oPXRaS3E1zBSgVXRESng9NOeu3CUYAlrc3V6oJuZGCd+63HlHWvikX7A7jsnHTB93/m6EAGBxA JKe3LDxOMnLw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,293,1613462400"; d="scan'208";a="469237118" Received: from ray-dev.ccr.corp.intel.com ([10.239.158.87]) by fmsmga002.fm.intel.com with ESMTP; 11 May 2021 21:53:29 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Cc: Eric Dong , Laszlo Ersek , Rahul Kumar Subject: [PATCH] UefiCpuPkg/PiSmmCpu: Remove hardcode 48 address size limitation Date: Wed, 12 May 2021 12:53:10 +0800 Message-Id: <20210512045310.302-1-ray.ni@intel.com> X-Mailer: git-send-email 2.31.1.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable 5-level paging can be enabled on CPU which supports up to 52 physical address size. But when the feature was enabled, the 48 address size limit was not removed and the 5-level paging testing didn't access address >=3D 2^48. So the issue wasn't detected until recently an address >=3D 2^48 is accessed. Change-Id: Iaedc73be318d4b4122071efc3ba6e967a4b58fc3 Signed-off-by: Ray Ni Cc: Eric Dong Cc: Laszlo Ersek Cc: Rahul Kumar --- UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxe= Smm/MpService.c index fd6583f9d1..89143810b6 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -1887,11 +1887,13 @@ InitializeMpServiceData ( IN UINTN ShadowStackSize=0D )=0D {=0D - UINT32 Cr3;=0D - UINTN Index;=0D - UINT8 *GdtTssTables;=0D - UINTN GdtTableStepSize;=0D - CPUID_VERSION_INFO_EDX RegEdx;=0D + UINT32 Cr3;=0D + UINTN Index;=0D + UINT8 *GdtTssTables;=0D + UINTN GdtTableStepSize;=0D + CPUID_VERSION_INFO_EDX RegEdx;=0D + UINT32 MaxExtendedFunction;=0D + CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize;=0D =0D //=0D // Determine if this CPU supports machine check=0D @@ -1918,9 +1920,17 @@ InitializeMpServiceData ( // Initialize physical address mask=0D // NOTE: Physical memory above virtual address limit is not supported !!= !=0D //=0D - AsmCpuid (0x80000008, (UINT32*)&Index, NULL, NULL, NULL);=0D - gPhyMask =3D LShiftU64 (1, (UINT8)Index) - 1;=0D - gPhyMask &=3D (1ull << 48) - EFI_PAGE_SIZE;=0D + AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedFunction, NULL, NULL, NUL= L);=0D + if (MaxExtendedFunction >=3D CPUID_VIR_PHY_ADDRESS_SIZE) {=0D + AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &VirPhyAddressSize.Uint32, NULL,= NULL, NULL);=0D + } else {=0D + VirPhyAddressSize.Bits.PhysicalAddressBits =3D 36;=0D + }=0D + gPhyMask =3D LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits) = - 1;=0D + //=0D + // Clear the low 12 bits=0D + //=0D + gPhyMask &=3D 0xfffffffffffff000ULL;=0D =0D //=0D // Create page tables=0D --=20 2.31.1.windows.1