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From: "Brijesh Singh" <brijesh.singh@amd.com>
To: devel@edk2.groups.io
Cc: Brijesh Singh <brijesh.singh@amd.com>,
	James Bottomley <jejb@linux.ibm.com>, Min Xu <min.m.xu@intel.com>,
	Jiewen Yao <jiewen.yao@intel.com>,
	Tom Lendacky <thomas.lendacky@amd.com>,
	Jordan Justen <jordan.l.justen@intel.com>,
	Ard Biesheuvel <ardb+tianocore@kernel.org>,
	Laszlo Ersek <lersek@redhat.com>,
	Erdem Aktas <erdemaktas@google.com>,
	Michael D Kinney <michael.d.kinney@intel.com>,
	Liming Gao <gaoliming@byosoft.com.cn>,
	Zhiguang Liu <zhiguang.liu@intel.com>
Subject: [PATCH v2 02/13] MdePkg/Register/Amd: realign macros with more space for future expansion
Date: Wed, 12 May 2021 18:46:04 -0500	[thread overview]
Message-ID: <20210512234615.1726-3-brijesh.singh@amd.com> (raw)
In-Reply-To: <20210512234615.1726-1-brijesh.singh@amd.com>

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275

Version 2 of the GHCB spec introduces several new SNP-specific NAEs.
Unfortunately, the names for those NAEs break the alignment. Add some
white spaces so that the SNP support patches do not break the alignment.

Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
---
 MdePkg/Include/Register/Amd/Fam17Msr.h | 10 +++++-----
 MdePkg/Include/Register/Amd/Ghcb.h     | 12 ++++++------
 2 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/MdePkg/Include/Register/Amd/Fam17Msr.h b/MdePkg/Include/Register/Amd/Fam17Msr.h
index 716d52fd508d..7368ce7af02a 100644
--- a/MdePkg/Include/Register/Amd/Fam17Msr.h
+++ b/MdePkg/Include/Register/Amd/Fam17Msr.h
@@ -53,11 +53,11 @@ typedef union {
   UINT64  GhcbPhysicalAddress;
 } MSR_SEV_ES_GHCB_REGISTER;
 
-#define GHCB_INFO_SEV_INFO                 1
-#define GHCB_INFO_SEV_INFO_GET             2
-#define GHCB_INFO_CPUID_REQUEST            4
-#define GHCB_INFO_CPUID_RESPONSE           5
-#define GHCB_INFO_TERMINATE_REQUEST        256
+#define GHCB_INFO_SEV_INFO                          1
+#define GHCB_INFO_SEV_INFO_GET                      2
+#define GHCB_INFO_CPUID_REQUEST                     4
+#define GHCB_INFO_CPUID_RESPONSE                    5
+#define GHCB_INFO_TERMINATE_REQUEST                 256
 
 #define GHCB_TERMINATE_GHCB                0
 #define GHCB_TERMINATE_GHCB_GENERAL        0
diff --git a/MdePkg/Include/Register/Amd/Ghcb.h b/MdePkg/Include/Register/Amd/Ghcb.h
index ccdb662af7a7..712dc8e769c0 100644
--- a/MdePkg/Include/Register/Amd/Ghcb.h
+++ b/MdePkg/Include/Register/Amd/Ghcb.h
@@ -49,12 +49,12 @@
 //
 // VMG Special Exit Codes
 //
-#define SVM_EXIT_MMIO_READ      0x80000001ULL
-#define SVM_EXIT_MMIO_WRITE     0x80000002ULL
-#define SVM_EXIT_NMI_COMPLETE   0x80000003ULL
-#define SVM_EXIT_AP_RESET_HOLD  0x80000004ULL
-#define SVM_EXIT_AP_JUMP_TABLE  0x80000005ULL
-#define SVM_EXIT_UNSUPPORTED    0x8000FFFFULL
+#define SVM_EXIT_MMIO_READ                      0x80000001ULL
+#define SVM_EXIT_MMIO_WRITE                     0x80000002ULL
+#define SVM_EXIT_NMI_COMPLETE                   0x80000003ULL
+#define SVM_EXIT_AP_RESET_HOLD                  0x80000004ULL
+#define SVM_EXIT_AP_JUMP_TABLE                  0x80000005ULL
+#define SVM_EXIT_UNSUPPORTED                    0x8000FFFFULL
 
 //
 // IOIO Exit Information
-- 
2.17.1


  parent reply	other threads:[~2021-05-12 23:46 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-12 23:46 [PATCH v2 00/13] Add GHCBv2 macro and helpers Brijesh Singh
2021-05-12 23:46 ` [PATCH v2 01/13] MdePkg/Register/Amd: expand the SEV MSR to include the SNP definition Brijesh Singh
2021-05-12 23:46 ` Brijesh Singh [this message]
2021-05-12 23:46 ` [PATCH v2 03/13] MdePkg/Register/Amd: define GHCB macros for hypervisor feature detection Brijesh Singh
2021-05-17 18:19   ` Erdem Aktas
2021-05-12 23:46 ` [PATCH v2 04/13] MdePkg/Register/Amd: define GHCB macro for Register GPA structure Brijesh Singh
2021-05-17 18:25   ` Erdem Aktas
2021-05-18 16:02     ` Laszlo Ersek
2021-05-19  1:09       ` 回复: " gaoliming
2021-05-12 23:46 ` [PATCH v2 05/13] MdePkg/Register/Amd: define GHCB macro for the Page State Change Brijesh Singh
2021-05-17 19:20   ` Erdem Aktas
2021-05-12 23:46 ` [PATCH v2 06/13] MdePkg/Register/Amd: define GHCB macros for SNP AP creation Brijesh Singh
2021-05-17  3:08   ` [edk2-devel] " Laszlo Ersek
2021-05-17  7:39     ` 回复: " gaoliming
2021-05-17 14:17     ` Lendacky, Thomas
2021-05-18 16:00       ` Laszlo Ersek
2021-05-12 23:46 ` [PATCH v2 07/13] MdePkg/BaseLib: add support for PVALIDATE instruction Brijesh Singh
2021-05-17  3:16   ` [edk2-devel] " Laszlo Ersek
2021-05-12 23:46 ` [PATCH v2 08/13] MdePkg/BaseLib: add support for RMPADJUST instruction Brijesh Singh
2021-05-17  3:25   ` [edk2-devel] " Laszlo Ersek
2021-05-12 23:46 ` [PATCH v2 09/13] OvmfPkg/BaseMemEncryptSevLib: introduce MemEncryptSevClearMmioPageEncMask() Brijesh Singh
2021-05-17  3:32   ` [edk2-devel] " Laszlo Ersek
2021-05-12 23:46 ` [PATCH v2 10/13] OvmfPkg/AmdSevDxe: use MemEncryptSevClearMmioPageEncMask() to clear EncMask Brijesh Singh
2021-05-12 23:46 ` [PATCH v2 11/13] OvmfPkg/QemuFlashFvbServicesRuntimeDxe: use Mmio helper to clear enc mask Brijesh Singh
2021-05-12 23:46 ` [PATCH v2 12/13] OvmfPkg/TpmMmioSevDecryptPei: use MemEncryptSevClearMmioPageEncMask() Brijesh Singh
2021-05-12 23:46 ` [PATCH v2 13/13] OvmfPkg/BaseMemEncryptSevLib: remove Flush parameter Brijesh Singh
2021-05-17  3:46   ` [edk2-devel] " Laszlo Ersek

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