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X-MS-Exchange-AntiSpam-MessageData: =?us-ascii?Q?ASQKcQMKL8TOgZfaOiJGzAkL1+amNjxY/OFJ1jsl6wb1HwutZ/0pJTlDZmVW?= =?us-ascii?Q?No+CzQMcVsuBVG+XaeQH0ypW34LWfdnV+j97J9cl2ddpw2NIVV8z4whGdQz9?= =?us-ascii?Q?jhdPchSBKBI5lpGznzhJtL6hhEqLMVr4yQwXh38e+FqikayIPAnlQB4k7IXo?= =?us-ascii?Q?Fdd4bgKhSXubvrqYjh/KXNvjEXWyStzU0XruuqtZFltocEpKZED1SrLFOM6d?= =?us-ascii?Q?ICK3UP9kpgguJMJKbO9JnuE5Dx/uU8VG/VcLwqgRgApbYWdhNqsi3AlRtdS9?= =?us-ascii?Q?bVyw1qiGksfg2OUiuag0vcuX+rvYqJ3YFnfJZkZGQCii9hl1EKGgW17eox2I?= =?us-ascii?Q?xBagm5n9UAdHMQKdaxG+2MwvWiLGTKGSDykc0uT/pkRdoHyi16BHy9FL8zMo?= =?us-ascii?Q?Zxi8gaquCxE+AyozIG0MKpZ44gsnKaCuhdnQvn0WUbt6OrKhKETu8/LJUK1L?= =?us-ascii?Q?M3YP6OoiOEmzgC+XxmrVhDN8y67dn4qfmGp021z4uV0xPDAXGh99RR7jXnPq?= =?us-ascii?Q?y0UAbg2ijlbINtUmRz9rPKkvf6uualu3aEzwXxqCTJ+FQwsXdh9JGZJHaq3h?= =?us-ascii?Q?h8e4vLlkGV3yG5M/1Dqa+d3lHXtVgNEzRbKqomM0DtMtUqmnFS2n8RYA4SXH?= =?us-ascii?Q?Fro/xb+SfAdif28ehKaC/gv0AX3jN97vugE9EJQ35XlV/jGTleabP4dOxUPX?= =?us-ascii?Q?ly4SbsEwirWx6PTnS0xahskKz9b5QDlQ2SpbLLQKeREZLiiDHmxJDNMNE/WQ?= =?us-ascii?Q?f4Mfsd5yrMMwH1/2aT3blXm2fFJL6PGuUAgc1SVtLmBfsqovU0pBINWEO9Ni?= =?us-ascii?Q?R4wnSuz4AyfQmcAKcIOehns6BKaVwBqKTgh36WlL1lCMBrOdc+5jZOVEtYtU?= =?us-ascii?Q?tOZ9v1DQVSgjz3LbjENMkHkvjY8bdLwuFZy5MAVijS59h/UWueDibx+I3NrX?= =?us-ascii?Q?xTvFfM0+TaQANrE2mb7hGa1uyEEdyZgTW2lT65lEmi5OoLObiwBWPDVaUHXG?= =?us-ascii?Q?SLjdvlxUDGPVT4flJQcBSzZKzoSDkRl2awDQKTSjjVm/0OJyOumgm+ddNDO/?= =?us-ascii?Q?lOUhxryCbLpF3zifmRKg5toj3pG6A4GX99EOyhONXcZ3Pfn3iyYIIifOVJNS?= =?us-ascii?Q?6UNOOUKQz93qe4LLnw32k5DvgIbNF3n2nZLS+uzC99w47ZYL+dnsn8T0tgyF?= =?us-ascii?Q?N0tauGobj93P9ddflQRm6F+I9DpNKrNx8Jk7eLaikY6s4464LQZa28yN8wb5?= =?us-ascii?Q?yfC4AoZxW/6qG+YbyoJoIO386jifklfpDh+H0WKz3Na4xgX/Itf7iKBJqURB?= =?us-ascii?Q?UY6BvO/RdBu+hdAS4Vlxr8E2?= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: e6adcae6-544e-49fe-ba53-08d915a03309 X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 May 2021 23:46:44.6311 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: eTaVA67EqnjiEweB5wfzFECU/ueUPpx7ca78OIvfJpgXULzB3eDW833yNUS7ojgCf6XI4CEB9FeQnluuPRojnA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2781 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3275 The RMPADJUST instruction will be used by the SEV-SNP guest to modify the RMP permissions for a guest page. See AMD APM volume 3 for further details. Cc: James Bottomley Cc: Min Xu Cc: Jiewen Yao Cc: Tom Lendacky Cc: Jordan Justen Cc: Ard Biesheuvel Cc: Laszlo Ersek Cc: Erdem Aktas Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Reviewed-by: Laszlo Ersek Reviewed-by: Liming Gao Signed-off-by: Tom Lendacky Signed-off-by: Brijesh Singh --- MdePkg/Library/BaseLib/BaseLib.inf | 1 + MdePkg/Include/Library/BaseLib.h | 35 ++++++++++++++++++++ MdePkg/Include/X64/Nasm.inc | 8 +++++ MdePkg/Library/BaseLib/X64/RmpAdjust.nasm | 40 +++++++++++++++++++++++ 4 files changed, 84 insertions(+) create mode 100644 MdePkg/Library/BaseLib/X64/RmpAdjust.nasm diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/Ba= seLib.inf index 89a52f72c08a..6ccb8997b7e8 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -319,6 +319,7 @@ [Sources.X64] X64/DisablePaging64.nasm X64/Pvalidate.nasm X64/RdRand.nasm + X64/RmpAdjust.nasm X64/XGetBv.nasm X64/XSetBv.nasm X64/VmgExit.nasm diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/Base= Lib.h index a2cd134bea9a..e8eff32716b8 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -4861,6 +4861,41 @@ AsmPvalidate ( IN BOOLEAN Validate, IN PHYSICAL_ADDRESS Address ); + +// +// RDX settings for RMPADJUST +// +#define RMPADJUST_VMPL_MAX 3 +#define RMPADJUST_VMPL_MASK 0xFF +#define RMPADJUST_VMPL_SHIFT 0 +#define RMPADJUST_PERMISSION_MASK_MASK 0xFF +#define RMPADJUST_PERMISSION_MASK_SHIFT 8 +#define RMPADJUST_VMSA_PAGE_BIT BIT16 + +/** + Adjusts the permissions of an SEV-SNP guest page. + + Executes a RMPADJUST instruction with the register state specified by Ra= x, + Rcx, and Rdx. Returns Rax. This function is only available on X64. + + The instruction is available only when CPUID Fn8000_001F_EAX[SNP]=3D1. + + @param[in] Rax The value to load into RAX before executing the RMPADJ= UST + instruction. + @param[in] Rcx The value to load into RCX before executing the RMPADJ= UST + instruction. + @param[in] Rdx The value to load into RDX before executing the RMPADJ= UST + instruction. + + @return Rax +**/ +UINT32 +EFIAPI +AsmRmpAdjust ( + IN UINT64 Rax, + IN UINT64 Rcx, + IN UINT64 Rdx + ); #endif =20 =20 diff --git a/MdePkg/Include/X64/Nasm.inc b/MdePkg/Include/X64/Nasm.inc index 528bb3385609..cfb14edc9449 100644 --- a/MdePkg/Include/X64/Nasm.inc +++ b/MdePkg/Include/X64/Nasm.inc @@ -41,6 +41,14 @@ DB 0xF2, 0x0F, 0x01, 0xFF %endmacro =20 +; +; Macro for the RMPADJUST instruction, defined in AMD APM volume 3. +; NASM feature request URL: https://bugzilla.nasm.us/show_bug.cgi?id=3D339= 2754 +; +%macro RMPADJUST 0 + DB 0xF3, 0x0F, 0x01, 0xFE +%endmacro + ; NASM provides built-in macros STRUC and ENDSTRUC for structure definitio= n. ; For example, to define a structure called mytype containing a longword, ; a word, a byte and a string of bytes, you might code diff --git a/MdePkg/Library/BaseLib/X64/RmpAdjust.nasm b/MdePkg/Library/Bas= eLib/X64/RmpAdjust.nasm new file mode 100644 index 000000000000..c307f64b518a --- /dev/null +++ b/MdePkg/Library/BaseLib/X64/RmpAdjust.nasm @@ -0,0 +1,40 @@ +;-------------------------------------------------------------------------= ---- +; +; Copyright (c) 2021, Advanced Micro Devices, Inc. All rights reserved. +; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; RmpAdjust.Asm +; +; Abstract: +; +; AsmRmpAdjust function +; +; Notes: +; +;-------------------------------------------------------------------------= ---- + +%include "Nasm.inc" + + SECTION .text + +;-------------------------------------------------------------------------= ---- +; UINT32 +; EFIAPI +; AsmRmpAdjust ( +; IN UINT64 Rax, +; IN UINT64 Rcx, +; IN UINT64 Rdx +; ) +;-------------------------------------------------------------------------= ---- +global ASM_PFX(AsmRmpAdjust) +ASM_PFX(AsmRmpAdjust): + mov rax, rcx ; Input Rax is in RCX by calling convention + mov rcx, rdx ; Input Rcx is in RDX by calling convention + mov rdx, r8 ; Input Rdx is in R8 by calling convention + + RMPADJUST + + ; RMPADJUST returns the status in the EAX register. + ret --=20 2.17.1