From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web09.4095.1621157375908360993 for ; Sun, 16 May 2021 02:29:36 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: pranav.madhu@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8AAA31042; Sun, 16 May 2021 02:29:35 -0700 (PDT) Received: from usa.arm.com (a074742.blr.arm.com [10.162.16.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 1E6153F73B; Sun, 16 May 2021 02:29:33 -0700 (PDT) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Sami Mujawar Subject: [edk2-platforms][PATCH V2 07/11] Platform/Sgi: Add SMBIOS Type7 Table Date: Sun, 16 May 2021 14:59:13 +0530 Message-Id: <20210516092917.21124-8-pranav.madhu@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210516092917.21124-1-pranav.madhu@arm.com> References: <20210516092917.21124-1-pranav.madhu@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Add the SMBIOS type 7 table (Cache Information) that includes information about cache levels implemented, cache configuration, ways of associativity and other information related to cache memory installed. Signed-off-by: Pranav Madhu --- Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf | = 1 + Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.h | = 6 + Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c | = 1 + Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c | = 334 ++++++++++++++++++++ 4 files changed, 342 insertions(+) diff --git a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatform= Dxe.inf b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe= .inf index 4652a9c62b88..ee00b773912b 100644 --- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf +++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf @@ -19,6 +19,7 @@ Type1SystemInformation.c Type3SystemEnclosure.c Type4ProcessorInformation.c + Type7CacheInformation.c =20 [Packages] ArmPkg/ArmPkg.dec diff --git a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatform= Dxe.h b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.h index 8a9be0cfc4c8..6f3ad29f0797 100644 --- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.h +++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.h @@ -35,6 +35,12 @@ InstallProcessorInformation ( IN EFI_SMBIOS_PROTOCOL *Smbios ); =20 +EFI_STATUS +EFIAPI +InstallCacheInformation ( + IN EFI_SMBIOS_PROTOCOL *Smbios + ); + enum SMBIOS_REFRENCE_HANDLES { SMBIOS_HANDLE_ENCLOSURE =3D 0x1000, SMBIOS_HANDLE_CLUSTER1, diff --git a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatform= Dxe.c b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c index 269bd0f9d843..62d0f5ce8033 100644 --- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c +++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c @@ -30,6 +30,7 @@ ARM_RD_SMBIOS_TABLE_INSTALL_FPTR mSmbiosTableList[] =3D= { &InstallSystemInformation, &InstallSystemEnclosure, &InstallProcessorInformation, + &InstallCacheInformation, }; =20 /** diff --git a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInfo= rmation.c b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInfor= mation.c new file mode 100644 index 000000000000..8b42ed3d622c --- /dev/null +++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation= .c @@ -0,0 +1,334 @@ +/** @file + SMBIOS Type 7 (Cache information) table for ARM RD platforms. + + This file installs SMBIOS Type 7 (Cache information) table for Arm's + Reference Design platforms. It includes information about cache levels + implemented, cache configuration, ways of associativity and other + information related to cache memory installed. + + Copyright (c) 2021, ARM Limited. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + - SMBIOS Reference Specification 3.4.0, Chapter 7.8 +**/ + +#include +#include + +#include "SgiPlatform.h" +#include "SmbiosPlatformDxe.h" + +#define TYPE7_STRINGS \ + "L1 Instruction\0" /* L1I */ \ + "L1 Data\0" /* L1D */ \ + "L2\0" /* L2 */ \ + "L3\0" /* L3 */ \ + "SLC\0" /* L4 */ + +/* SMBIOS Type7 structure */ +#pragma pack(1) +struct ArmRdSmbiosType7 { + SMBIOS_TABLE_TYPE7 Base; + UINT8 Strings[sizeof (TYPE7_STRINGS)]; +} ARM_TYPE7; +#pragma pack() + +/* Cache information */ +static struct ArmRdSmbiosType7 mArmRdSmbiosType7[] =3D { + { // Entry 0, L1 instruction cache + { + { + // SMBIOS header + EFI_SMBIOS_TYPE_CACHE_INFORMATION, // Type 7 + sizeof (SMBIOS_TABLE_TYPE7), // Length + SMBIOS_HANDLE_L1I_CACHE, // Handle number + }, + 1, + ( + (1 << 8) | // Write-back + (1 << 7) | // Cache enabled + (1 << 3) | // Cache socketed + 0x0 // Cache level 1 + ), + 0xFFFF, // Uses Maximum cache size 2 field + 0xFFFF, // Uses Installed cache size 2 field + {0, 1}, // Supported SRAM type unknown + {0, 1}, // Current SRAM type unknown + 0, // Cache Speed Unknown + 0x02, // Error correction type unknown + 0x03, // Instruction cache + 0, // Associativity, update dynamically + 0, // Maximum cache size 2, update dynamically + 0 // Installed cache size 2, update dynamically + }, + // Text strings (unformatted area) + TYPE7_STRINGS + }, + { // Entry 1, L1 data cache + { + { + // SMBIOS header + EFI_SMBIOS_TYPE_CACHE_INFORMATION, // Type 7 + sizeof (SMBIOS_TABLE_TYPE7), // Length + SMBIOS_HANDLE_L1D_CACHE, // Handle number + }, + 2, + ( + (1 << 8) | // Write-back + (1 << 7) | // Cache enabled + (1 << 3) | // Cache socketed + 0x0 // Cache level 1 + ), + 0xFFFF, // Uses Maximum cache size 2 field + 0xFFFF, // Uses Installed cache size 2 field + {0, 1}, // Supported SRAM type unknown + {0, 1}, // Current SRAM type unknown + 0, // Cache Speed Unknown + 0x02, // Error correction type unknown + 0x04, // Data cache + 0, // Associativity, update dynamically + 0, // Maximum cache size 2, update dynamically + 0 // Installed cache size 2, update dynamically + }, + // Text strings (unformatted area) + TYPE7_STRINGS + }, + { // Entry 2, L2 cache + { + { + // SMBIOS header + EFI_SMBIOS_TYPE_CACHE_INFORMATION, // Type 7 + sizeof (SMBIOS_TABLE_TYPE7), // Length + SMBIOS_HANDLE_L2_CACHE, // Handle number + }, + 3, + ( + (1 << 8) | // Write-back + (1 << 7) | // Cache enabled + (1 << 3) | // Cache socketed + 0x1 // Cache level 2 + ), + 0xFFFF, // Uses Maximum cache size 2 field + 0xFFFF, // Uses Installed cache size 2 field + {0, 1}, // Supported SRAM type unknown + {0, 1}, // Current SRAM type unknown + 0, // Cache Speed Unknown + 0x02, // Error correction type unknown + 0x05, // Unified cache + 0, // Associativity, update dynamically + 0, // Maximum cache size 2, update dynamically + 0 // Installed cache size 2, update dynamically + }, + // Text strings (unformatted area) + TYPE7_STRINGS + }, + { // Entry 3, L3 cache + { + { + // SMBIOS header + EFI_SMBIOS_TYPE_CACHE_INFORMATION, // Type 7 + sizeof (SMBIOS_TABLE_TYPE7), // Length + SMBIOS_HANDLE_L3_CACHE, // Handle number + }, + 4, + ( + (1 << 8) | // Write-back + (1 << 7) | // Cache enabled + (1 << 3) | // Cache socketed + 0x2 // Cache level 3 + ), + 0xFFFF, // Uses Maximum cache size 2 field + 0xFFFF, // Uses Installed cache size 2 field + {0, 1}, // Supported SRAM type unknown + {0, 1}, // Current SRAM type unknown + 0, // Cache Speed Unknown + 0x02, // Error correction type unknown + 0x05, // Unified cache + 0, // Associativity, update dynamically + 0, // Maximum cache size 2, update dynamically + 0 // Installed cache size 2, update dynamically + }, + // Text strings (unformatted area) + TYPE7_STRINGS + }, + { // Entry 4, SLC Cache + { + { + // SMBIOS header + EFI_SMBIOS_TYPE_CACHE_INFORMATION, // Type 7 + sizeof (SMBIOS_TABLE_TYPE7), // Length + SMBIOS_HANDLE_L4_CACHE, // Handle number + }, + 5, + ( + (1 << 8) | // Write-back + (1 << 7) | // Cache enabled + (1 << 3) | // Cache socketed + 0x3 // Cache level 4 + ), + 0xFFFF, // Uses Maximum cache size 2 field + 0xFFFF, // Uses Installed cache size 2 field + {0, 1}, // Supported SRAM type unknown + {0, 1}, // Current SRAM type unknown + 0, // Cache Speed Unknown + 0x02, // Error correction type unknown + 0x05, // Unified cache + 0, // Associativity, update dynamically + 0, // Maximum cache size 2, update dynamically + 0 // Installed cache size 2, update dynamically + }, + // Text strings (unformatted area) + TYPE7_STRINGS + } +}; + +/** + Install SMBIOS Cache information Table + + Install the SMBIOS Cache information (type 7) table for Arm's Referenc= e + Design platforms. + + @param[in] Smbios SMBIOS protocol. + + @retval EFI_SUCCESS Record was added. + @retval EFI_NOT_FOUND Unknown product id. + @retval EFI_OUT_OF_RESOURCES Record was not added. + @retval EFI_ALREADY_STARTED The SmbiosHandle passed in is already in= use. +**/ +EFI_STATUS +InstallCacheInformation ( + IN EFI_SMBIOS_PROTOCOL *Smbios + ) +{ + EFI_STATUS Status; + EFI_SMBIOS_HANDLE SmbiosHandle; + UINT8 CacheIdx; + + /* Update the cache attributes based on the product */ + switch (SgiGetProductId ()) { + case Sgi575: + /* L1 instruction cache */ + mArmRdSmbiosType7[0].Base.MaximumCacheSize2 =3D 64; // 64KB + mArmRdSmbiosType7[0].Base.InstalledSize2 =3D 64; // 64KB + mArmRdSmbiosType7[0].Base.Associativity =3D CacheAssociativity4Way; + /* L1 data cache */ + mArmRdSmbiosType7[1].Base.MaximumCacheSize2 =3D 64; // 64KB + mArmRdSmbiosType7[1].Base.InstalledSize2 =3D 64; // 64KB + mArmRdSmbiosType7[1].Base.Associativity =3D CacheAssociativity16Way; + /* L2 cache */ + mArmRdSmbiosType7[2].Base.MaximumCacheSize2 =3D 512; // 512KB + mArmRdSmbiosType7[2].Base.InstalledSize2 =3D 512; // 512KB + mArmRdSmbiosType7[2].Base.Associativity =3D CacheAssociativity8Way; + /* L3 cache */ + mArmRdSmbiosType7[3].Base.MaximumCacheSize2 =3D 2048; // 2MB + mArmRdSmbiosType7[3].Base.InstalledSize2 =3D 2048; // 2MB + mArmRdSmbiosType7[3].Base.Associativity =3D CacheAssociativity16Way; + break; + case RdN1Edge: + case RdN1EdgeX2: + /* L1 instruction cache */ + mArmRdSmbiosType7[0].Base.MaximumCacheSize2 =3D 64; // 64KB + mArmRdSmbiosType7[0].Base.InstalledSize2 =3D 64; // 64KB + mArmRdSmbiosType7[0].Base.Associativity =3D CacheAssociativity4Way; + /* L1 data cache */ + mArmRdSmbiosType7[1].Base.MaximumCacheSize2 =3D 64; // 64KB + mArmRdSmbiosType7[1].Base.InstalledSize2 =3D 64; // 64KB + mArmRdSmbiosType7[1].Base.Associativity =3D CacheAssociativity4Way; + /* L2 cache */ + mArmRdSmbiosType7[2].Base.MaximumCacheSize2 =3D 512; // 512KB + mArmRdSmbiosType7[2].Base.InstalledSize2 =3D 512; // 512KB + mArmRdSmbiosType7[2].Base.Associativity =3D CacheAssociativity8Way; + /* L3 cache */ + mArmRdSmbiosType7[3].Base.MaximumCacheSize2 =3D 2048; // 2MB + mArmRdSmbiosType7[3].Base.InstalledSize2 =3D 2048; // 2MB + mArmRdSmbiosType7[3].Base.Associativity =3D CacheAssociativity16Way; + /* System level cache */ + mArmRdSmbiosType7[4].Base.MaximumCacheSize2 =3D 8192; // 8MB SLC pe= r chip + mArmRdSmbiosType7[4].Base.InstalledSize2 =3D 8192; // 8MB SLC pe= r chip + mArmRdSmbiosType7[4].Base.Associativity =3D CacheAssociativity16Way; + break; + case RdE1Edge: + /* L1 instruction cache */ + mArmRdSmbiosType7[0].Base.MaximumCacheSize2 =3D 32; // 32KB + mArmRdSmbiosType7[0].Base.InstalledSize2 =3D 32; // 32KB + mArmRdSmbiosType7[0].Base.Associativity =3D CacheAssociativity4Way; + /* L1 data cache */ + mArmRdSmbiosType7[1].Base.MaximumCacheSize2 =3D 32; // 32KB + mArmRdSmbiosType7[1].Base.InstalledSize2 =3D 32; // 32KB + mArmRdSmbiosType7[1].Base.Associativity =3D CacheAssociativity4Way; + /* L2 cache */ + mArmRdSmbiosType7[2].Base.MaximumCacheSize2 =3D 256; // 256KB + mArmRdSmbiosType7[2].Base.InstalledSize2 =3D 256; // 256KB + mArmRdSmbiosType7[2].Base.Associativity =3D CacheAssociativity4Way; + /* L3 cache */ + mArmRdSmbiosType7[3].Base.MaximumCacheSize2 =3D 2048; // 2MB + mArmRdSmbiosType7[3].Base.InstalledSize2 =3D 2048; // 2MB + mArmRdSmbiosType7[3].Base.Associativity =3D CacheAssociativity16Way; + /* System level cache */ + mArmRdSmbiosType7[4].Base.MaximumCacheSize2 =3D 8192; // 8MB SLC + mArmRdSmbiosType7[4].Base.InstalledSize2 =3D 8192; // 8MB SLC + mArmRdSmbiosType7[4].Base.Associativity =3D CacheAssociativity16Way; + break; + case RdV1: + case RdV1Mc: + /* L1 instruction cache */ + mArmRdSmbiosType7[0].Base.MaximumCacheSize2 =3D 64; // 64KB + mArmRdSmbiosType7[0].Base.InstalledSize2 =3D 64; // 64KB + mArmRdSmbiosType7[0].Base.Associativity =3D CacheAssociativity4Way; + /* L1 data cache */ + mArmRdSmbiosType7[1].Base.MaximumCacheSize2 =3D 64; // 64KB + mArmRdSmbiosType7[1].Base.InstalledSize2 =3D 64; // 64KB + mArmRdSmbiosType7[1].Base.Associativity =3D CacheAssociativity4Way; + /* L2 cache */ + mArmRdSmbiosType7[2].Base.MaximumCacheSize2 =3D 1024; // 1MB + mArmRdSmbiosType7[2].Base.InstalledSize2 =3D 1024; // 1MB + mArmRdSmbiosType7[2].Base.Associativity =3D CacheAssociativity8Way; + /* System level cache */ + mArmRdSmbiosType7[4].Base.MaximumCacheSize2 =3D 16384; // 16MB SLC p= er chip + mArmRdSmbiosType7[4].Base.InstalledSize2 =3D 16384; // 16MB SLC p= er chip + mArmRdSmbiosType7[4].Base.Associativity =3D CacheAssociativity16Way; + break; + case RdN2: + /* L1 instruction cache */ + mArmRdSmbiosType7[0].Base.MaximumCacheSize2 =3D 64; // 64KB + mArmRdSmbiosType7[0].Base.InstalledSize2 =3D 64; // 64KB + mArmRdSmbiosType7[0].Base.Associativity =3D CacheAssociativity4Way; + /* L1 data cache */ + mArmRdSmbiosType7[1].Base.MaximumCacheSize2 =3D 64; // 64KB + mArmRdSmbiosType7[1].Base.InstalledSize2 =3D 64; // 64KB + mArmRdSmbiosType7[1].Base.Associativity =3D CacheAssociativity4Way; + /* L2 cache */ + mArmRdSmbiosType7[2].Base.MaximumCacheSize2 =3D 1024; // 1MB + mArmRdSmbiosType7[2].Base.InstalledSize2 =3D 1024; // 1MB + mArmRdSmbiosType7[2].Base.Associativity =3D CacheAssociativity8Way; + /* System level cache */ + mArmRdSmbiosType7[4].Base.MaximumCacheSize2 =3D 32768; // 32MB SLC + mArmRdSmbiosType7[4].Base.InstalledSize2 =3D 32768; // 32MB SLC + mArmRdSmbiosType7[4].Base.Associativity =3D CacheAssociativity16Way; + break; + } + + /* Install valid cache information tables */ + for (CacheIdx =3D 0; CacheIdx < ARRAY_SIZE (mArmRdSmbiosType7); CacheI= dx++) { + if (mArmRdSmbiosType7[CacheIdx].Base.MaximumCacheSize2 =3D=3D 0) { + continue; + } + + SmbiosHandle =3D ((EFI_SMBIOS_TABLE_HEADER *)&mArmRdSmbiosType7[Cach= eIdx])->Handle; + Status =3D Smbios->Add ( + Smbios, + NULL, + &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER *)&mArmRdSmbiosType7[Cac= heIdx] + ); + if (Status !=3D EFI_SUCCESS) { + DEBUG (( + DEBUG_ERROR, + "SMBIOS: Failed to install Type7 SMBIOS table.\n" + )); + } + } + + return Status; +} --=20 2.17.1