From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mx.groups.io with SMTP id smtpd.web11.6941.1621396826747902658 for ; Tue, 18 May 2021 21:00:26 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="body hash did not verify" header.i=@linux.microsoft.com header.s=default header.b=cD6tHYDl; spf=pass (domain: linux.microsoft.com, ip: 13.77.154.182, mailfrom: mikuback@linux.microsoft.com) Received: from localhost.localdomain (unknown [167.220.2.74]) by linux.microsoft.com (Postfix) with ESMTPSA id 7BDC120B7178; Tue, 18 May 2021 21:00:26 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 7BDC120B7178 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1621396826; bh=8R5cDv6omkhmDgC0OydGBrIeXa/CS5y/DFszUa+Uf5U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cD6tHYDlYe53z6g7PvX+l2WFEWQS1yWqrwDnNQHXTGmJPUpMpdkX7EgIpjZ4geGuX hwb7jHTDef5KtDbzLn5CR5VyQmXkwU18Usy/UB4jIIJsZBY1s4ZEXZC/XWZzMniiuh UEv1abWnsT523yKuTw0GK3rksq5aCCFnWDUY2sRI= From: "Michael Kubacki" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Rangasai V Chaganty , Deepika Kethi Reddy , Kathappan Esakkithevar Subject: [edk2-platforms][PATCH v2 11/35] CometlakeOpenBoardPkg: Use IntelSiliconPkg BIOS area and ucode PCDs Date: Tue, 18 May 2021 20:59:23 -0700 Message-Id: <20210519035947.1234-12-mikuback@linux.microsoft.com> X-Mailer: git-send-email 2.28.0.windows.1 In-Reply-To: <20210519035947.1234-1-mikuback@linux.microsoft.com> References: <20210519035947.1234-1-mikuback@linux.microsoft.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Michael Kubacki REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3307 Updates PCDs to use the IntelSiliconPkg PCD tokenspace now that the PCDs are declared in IntelSiliconPkg.dec. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Rangasai V Chaganty Cc: Deepika Kethi Reddy Cc: Kathappan Esakkithevar Signed-off-by: Michael Kubacki --- Platform/Intel/CometlakeOpenBoardPkg/BiosInfo/BiosInfo.inf = | 4 +-- Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Fdf/FlashMapI= nclude.fdf | 4 +-- Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.fdf = | 36 ++++++++++---------- Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.= inf | 4 +-- 4 files changed, 24 insertions(+), 24 deletions(-) diff --git a/Platform/Intel/CometlakeOpenBoardPkg/BiosInfo/BiosInfo.inf b= /Platform/Intel/CometlakeOpenBoardPkg/BiosInfo/BiosInfo.inf index 9208aeda5d2a..6ca0ada751f6 100644 --- a/Platform/Intel/CometlakeOpenBoardPkg/BiosInfo/BiosInfo.inf +++ b/Platform/Intel/CometlakeOpenBoardPkg/BiosInfo/BiosInfo.inf @@ -36,8 +36,8 @@ [Packages] MinPlatformPkg/MinPlatformPkg.dec =20 [Pcd] - gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ## CON= SUMES - gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ## CON= SUMES + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ## CON= SUMES + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ## CON= SUMES =20 [Sources] BiosInfo.c diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/F= df/FlashMapInclude.fdf b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeUR= vp/Include/Fdf/FlashMapInclude.fdf index d9959a79d0bb..7d2f4b2c0cb2 100644 --- a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Fdf/Flas= hMapInclude.fdf +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Fdf/Flas= hMapInclude.fdf @@ -34,8 +34,8 @@ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize =3D = 0x00190000 # SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset =3D = 0x00320000 # Flash addr (0xFFB20000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize =3D = 0x00170000 # -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D = 0x00490000 # Flash addr (0xFFC90000) -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D = 0x000B0000 # +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D = 0x00490000 # Flash addr (0xFFC90000) +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D = 0x000B0000 # SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset =3D = 0x00540000 # Flash addr (0xFFD40000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize =3D = 0x00070000 # SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset =3D = 0x005B0000 # Flash addr (0xFFDB0000) diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoard= Pkg.fdf b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg= .fdf index 795cc0da75d8..6397d80d3895 100644 --- a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.fdf +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.fdf @@ -31,8 +31,8 @@ [FD.CometlakeURvp] # assigned with PCD values. Instead, it uses the definitions for its var= iety, which # are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and FLASH_NUM_BLOCKS. # -BaseAddress =3D $(FLASH_BASE) | gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAd= dress #The base address of the FLASH Device. -Size =3D $(FLASH_SIZE) | gSiPkgTokenSpaceGuid.PcdBiosSize = #The size in bytes of the FLASH Device +BaseAddress =3D $(FLASH_BASE) | gIntelSiliconPkgTokenSpaceGuid.PcdBios= AreaBaseAddress #The base address of the FLASH Device. +Size =3D $(FLASH_SIZE) | gIntelSiliconPkgTokenSpaceGuid.PcdBios= Size #The size in bytes of the FLASH Device ErasePolarity =3D 1 BlockSize =3D $(FLASH_BLOCK_SIZE) NumBlocks =3D $(FLASH_NUM_BLOCKS) @@ -43,21 +43,21 @@ [FD.CometlakeURvp] # Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase, because ma= cro expression is not supported. # So, PlatformSecLib uses PcdBiosAreaBaseAddress + PcdNemCodeCacheBase t= o get the real CodeCache base address. SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase =3D $(gMinPlatformPkgTokenS= paceGuid.PcdFlashFvPreMemoryOffset) -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D $(gSiPkgTokenSpaceG= uid.PcdBiosAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvO= ffset) -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D $(gSiPkgTokenSpaceG= uid.PcdFlashMicrocodeFvSize) -SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gSiPkgTo= kenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 -SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(gSiPk= gTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60 +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D $(gIntelS= iliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gIntelSiliconPkgToken= SpaceGuid.PcdFlashMicrocodeFvOffset) +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D $(gIntelS= iliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gIntelSi= liconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(gInte= lSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60 SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv =3D 0x60 -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D gSiPkgT= okenSpaceGuid.PcdFlashMicrocodeFvBase -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D gSiPkgT= okenSpaceGuid.PcdFlashMicrocodeFvSize -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D gSiPkgT= okenSpaceGuid.PcdFlashMicrocodeFvOffset -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =3D gSiPkgT= okenSpaceGuid.PcdBiosAreaBaseAddress -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =3D gSiPkgT= okenSpaceGuid.PcdBiosSize -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D $(gSiPk= gTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid= .PcdFlashFvFspTOffset) -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D $(gSiPk= gTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid= .PcdFlashFvFspMOffset) -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D $(gSiPk= gTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid= .PcdFlashFvFspSOffset) -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D gSiPkgT= okenSpaceGuid.PcdBiosAreaBaseAddress -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D gSiPkgT= okenSpaceGuid.PcdBiosSize +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D gIntelS= iliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D gIntelS= iliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D gIntelS= iliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =3D gIntelS= iliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =3D gIntelS= iliconPkgTokenSpaceGuid.PcdBiosSize +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D $(gInte= lSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvFspTOffset) +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D $(gInte= lSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvFspMOffset) +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D $(gInte= lSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvFspSOffset) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D gIntelS= iliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D gIntelS= iliconPkgTokenSpaceGuid.PcdBiosSize ########################################################################= ######## # # Following are lists of FD Region layout which correspond to the locati= ons of different @@ -153,8 +153,8 @@ [FD.CometlakeURvp] gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvPostMemorySize FV =3D FvPostMemory =20 -gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGuid.PcdF= lashMicrocodeFvSize -gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid.PcdFla= shMicrocodeFvSize +gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gIntelSiliconPk= gTokenSpaceGuid.PcdFlashMicrocodeFvSize +gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gIntelSiliconPkgT= okenSpaceGuid.PcdFlashMicrocodeFvSize #Microcode FV =3D FvMicrocode =20 diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/Po= licyInitDxe.inf b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitD= xe/PolicyInitDxe.inf index 1d09b990b163..abb79c111e0b 100644 --- a/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyIni= tDxe.inf +++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyIni= tDxe.inf @@ -47,8 +47,8 @@ [Packages] =20 [Pcd] gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress = ## CONSUMES - gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = ## CONSUMES - gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = ## CONSUMES + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = ## CONSUMES + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = ## CONSUMES gCometlakeOpenBoardPkgTokenSpaceGuid.PcdIntelGopEnable gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPlatformFlavor gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPlatformType --=20 2.28.0.windows.1